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1. 发明申请

US20110208904A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110208904A1
公开(公告)日：2011-08-25
申请号：US13099720
申请日：2011-05-03
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G06F12/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译：半导体器件包括非易失性存储器，具有包含1比特双胞格的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并且具有不同的保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。布置构成双胞胎的两个存储单元以保存不同的数据。因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。因此，这种差异的差分放大使得能够获得正确的存储信息。因此，提高了电可重写非易失性存储单元的保持性能。

2. 发明申请

US20100080058A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100080058A1
公开(公告)日：2010-04-01
申请号：US12630295
申请日：2009-12-03
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G11C16/26 , G11C16/04
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译：半导体器件包括非易失性存储器，具有包含1比特双胞胞的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并具有不同的保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。布置构成双胞胎的两个存储单元以保存不同的数据。因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。因此，这种差异的差分放大使得能够获得正确的存储信息。因此，提高了电可重写非易失性存储单元的保持性能。

3. 发明申请

US20080089146A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080089146A1
公开(公告)日：2008-04-17
申请号：US11869144
申请日：2007-10-09
申请人： Masamichi FUJITO , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi FUJITO , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G11C7/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译：半导体器件包括非易失性存储器，具有包含1比特双胞格的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并且具有不同的保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。布置构成双胞胎的两个存储单元以保存不同的数据。因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。因此，这种差异的差分放大使得能够获得正确的存储信息。因此，提高了电可重写非易失性存储单元的保持性能。

4. 发明授权

US07080185B2 Bus control device altering drive capability according to condition 失效
标题翻译：总线控制装置根据条件改变驱动能力
公开(公告)号：US07080185B2
公开(公告)日：2006-07-18
申请号：US10295916
申请日：2002-11-18
申请人： Takashi Kurafuji
发明人： Takashi Kurafuji
IPC分类号： G06F13/14 , H03F3/00 , H01L25/00 , H03K19/0175
CPC分类号： G06F1/3203 , G06F1/3253 , Y02D10/151
摘要： An access destination determining section determines whether an access is directed to region 1 or region 2. A region 1 drive capability register and a region 2 drive capability register set drive capabilities of output buffers when accesses to region 1 and region 2 generate, respectively. For example, if “1” is set to region 1 drive capability register, when an access to region 1 generates, a Buf2 output enable signal is output at high level to enable outputs of Buf2s. Therefore, a drive capability of a bus can be altered according to a region to which an access is made by a CPU or the like, thereby enabling prevention of unnecessary power consumption and generation of noise.
摘要翻译：访问目的地确定部分确定访问是指向区域1还是区域2。区域1驱动能力寄存器和区域2驱动能力寄存器分别设置对区域1和区域2的访问时输出缓冲器的驱动能力。例如，如果将“1”设置为区域1驱动能力寄存器，当访问区域1产生时，Buf 2输出使能信号以高电平输出以使能Buf 2s的输出。因此，可以根据由CPU等进行访问的区域来改变总线的驱动能力，从而能够防止不必要的电力消耗和噪声的产生。

5. 发明授权

US08144518B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08144518B2
公开(公告)日：2012-03-27
申请号：US13099720
申请日：2011-05-03
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G11C16/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译：半导体器件包括非易失性存储器，具有包含1比特双胞胞的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并具有不同的保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。布置构成双胞胎的两个存储单元以保存不同的数据。因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。因此，这种差异的差分放大使得能够获得正确的存储信息。因此，提高了电可重写非易失性存储单元的保持性能。

6. 发明授权

US07646642B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07646642B2
公开(公告)日：2010-01-12
申请号：US11869144
申请日：2007-10-09
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G11C16/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译：半导体器件包括非易失性存储器，具有包含1比特双胞胞的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并具有不同的保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。布置构成双胞胎的两个存储单元以保存不同的数据。因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。因此，这种差异的差分放大使得能够获得正确的存储信息。因此，提高了电可重写非易失性存储单元的保持性能。

7. 发明授权

US06816983B2 Microprocessor internally provided with test circuit 有权
标题翻译：微处理器内部提供测试电路
公开(公告)号：US06816983B2
公开(公告)日：2004-11-09
申请号：US09785466
申请日：2001-02-20
申请人： Takashi Kurafuji
发明人： Takashi Kurafuji
IPC分类号： G06F1100
CPC分类号： G06F11/2236
摘要： A microprocessor includes: a memory storing a program and various data; a processor core executing the program stored in the memory; an external bus interface serving as an interface portion of an external bus connected to an external device; a test circuit receiving a program counter value of an instruction to be executed by the processor core for outputting a test event signal for testing the microprocessor in synchronization with an operation timing of the processor core; a test event signal output terminal for outputting the test event signal to an external portion of the microprocessor, and an external event request signal input terminal provided for applying the processor core an external event request signal used by the external device to notify an event request with respect to the processor core.
摘要翻译：微处理器包括：存储程序和各种数据的存储器; 执行存储在存储器中的程序的处理器核心; 外部总线接口，用作连接到外部设备的外部总线的接口部分; 接收由处理器核心执行的指令的程序计数器值的测试电路，用于与处理器核心的操作定时同步地输出用于测试微处理器的测试事件信号; 测试事件信号输出端，用于将测试事件信号输出到微处理器的外部;以及外部事件请求信号输入端，用于将处理器核应用于由外部设备使用的外部事件请求信号以通知事件请求尊重处理器核心。

8. 发明授权

US07957195B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07957195B2
公开(公告)日：2011-06-07
申请号：US12630295
申请日：2009-12-03
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G11C16/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译：半导体器件包括非易失性存储器，具有包含1比特双胞胞的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并具有不同的保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。布置构成双胞胎的两个存储单元以保存不同的数据。因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。因此，这种差异的差分放大使得能够获得正确的存储信息。因此，提高了电可重写非易失性存储单元的保持性能。

9. 发明授权

US06584528B1 Microprocessor allocating no wait storage of variable capacity to plurality of resources, and memory device therefor 失效
标题翻译：微处理器不分配可变容量的等待存储到多个资源，以及其存储器件
公开(公告)号：US06584528B1
公开(公告)日：2003-06-24
申请号：US09488784
申请日：2000-01-21
申请人： Takashi Kurafuji , Akira Yamada
发明人： Takashi Kurafuji , Akira Yamada
IPC分类号： G06F1200
CPC分类号： G06F13/4022 , G06F13/1647
摘要： A microprocessor includes a first bus and a second bus capable of operating simultaneously, a single port memory divided into a plurality of banks, a bus switch circuit provided between the plurality of banks and the first and second buses, and a processor core connected to the first and second buses and the single port memory. The bus switch circuit may be controlled statically, independent of activities on the buses, or may be controlled dynamically according to the activities.
摘要翻译：微处理器包括能够同时工作的第一总线和第二总线，分成多个存储体的单端口存储器，设置在多个存储体之间的总线开关电路和第一和第二总线;以及处理器核心，第一和第二巴士和单口记忆。总线开关电路可以静态地控制，独立于总线上的活动，或者可以根据活动动态地控制。

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