专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

IL254101A Semiconductor memory device 未知
公开(公告)号：IL254101A
公开(公告)日：2022-02-01
申请号：IL25410117
申请日：2017-08-22
申请人： FLOADIA CORP , HIDEO KASAI , YASUHIRO TANIGUCHI , YASUHIKO KAWASHIMA , RYOTARO SAKURAI , YUTAKA SHINAGAWA , TATSURO TOYA , TAKANORI YAMAGUCHI , FUKUO OWADA , SHINJI YOSHIDA , TERUO HATADA , SATOSHI NODA , TAKAFUMI KATO , TETSUYA MURAYA , KOSUKE OKUYAMA
发明人： HIDEO KASAI , YASUHIRO TANIGUCHI , YASUHIKO KAWASHIMA , RYOTARO SAKURAI , YUTAKA SHINAGAWA , TATSURO TOYA , TAKANORI YAMAGUCHI , FUKUO OWADA , SHINJI YOSHIDA , TERUO HATADA , SATOSHI NODA , TAKAFUMI KATO , TETSUYA MURAYA , KOSUKE OKUYAMA
IPC分类号： H01L23/525 , G11C17/16 , H01L27/10 , H01L27/112
摘要： In a semiconductor memory device (1), voltage application from a memory gate electrode (G) of the memory capacitor (4) to a word line can be blocked by a rectifier element (3) depending on values of voltages applied to the memory gate electrode (G) and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device (1), for example, each bit line contact (BC15) is shared by four anti-fuse memories (2a 6 , 2a 7 , 2a 10 , and 2a 11 ) adjacent to each other and each word line contact (WC12) is shared by four anti-fuse memories (2a 3 , 2a 4 , 2a 7 , and 2a 8 ) adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.

2. 发明专利

IL254101D0 Semiconductor memory device 未知
公开(公告)号：IL254101D0
公开(公告)日：2017-10-31
申请号：IL25410117
申请日：2017-08-22
申请人： FLOADIA CORP , HIDEO KASAI , YASUHIRO TANIGUCHI , YASUHIKO KAWASHIMA , RYOTARO SAKURAI , YUTAKA SHINAGAWA , TATSURO TOYA , TAKANORI YAMAGUCHI , FUKUO OWADA , SHINJI YOSHIDA , TERUO HATADA , SATOSHI NODA , TAKAFUMI KATO , TETSUYA MURAYA , KOSUKE OKUYAMA
发明人： HIDEO KASAI , YASUHIRO TANIGUCHI , YASUHIKO KAWASHIMA , RYOTARO SAKURAI , YUTAKA SHINAGAWA , TATSURO TOYA , TAKANORI YAMAGUCHI , FUKUO OWADA , SHINJI YOSHIDA , TERUO HATADA , SATOSHI NODA , TAKAFUMI KATO , TETSUYA MURAYA , KOSUKE OKUYAMA
IPC分类号： H01L20060101
摘要： In a semiconductor memory device (1), voltage application from a memory gate electrode (G) of the memory capacitor (4) to a word line can be blocked by a rectifier element (3) depending on values of voltages applied to the memory gate electrode (G) and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device (1), for example, each bit line contact (BC15) is shared by four anti-fuse memories (2a 6 , 2a 7 , 2a 10 , and 2a 11 ) adjacent to each other and each word line contact (WC12) is shared by four anti-fuse memories (2a 3 , 2a 4 , 2a 7 , and 2a 8 ) adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.

3. 发明授权

US08478929B2 Data processing semiconductor device 有权
标题翻译：数据处理半导体器件
公开(公告)号：US08478929B2
公开(公告)日：2013-07-02
申请号：US12964803
申请日：2010-12-10
申请人： Yasunobu Aoki , Hideo Kasai , Masamichi Fujito , Junpei Inoue
发明人： Yasunobu Aoki , Hideo Kasai , Masamichi Fujito , Junpei Inoue
IPC分类号： G06F12/00
CPC分类号： G11C7/04 , G11C16/22
摘要： To improve the reliability of controlling overwriting of a nonvolatile memory in a data processing semiconductor device.In a data processing semiconductor device, a control unit which controls reading, writing, or erasing of data in a rewritable nonvolatile memory area has an operation mode that, referring to the input temperature data, controls a temperature range in which writing or erasing of data is performed to be narrower than the temperature range that allows reading of data in the memory area.
摘要翻译：提高在数据处理半导体器件中控制非易失性存储器的重写的可靠性。在数据处理半导体器件中，控制可重写非易失性存储区域中的数据的读取，写入或擦除的控制单元具有操作模式，其参考输入温度数据来控制数据写入或擦除的温度范围被执行为比允许读取存储器区域中的数据的温度范围窄。

4. 发明申请

US20100131475A1 COMPUTER PRODUCT, INFORMATION RETRIEVING APPARATUS, AND INFORMATION RETRIEVAL METHOD 有权
标题翻译：计算机产品，信息检索设备和信息检索方法
公开(公告)号：US20100131475A1
公开(公告)日：2010-05-27
申请号：US12622902
申请日：2009-11-20
申请人： Masahiro Kataoka , Ken Murata , Hideo Kasai , Takashi Tsubokura
发明人： Masahiro Kataoka , Ken Murata , Hideo Kasai , Takashi Tsubokura
IPC分类号： G06F17/30
CPC分类号： G06F17/30911
摘要： A recording medium stores therein an information retrieval program that causes a computer to execute generating a Huffman tree based on an XML tag written in an XML file and an appearance frequency of character data exclusive of the XML tag; compressing the XML file using the Huffman tree; receiving a retrieval condition that includes a retrieval keyword and type information concerning the retrieval keyword; setting a decompression start flag for a compression code that is for an XML start tag related to the type information, the decompression start flag instructing commencement of decompression of a compression code string subsequent to the XML start tag; detecting, in the compressed XML file, the compression code for which the decompression start flag has been set; and decompressing, when the compression code for which the decompression start flag has been set is detected, the compression code string, using the Huffman tree.
摘要翻译：记录媒体存储信息检索程序，该程序使计算机执行基于XML文件中写入的XML标签和排除XML标签的字符数据的出现频率来生成霍夫曼树; 使用霍夫曼树压缩XML文件; 接收包括检索关键字的检索条件和关于检索关键字的类型信息; 设置用于与类型信息相关的XML开始标签的压缩代码的解压开始标志，所述解压开始标志指示开始解压缩XML开始标签之后的压缩代码串; 在压缩XML文件中检测已经设置了解压开始标志的压缩码; 并且当检测到已经设置了解压开始标志的压缩码时，解压缩压缩码串，使用霍夫曼树。

5. 发明授权

US07170787B2 Nonvolatile memory apparatus 有权
标题翻译：非易失存储器
公开(公告)号：US07170787B2
公开(公告)日：2007-01-30
申请号：US11150144
申请日：2005-06-13
申请人： Ryotaro Sakurai , Hideo Chigasaki , Hideo Kasai
发明人： Ryotaro Sakurai , Hideo Chigasaki , Hideo Kasai
IPC分类号： G11C16/30
CPC分类号： G11C16/30 , G11C5/147
摘要： Current consumption in a nonvolatile memory apparatus operable on two or more different power voltages is to be substantially reduced in its standby mode. A stepped-down power supply unit provided in a flash memory to generate an internal power voltage, when supplied from outside with about 3.3 V as a power voltage, causes a first stepped-down power supply circuit to output the internal power voltage to control circuits when in normal operation. In a low power consumption mode, a second stepped-down power supply circuit outputs the internal power voltage to the control circuits, and in a standby mode a third stepped-down power supply circuit outputs to the control circuits an internal power voltage stepped down by an N-channel MOS transistor.
摘要翻译：在两种或多种不同电源电压下操作的非易失性存储装置中的电流消耗在其待机模式下将大幅降低。设置在闪速存储器中以产生内部电源电压的降压电源单元，当从外部供给约3.3V作为电源电压时，使第一降压电源电路将内部电源电压输出到控制电路正常运行时。在低功耗模式中，第二降压电源电路将内部电源电压输出到控制电路，并且在待机模式下，第三降压电源电路向控制电路输出内部电源电压，一个N沟道MOS晶体管。

6. 发明授权

US06982919B2 Memory card and data processing system 有权
标题翻译：存储卡和数据处理系统
公开(公告)号：US06982919B2
公开(公告)日：2006-01-03
申请号：US10891297
申请日：2004-07-15
申请人： Chiaki Kumahara , Atsushi Shikata , Yasuhiro Nakamura , Hideo Kasai , Hidefumi Odate
发明人： Chiaki Kumahara , Atsushi Shikata , Yasuhiro Nakamura , Hideo Kasai , Hidefumi Odate
IPC分类号： G11C7/08
CPC分类号： G11C16/30
摘要： A memory card and a microcomputer with nonvolatile memory wherein operation under two different types of power supply specifications is achieved are provided.A MultiMediaCard includes a flash memory and a controller which controls the operation associated with the flash memory. When the controller judges the level of supply voltage supplied from host equipment, it operates as follows: the controller judges whether detecting point corresponding to the voltage level of 1.8V system has been exceeded. After the judgment of excess, the controller judges whether detecting point corresponding to the voltage level of 3.3V system has been exceeded. When the supply voltage is at the voltage level of 1.8V system, the controller causes the flash memory to operate in the 1.8V-system operation mode without driving regulators or level shifters. When the supply voltage is at the voltage level of 3.3V system, the controller drives the regulators and the level shifters to convert the voltage level and causes the flash memory to operate in the 3.3V-system operation mode.
摘要翻译：提供一种存储卡和具有非易失性存储器的微型计算机，其中实现了两种不同类型的电源规格下的操作。多媒体卡包括闪存和控制与闪存相关的操作的控制器。当控制器判断从主机设备供电的电平时，其操作如下：控制器判断是否超过了对应于1.8V系统电压等级的检测点。超过判定后，控制器判断是否超过与3.3V系统的电压电平对应的检测点。当电源电压处于1.8V系统的电压电平时，控制器使闪存在1.8V系统运行模式下工作，无需驱动稳压器或电平转换器。当电源电压处于3.3V系统的电压电平时，控制器驱动稳压器和电平转换器转换电压电平，并使闪存在3.3V系统运行模式下工作。

7. 发明申请

US20050276110A1 Nonvolatile memory apparatus 有权
标题翻译：非易失存储器
公开(公告)号：US20050276110A1
公开(公告)日：2005-12-15
申请号：US11150144
申请日：2005-06-13
申请人： Ryotaro Sakurai , Hideo Chigasaki , Hideo Kasai
发明人： Ryotaro Sakurai , Hideo Chigasaki , Hideo Kasai
IPC分类号： G11C16/06 , G11C5/14 , G11C11/34 , G11C16/30
CPC分类号： G11C16/30 , G11C5/147
摘要： Current consumption in a nonvolatile memory apparatus operable on two or more different power voltages is to be substantially reduced in its standby mode. A stepped-down power supply unit provided in a flash memory to generate an internal power voltage, when supplied from outside with about 3.3 V as a power voltage, causes a first stepped-down power supply circuit to output the internal power voltage to control circuits when in normal operation. In a low power consumption mode, a second stepped-down power supply circuit outputs the internal power voltage to the control circuits, and in a standby mode a third stepped-down power supply circuit outputs to the control circuits an internal power voltage stepped down by an N-channel MOS transistor.
摘要翻译：在两种或多种不同电源电压下操作的非易失性存储装置中的电流消耗在其待机模式下将大幅降低。设置在闪速存储器中以产生内部电源电压的降压电源单元，当从外部供给约3.3V作为电源电压时，使第一降压电源电路将内部电源电压输出到控制电路正常运行时。在低功耗模式中，第二降压电源电路将内部电源电压输出到控制电路，并且在待机模式下，第三降压电源电路向控制电路输出内部电源电压，一个N沟道MOS晶体管。

8. 发明授权

US09081874B2 Information retrieval method, information retrieval apparatus, and computer product 有权
标题翻译：信息检索方法，信息检索装置和计算机产品
公开(公告)号：US09081874B2
公开(公告)日：2015-07-14
申请号：US13308133
申请日：2011-11-30
申请人： Masahiro Kataoka , Hiroyuki Torii , Masahiro Kurishima , Hideo Kasai
发明人： Masahiro Kataoka , Hiroyuki Torii , Masahiro Kurishima , Hideo Kasai
IPC分类号： G06F17/30 , H03M7/30
CPC分类号： G06F17/30985 , G06F17/30911 , H03M7/30 , Y10S707/99942
摘要： An information retrieval apparatus including a first detecting unit that detects a feeder indicative of a presence of a numerical value in a file subject to retrieval in which a numeral and a character are present together; a second detecting unit that detects a number of places in the numerical value correlated to the feeder detected by the first detecting unit; and a compressing unit that compresses the numerical value into compressed information including a compression code for a numeral indicative of the number of places detected by the second detecting unit and a compression code for a numeral at each place in the numerical value, wherein the numerical value is correlated to the feeder based on an appearance frequency of a numeral included in the file.
摘要翻译：一种信息检索装置，包括：第一检测单元，检测指示在数字和字符存在于一起的检索文件中存在数字值的馈送器; 第二检测单元，检测与由所述第一检测单元检测到的所述供给器相关的数值中的位置数; 以及压缩单元，其将数值压缩为压缩信息，该压缩信息包括表示由第二检测单元检测的位置的数量的数字的压缩代码和数值中每个位置的数字的压缩代码，其中数值基于文件中包括的数字的出现频率与馈线相关。

9. 发明授权

US08670280B2 Charge pump circuit, nonvolatile memory, data processing apparatus, and microcomputer application system 有权
标题翻译：电荷泵电路，非易失性存储器，数据处理装置和微机应用系统
公开(公告)号：US08670280B2
公开(公告)日：2014-03-11
申请号：US13181804
申请日：2011-07-13
申请人： Ryotaro Sakurai , Hideo Kasai
发明人： Ryotaro Sakurai , Hideo Kasai
IPC分类号： G11C7/00 , G05F3/02
CPC分类号： H02M3/073 , G11C5/145 , G11C16/12 , G11C16/30 , H01L27/0222 , H01L27/0251
摘要： Improvement technology of a charge pump circuit is provided for avoiding device destruction due to electrification of an intermediate node of plural capacitors coupled in series to form one step-up capacitor, and avoiding reduction of pump efficiency due to leakage current which flows through a leakage path of the intermediate node concerned. A charge pump circuit includes a step-up capacitor configured by a first capacitance and a second capacitance coupled in series, a capacitance driver, and a protection circuit. The protection circuit is set at a conductive state and discharges a stored charge at the series coupling node of the first capacitance and the second capacitance, when the step-up voltage is not generated, and the protection circuit is maintained in a non-conductive state, when the step-up voltage is generated. Accordingly, relaxation of the withstand voltage of the step-up capacitor is achieved, and reduction of the pump efficiency is avoided.
摘要翻译：提供电荷泵电路的改进技术，用于避免由于串联耦合的多个电容器的中间节点的通电而导致的器件破坏，以形成一个升压电容器，并且避免由于流过漏电路径的漏电流而导致的泵效率降低的中间节点。电荷泵电路包括由串联耦合的第一电容和第二电容器构成的升压电容器，电容驱动器和保护电路。当不产生升压电压时，保护电路设定在导通状态，并且在第一电容和第二电容的串联耦合节点处放电存储电荷，并且保护电路保持在非导通状态，当产生升压电压时。因此，实现了升压电容器的耐压的松弛，并且避免了泵效率的降低。

10. 发明申请

US20120014193A1 CHARGE PUMP CIRCUIT, NONVOLATILE MEMORY, DATA PROCESSING APPARATUS, AND MICROCOMPUTER APPLICATION SYSTEM 有权
标题翻译：充电泵电路，非易失性存储器，数据处理设备和微处理器应用系统
公开(公告)号：US20120014193A1
公开(公告)日：2012-01-19
申请号：US13181804
申请日：2011-07-13
申请人： Ryotaro SAKURAI , Hideo KASAI
发明人： Ryotaro SAKURAI , Hideo KASAI
IPC分类号： G11C7/00 , G05F3/02
CPC分类号： H02M3/073 , G11C5/145 , G11C16/12 , G11C16/30 , H01L27/0222 , H01L27/0251
摘要： Improvement technology of a charge pump circuit is provided for avoiding device destruction due to electrification of an intermediate node of plural capacitors coupled in series to form one step-up capacitor, and avoiding reduction of pump efficiency due to leakage current which flows through a leakage path of the intermediate node concerned. A charge pump circuit includes a step-up capacitor configured by a first capacitance and a second capacitance coupled in series, a capacitance driver, and a protection circuit. The protection circuit is set at a conductive state and discharges a stored charge at the series coupling node of the first capacitance and the second capacitance, when the step-up voltage is not generated, and the protection circuit is maintained in a non-conductive state, when the step-up voltage is generated. Accordingly, relaxation of the withstand voltage of the step-up capacitor is achieved, and reduction of the pump efficiency is avoided.
摘要翻译：提供电荷泵电路的改进技术，用于避免由于串联耦合的多个电容器的中间节点的通电而导致的器件破坏，以形成一个升压电容器，并且避免由于流过泄漏路径的漏电流而导致的泵效率降低的中间节点。电荷泵电路包括由串联耦合的第一电容和第二电容器构成的升压电容器，电容驱动器和保护电路。当不产生升压电压时，保护电路设定在导通状态，并且在第一电容和第二电容的串联耦合节点处放电存储电荷，并且保护电路保持在非导通状态，当产生升压电压时。因此，实现了升压电容器的耐压的松弛，并且避免了泵效率的降低。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式