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1. 发明申请

US20060174303A1 Moving picture encoding or decoding processing system and mobin g picture encoding or decoding processing method 审中-公开
标题翻译：运动图像编码或解码处理系统和移动图像编码或解码处理方法
公开(公告)号：US20060174303A1
公开(公告)日：2006-08-03
申请号：US10553651
申请日：2004-04-15
申请人： Masahiko Yoshimoto , Kentaro Kawakami , Miwako Kanamori , Hideo Ohira
发明人： Masahiko Yoshimoto , Kentaro Kawakami , Miwako Kanamori , Hideo Ohira
IPC分类号： H04N7/173 , H04N7/16
CPC分类号： H04N19/42 , H04N19/127 , H04N19/136 , H04N19/172 , H04N19/61
摘要： This invention is aimed at providing a motion picture encoding or decoding system and a motion picture encoding or decoding method which economize the electric power consumption efficiently as compared with the conventional technique. They are provided with at least one failure avoiding means adapted to calculate a necessary volume Kp of operation required for encoding or decoding one frame, decide an operating frequency F capable of encoding or decoding the necessary volume Kp of operation within a duration Te allocated in advance to the operation of encoding or decoding the one frame, perform the operation of encoding or decoding the one frame while continuing the operation of the processor at the operating frequency F and an operating voltage V befitting the operating frequency F, and avoid the failure situation which occurs when the necessary volume Kp of operation is smaller than the actually necessary volume of operation.
摘要翻译：本发明旨在提供一种与常规技术相比有效地节省电力消耗的运动图像编码或解码系统和运动图像编码或解码方法。它们被提供有至少一个故障避免装置，其适于计算编码或解码一帧所需的操作的必要体积Kp，决定能够在预先分配的持续时间Te内编码或解码所需体积Kp的操作频率F 对于一帧编码或解码的操作，在操作频率F持续处理器的操作和与操作频率F相匹配的操作电压V的同时执行对一帧进行编码或解码的操作，并避免出现故障情况当必需的操作量Kp小于实际所需的操作量时发生。

2. 发明授权

US08291256B2 Clock stop and restart control to pipelined arithmetic processing units processing plurality of macroblock data in image frame per frame processing period 有权
标题翻译：对每帧处理周期的图像帧处理多个宏块数据的流水线运算处理单元进行时钟停止和重启控制
公开(公告)号：US08291256B2
公开(公告)日：2012-10-16
申请号：US12278015
申请日：2007-02-05
申请人： Masahiko Yoshimoto , Kentaro Kawakami , Jun Takemura
发明人： Masahiko Yoshimoto , Kentaro Kawakami , Jun Takemura
IPC分类号： G06F1/04 , G06F15/80
CPC分类号： G06F1/10 , G06F1/3203 , G06F1/3237 , Y02D10/128
摘要： A digital VLSI circuit is provided with functions in which the number of switching operations to supply electric power to each arithmetic operation unit is reduced in a restricted period of time while electric power supply is controlled for each arithmetic operation unit, so that low power consumption can be achieved in real pipe-line arithmetic operation. The VLSI circuit that performs each stage of the pipe-line arithmetic operation is comprised of a plurality of arithmetic operation units for carrying out arithmetic operations in synchronization with a clock signal, a detecting means for detecting completion of the stage in the arithmetic operation assigned to the arithmetic operation unit, and a clock signal supply control means for controlling supply/stop operation of the clock signal to each arithmetic operation unit, wherein the clock signal supply control means stops supplying the clock signal to a certain arithmetic operation unit when the detecting means detects the completion of the arithmetic operation assigned to the same, and restarts supplying the clock signal to all the arithmetic operation units for a next pipe-line arithmetic operation when the detecting means detects the completion of the arithmetic operations assigned to them.
摘要翻译：数字VLSI电路具有这样的功能，其中在每个算术运算单元控制电力供应时，在限制的时间段内减少向每个算术运算单元供电的开关操作次数，从而低功耗可以在实际管线算术运算中实现。执行管线算术运算的每个阶段的VLSI电路包括用于与时钟信号同步地执行算术运算的多个算术运算单元，检测装置，用于检测分配给算术运算单元，以及时钟信号供给控制单元，用于控制对每个算术运算单元的时钟信号的供给/停止运行，其中，当所述检测单元检测到所述检测单元时，所述时钟信号供给控制单元停止向所述算术运算单元供给所述时钟信号检测到分配给其的算术运算的完成，并且当检测装置检测到分配给它们的算术运算的完成时，重新开始向所有算术运算单元提供时钟信号用于下一个管线算术运算。

3. 发明申请

US20090024866A1 DIGITAL VLSI CIRCUIT AND IMAGE PROCESSING DEVICE INTO WHICH THE SAME IS ASSEMBLED 有权
标题翻译：数字VLSI电路和图像处理装置同时组装
公开(公告)号：US20090024866A1
公开(公告)日：2009-01-22
申请号：US12278015
申请日：2007-02-05
申请人： Masahiko Yoshimoto , Kentaro Kawakami
发明人： Masahiko Yoshimoto , Kentaro Kawakami
IPC分类号： G06F1/04 , G06F9/302
CPC分类号： G06F1/10 , G06F1/3203 , G06F1/3237 , Y02D10/128
摘要： A digital VLSI circuit is provided with functions in which the number of switching operations to supply electric power to each arithmetic operation unit is reduced in a restricted period of time while electric power supply is controlled for each arithmetic operation unit, so that low power consumption can be achieved in real pipe-line arithmetic operation. The VLSI circuit that performs each stage of the pipe-line arithmetic operation is comprised of a plurality of arithmetic operation units for carrying out arithmetic operations in synchronization with a clock signal, a detecting means for detecting completion of the stage in the arithmetic operation assigned to the arithmetic operation unit, and a clock signal supply control means for controlling supply/stop operation of the clock signal to each arithmetic operation unit, wherein the clock signal supply control means stops supplying the clock signal to a certain arithmetic operation unit when the detecting means detects the completion of the arithmetic operation assigned to the same, and restarts supplying the clock signal to all the arithmetic operation units for a next pipe-line arithmetic operation when the detecting means detects the completion of the arithmetic operations assigned to them.
摘要翻译：数字VLSI电路具有这样的功能，其中在每个算术运算单元控制电力供应时，在限制的时间段内减少向每个算术运算单元供电的开关操作次数，从而低功耗可以在实际管线算术运算中实现。执行管线算术运算的每个阶段的VLSI电路包括用于与时钟信号同步地执行算术运算的多个算术运算单元，检测装置，用于检测分配给算术运算单元，以及时钟信号供给控制单元，用于控制对每个算术运算单元的时钟信号的供给/停止运行，其中，当所述检测单元检测到所述检测单元时，所述时钟信号供给控制单元停止向所述算术运算单元供给所述时钟信号检测到分配给其的算术运算的完成，并且当检测装置检测到分配给它们的算术运算的完成时，重新开始向所有算术运算单元提供时钟信号用于下一个管线算术运算。

4. 发明授权

US07236634B2 Image encoding of moving pictures 失效
标题翻译：运动图像的图像编码
公开(公告)号：US07236634B2
公开(公告)日：2007-06-26
申请号：US10703547
申请日：2003-11-10
申请人： Junichi Miyakoshi , Masayuki Miyama , Masahiko Yoshimoto , Hideo Hashimoto , Kousuke Imamura
发明人： Junichi Miyakoshi , Masayuki Miyama , Masahiko Yoshimoto , Hideo Hashimoto , Kousuke Imamura
IPC分类号： G06K9/36
CPC分类号： H04N19/61 , H04N19/51
摘要： In an encoding method of moving pictures which generates a predictive picture for a current picture based on a reference picture and a motion vector, a macroblock is divided into subblocks. In each of the plurality of subblocks, an initial value of the motion vector is set and an evaluated value E on a difference between the current picture and the reference picture is calculated along a steepest descent direction to determine the minimum value. Then, the smallest evaluated value is selected among the minimum values obtained on the plurality of subblocks to determine the motion vector based on the pixel position of the smallest value.
摘要翻译：在基于参考图像和运动矢量生成当前图像的预测图像的运动图像的编码方法中，宏块被划分为子块。在多个子块中的每一个中，设置运动矢量的初始值，并且沿最陡下降方向计算当前画面与参考画面之间的差值的评估值E，以确定最小值。然后，从在多个子块上获得的最小值中选择最小的评估值，以基于最小值的像素位置来确定运动矢量。

5. 发明授权

US5379257A Semiconductor integrated circuit device having a memory and an operational unit integrated therein 失效
标题翻译：具有集成在其中的存储器和操作单元的半导体集成电路器件
公开(公告)号：US5379257A
公开(公告)日：1995-01-03
申请号：US767767
申请日：1991-09-30
申请人： Tetsuya Matsumura , Hiroshi Segawa , Kazuya Ishihara , Shinichi Uramoto , Masahiko Yoshimoto
发明人： Tetsuya Matsumura , Hiroshi Segawa , Kazuya Ishihara , Shinichi Uramoto , Masahiko Yoshimoto
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C13/00
CPC分类号： G11C7/1006 , G11C2207/104
摘要： A semiconductor integrated circuit device includes a memory cell array for storing data to be processed, and an operational unit for effecting a predetermined operation on the data read from the memory cell array. The memory cell array has first and second regions for storing first and second data words of first and second groups. The first data words and second data words each include a plurality of data bits. The first region includes a plurality of bit arrays for storing data bits of the same digit in the first data words, and the second region includes a plurality of bit arrays for storing data bite of the same digit in the second data words. The bit arrays of the first and second groups are arranged alternately in the order of digits of the data words. The bit arrays storing the data bits of the same digit form one subarray. The data bits in one data word are stored in the same positions of the bit arrays. The operational unit includes operational circuits each corresponding to one of the subarrays. Each operational circuit effects the predetermined operation on the data read from the two bit arrays in the corresponding subarray. Each bit array has selectors responsive to external addresses to select one column from each bit array and connect this column to a corresponding operational circuit.
摘要翻译：半导体集成电路装置包括用于存储要处理的数据的存储单元阵列和用于对从存储单元阵列读取的数据进行预定操作的操作单元。存储单元阵列具有用于存储第一和第二组的第一和第二数据字的第一和第二区域。第一数据字和第二数据字各自包括多个数据位。第一区域包括用于存储第一数据字中相同数位的数据位的多个位阵列，并且第二区域包括用于存储第二数据字中相同数字的数据位的多个位数组。第一组和第二组的位阵列以数据字的数位顺序交替排列。存储相同数位数据位的位数组形成一个子阵列。一个数据字中的数据位存储在位阵列的相同位置。操作单元包括各自对应于一个子阵列的操作电路。每个操作电路对从相应子阵列中的两个位阵列读取的数据执行预定的操作。每个位阵列具有响应于外部地址的选择器，从每个位阵列中选择一个列，并将该列连接到相应的运算电路。

6. 发明授权

US5053999A Semiconductor memory device having redundancy and capable of sequentially selecting memory cell lines 失效
标题翻译：半导体存储器件具有冗余并且能够顺序地选择存储器单元线
公开(公告)号：US5053999A
公开(公告)日：1991-10-01
申请号：US500328
申请日：1990-03-28
申请人： Tetsuya Matsumura , Masahiko Yoshimoto
发明人： Tetsuya Matsumura , Masahiko Yoshimoto
IPC分类号： G06F5/00 , G11C29/00
CPC分类号： G11C29/70 , G11C29/86 , G06F5/00
摘要： First-In First-Out (FIFO) memory device is disclosed. A ring pointer circuit sequentially and repeatedly selects memory cells in a memory cell array. When it is detected that a defective memory cell exists on a memory cell row, selection of that memory cell row is invalidated by the ring pointer circuit by cutting off a laser trimming line. In addition, by selectively cutting off laser trimming lines in a switching circuit and a redundancy ring pointer circuit, a redundancy memory cell row is selectively added in place of the defective memory cell row. Accordingly, stages required for the ring pointer circuit are maintained. In other words, the FIFO memory device having a defective memory cell is saved, resulting in improvement in yield in the manufacture.
摘要翻译：先进先出（FIFO）存储器件被公开。环形指针电路依次重复地选择存储单元阵列中的存储单元。当检测到存储单元行中存在有缺陷的存储单元时，通过切断激光修整线，通过环形指针电路对该存储单元行的选择无效。此外，通过选择性地切断开关电路和冗余环形指针电路中的激光微调线，选择性地添加冗余存储单元行来代替有缺陷的存储单元行。因此，保持环形指针电路所需的阶段。换句话说，具有缺陷存储单元的FIFO存储器件被保存，从而提高了制造中的产量。

7. 发明授权

US4935896A Semiconductor memory device having three-transistor type memory cells structure without additional gates 失效
标题翻译：具有三晶体管型存储单元的半导体存储器件结构而没有附加栅极
公开(公告)号：US4935896A
公开(公告)日：1990-06-19
申请号：US266057
申请日：1988-11-02
申请人： Tetsuya Matsumura , Masahiko Yoshimoto
发明人： Tetsuya Matsumura , Masahiko Yoshimoto
IPC分类号： G11C7/06 , G11C11/405 , G11C11/406
CPC分类号： G11C7/065 , G11C11/405 , G11C11/406 , G11C7/067
摘要： A memory cell array (61) comprises a plurality of three-transistor type memory cells (10) arranged in a plurality of rows and columns. A plurality of pairs of write bit lines (WB1, WB2) and a plurality of read bit lines (RB) are provided corresponding to each column of the memory cell array (61). The plurality of write word lines (WWL) and the plurality of read word lines (RWL) are provided corresponding to each row of the memory cell array (61). Information is written to memory cells (10) in odd rows through the respective one write bit lines of the pairs of write bit lines (WB1, WB2), and information is written to memory cells (10) in even rows through the respective other write bit lines of the pairs of write bit lines (WB1, WB2). A sense amplifier (30) is connected to each of the pairs of write bit lines (WB1, WB2). At the time of write operation, refresh operation is performed by the sense amplifier (30) with respect to memory cells (10) in non-selected columns.
摘要翻译：存储单元阵列（61）包括以多个行和列排列的多个三晶体管型存储单元（10）。对应于存储单元阵列（61）的每列，提供多对写位线（WB1，WB2）和多条读位线（RB）。对应于存储单元阵列（61）的每一行，提供多个写入字线（WWL）和多条读取字线（RWL）。信息通过写入位线对（WB1，WB2）中的相应的一个写位线被写入奇数行的存储单元（10），并且信息通过相应的其他写入写入偶数行的存储单元（10）写位线对（WB1，WB2）的位线。读出放大器（30）连接到写入位线对（WB1，WB2）中的每一对。在写入操作时，相对于非选择列中的存储单元（10），读出放大器（30）执行刷新操作。

8. 发明授权

US4878125A Method and apparatus for image processing with fed-back error correction 失效
标题翻译：具有反馈误差校正的图像处理方法和装置
公开(公告)号：US4878125A
公开(公告)日：1989-10-31
申请号：US140029
申请日：1987-12-31
申请人： Akihiro Katayama , Hidefumi Ohsawa , Izuru Sunohara , Hiroshi Hosokawa , Masahiko Yoshimoto
发明人： Akihiro Katayama , Hidefumi Ohsawa , Izuru Sunohara , Hiroshi Hosokawa , Masahiko Yoshimoto
IPC分类号： G06T5/00 , H04N1/405 , H04N1/52 , H04N7/26
CPC分类号： H04N19/90 , G06T7/0083 , H04N1/4052 , H04N1/52 , G06T2207/10008
摘要： There is an image processing apparatus for digitally processing an image. This apparatus comprises: a binarization circuit to binarize image data by a predetermined threshold value; a processor to correct errors generated in binarization; a first detector to detect an edge direction of the image from the image data; and a second detector to detect an edge quantum of the image from the image data. The process corrects the error data in accordance with the edge direction detected by the first detector or the edge quantum detected by the second detector. The errors to be corrected by the processor are the errors between the output concentration data after the binarization and the image concentration data. The processor adds weight coefficients to the error data in a predetermined range stored in a memory and then adds the weighted error data to image data to be newly binarized. The sum of the weight coefficients which are used in the weighting process is set to "1". With this apparatus, a high quality apparatus can be reproduced with a high fidelity from an original including many edges.
摘要翻译：存在用于数字处理图像的图像处理装置。该装置包括：将图像数据二值化预定阈值的二值化电路; 处理器，用于校正二值化中产生的错误; 第一检测器，用于从图像数据检测图像的边缘方向; 以及第二检测器，用于从图像数据检测图像的边缘量子。该过程根据由第一检测器检测到的边缘方向或由第二检测器检测到的边缘量子来校正误差数据。处理器要纠正的错误是二值化后的输出浓度数据与图像浓度数据之间的误差。处理器将加权系数加到存储在存储器中的预定范围内的误差数据上，然后将加权的误差数据加到新二进制化的图像数据上。在加权处理中使用的加权系数的和被设置为“1”。利用该装置，可以从包括许多边缘的原稿以高保真度再现高质量的装置。

9. 发明授权

US4554646A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4554646A
公开(公告)日：1985-11-19
申请号：US542388
申请日：1983-10-17
申请人： Masahiko Yoshimoto , Tsutomu Yoshihara , Kenji Anami , Hirofumi Shinohara
发明人： Masahiko Yoshimoto , Tsutomu Yoshihara , Kenji Anami , Hirofumi Shinohara
IPC分类号： G11C8/12 , G11C8/14 , G11C11/40
CPC分类号： G11C8/14 , G11C8/12
摘要： A memory matrix is segmented in the direction of columns into a plurality of groups of memory cells. The memory cells are accessible through respective preceding word lines each of which is provided for each of the rows of the matrix and commonly to all of the groups of the memory cells and group word lines each of which is provided per group and per row, so that a path for column current is set up during access time only in the column which belongs to a particular group including a particular memory to be accessed.
摘要翻译：存储器矩阵在列的方向上分割成多组存储器单元。存储器单元可以通过各自的前面的字线访问，每个字线是为矩阵的每一行提供的，并且通常是存储器单元的所有组以及每个组和每行提供的组字线，因此在访问时间期间仅在属于包括要访问的特定存储器的特定组的列中建立列电流的路径。

10. 发明授权

US08600443B2 Sensor network system for acquiring high quality speech signals and communication method therefor 失效
标题翻译：用于获取高质量语音信号的传感器网络系统及其通信方法
公开(公告)号：US08600443B2
公开(公告)日：2013-12-03
申请号：US13547426
申请日：2012-07-12
申请人： Hiroshi Kawaguchi , Masahiko Yoshimoto , Shintaro Izumi
发明人： Hiroshi Kawaguchi , Masahiko Yoshimoto , Shintaro Izumi
IPC分类号： H04B1/38
CPC分类号： H04R3/005 , G10L2021/02166 , H04R1/406 , H04R2201/401
摘要： A sensor network system including node devices connected in a network via predetermined propagation paths collects data measured at each node device to be aggregated into one base station via a time-synchronized sensor network system. The base station calculates a position of the signal source based on the angle estimation value of the signal from each node device and position information thereof, designates a node device located nearest to the signal source as a cluster head node device, and transmits information of the position of the signal source and the designated cluster head node device to each node device, to cluster each node device located within the number of hops from the cluster head node device as a node device belonging to each cluster. Each node device performs an emphasizing process on the received signal from the signal source, and transmits an emphasized signal to the base station.
摘要翻译：包括经由预定传播路径连接在网络中的节点设备的传感器网络系统经由时间同步的传感器网络系统收集在每个节点设备测量的要聚合成一个基站的数据。基站基于来自各节点装置的信号的角度估计值及其位置信息来计算信号源的位置，将位于最靠近信号源的节点装置指定为簇头节点装置，并发送信息源信号源和指定的簇头节点设备的位置到每个节点设备，将位于簇头节点设备内的跳数内的每个节点设备聚类为属于每个集群的节点设备。每个节点设备对来自信号源的接收信号执行强调处理，并将强调信号发送到基站。

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