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    • 1. 发明授权
    • Sensor network system for acquiring high quality speech signals and communication method therefor
    • 用于获取高质量语音信号的传感器网络系统及其通信方法
    • US08600443B2
    • 2013-12-03
    • US13547426
    • 2012-07-12
    • Hiroshi KawaguchiMasahiko YoshimotoShintaro Izumi
    • Hiroshi KawaguchiMasahiko YoshimotoShintaro Izumi
    • H04B1/38
    • H04R3/005G10L2021/02166H04R1/406H04R2201/401
    • A sensor network system including node devices connected in a network via predetermined propagation paths collects data measured at each node device to be aggregated into one base station via a time-synchronized sensor network system. The base station calculates a position of the signal source based on the angle estimation value of the signal from each node device and position information thereof, designates a node device located nearest to the signal source as a cluster head node device, and transmits information of the position of the signal source and the designated cluster head node device to each node device, to cluster each node device located within the number of hops from the cluster head node device as a node device belonging to each cluster. Each node device performs an emphasizing process on the received signal from the signal source, and transmits an emphasized signal to the base station.
    • 包括经由预定传播路径连接在网络中的节点设备的传感器网络系统经由时间同步的传感器网络系统收集在每个节点设备测量的要聚合成一个基站的数据。 基站基于来自各节点装置的信号的角度估计值及其位置信息来计算信号源的位置,将位于最靠近信号源的节点装置指定为簇头节点装置,并发送信息源 信号源和指定的簇头节点设备的位置到每个节点设备,将位于簇头节点设备内的跳数内的每个节点设备聚类为属于每个集群的节点设备。 每个节点设备对来自信号源的接收信号执行强调处理,并将强调信号发送到基站。
    • 2. 发明授权
    • Ad converter and TD converter configured without operational amplifier and capacitor
    • Ad转换器和TD转换器配置无运算放大器和电容
    • US08519880B2
    • 2013-08-27
    • US13470605
    • 2012-05-14
    • Hiroshi KawaguchiMasahiko YoshimotoToshihiro KonishiShintaro Izumi
    • Hiroshi KawaguchiMasahiko YoshimotoToshihiro KonishiShintaro Izumi
    • H03M1/50
    • H03M1/50H03M3/416
    • An AD converter includes a VT converter circuit part which inputs an analog input voltage and a sampling clock, converts the analog input voltage to a corresponding delay time, and outputs time domain data. A ring oscillator circuit part of N stages inputs the time domain data, and an error propagation circuit part takes out delay information containing a quantization error from phase information of the ring oscillator circuit part of the previous stage, and propagate the delay information to the ring oscillator circuit part of a subsequent stage. A counter circuit part measures a number of waves of an output oscillation waveform of the ring oscillator circuit part of each stage, and an output signal generator part generates an output signal from an output counted value of each counter circuit part. A reset part resets each error propagation circuit part and each counter circuit part with a sampling clock.
    • AD转换器包括输入模拟输入电压和采样时钟的VT转换器电路部分,将模拟输入电压转换为相应的延迟时间,并输出时域数据。 N级的环形振荡器电路部分输入时域数据,误差传播电路部分从前级的环形振荡电路部分的相位信息中取出包含量化误差的延迟信息,并将延迟信息传播到环 振荡电路是后续阶段的一部分。 计数器电路部分测量每个级的环形振荡器电路部分的输出振荡波形的波数,并且输出信号发生器部分根据每个计数器电路部分的输出计数值产生输出信号。 复位部分将采样时钟复位每个误差传播电路部分和每个计数器电路部分。
    • 5. 发明授权
    • Semiconductor memory and program
    • 半导体存储器和程序
    • US08238140B2
    • 2012-08-07
    • US12809684
    • 2009-01-07
    • Masahiko YoshimotoHiroshi KawaguchiShunsuke OkumuraHidehiro Fujiwara
    • Masahiko YoshimotoHiroshi KawaguchiShunsuke OkumuraHidehiro Fujiwara
    • G11C11/24G11C11/00G11C7/00G11C7/02G11C29/00
    • G11C11/4125G11C5/005
    • A memory wherein the bit reliability of the memory cells can be dynamically varied depending on the application or the memory status, the operation stability is ensured, and thereby a low power consumption and a high reliability are realized. Either a mode (a 1-bit/1-cell mode) in which one bit is composed of one memory cell or a mode (a 1-bit/n-cell mode) in which one bit is composed of n (n is two or more) connected memory cells is dynamically selected. When the 1-bit/n-cell mode is selected, the read/write stability of one bit is enhanced, the cell current during read is increased (read is speeded up), and a bit error, if occurs, is self-corrected. Especially, a pair of CMOS transistors and a control line for performing control so as to permit the CMOS transistors to conduct are added between the data holding nodes of n adjacent memory cells. With this, the word line (WL) is controlled, and thereby the operation stability is further improved.
    • 可以根据应用或存储器状态来动态地改变存储器单元的位可靠性的存储器,从而确保操作稳定性,从而实现低功耗和高可靠性。 一个位由一个存储器单元组成的模式(1位/ 1单元模式)或其中一个位由n组成的模式(1位/ n单元模式) 或更多)连接的存储器单元被动态地选择。 当选择1位/ n单元模式时,增加了一位的读/写稳定性,读取期间的单元电流增加(读取速度加快),如果出现位错误,则自校正 。 特别地,在n个相邻的存储单元的数据保持节点之间添加一对CMOS晶体管和用于执行控制以允许CMOS晶体管导通的控制线。 由此,对字线(WL)进行控制,从而进一步提高操作稳定性。
    • 9. 发明授权
    • Flying object
    • 飞行对象
    • US09016616B2
    • 2015-04-28
    • US13190040
    • 2011-07-25
    • Hiroshi Kawaguchi
    • Hiroshi Kawaguchi
    • B64C29/00B64C29/02
    • B64C29/02
    • By using the interaction between the wind flow and the stabilizer arranged in the wind flow and along the direction of the wind flow, this invention provides the flying object that secures the stability of device or aircraft or stabilizer itself unified with the stabilizer by above effect. The interaction mentioned above is that when the wind flow hits the stabilizer at a certain angle, the wind flow changes the direction, and the power corresponding its reaction is given to the stabilizer by its reaction.
    • 通过使用风流和布置在风流中并沿风流方向的稳定器之间的相互作用,本发明提供了通过上述效果确保装置或飞行器或稳定器本身与稳定器一致的稳定性的飞行物体。 上述相互作用是当风流以一定角度撞击稳定器时,风流改变方向,并且通过其反应将稳定器的功率与其反应相对应。