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1. 发明授权

US4554646A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4554646A
公开(公告)日：1985-11-19
申请号：US542388
申请日：1983-10-17
申请人： Masahiko Yoshimoto , Tsutomu Yoshihara , Kenji Anami , Hirofumi Shinohara
发明人： Masahiko Yoshimoto , Tsutomu Yoshihara , Kenji Anami , Hirofumi Shinohara
IPC分类号： G11C8/12 , G11C8/14 , G11C11/40
CPC分类号： G11C8/14 , G11C8/12
摘要： A memory matrix is segmented in the direction of columns into a plurality of groups of memory cells. The memory cells are accessible through respective preceding word lines each of which is provided for each of the rows of the matrix and commonly to all of the groups of the memory cells and group word lines each of which is provided per group and per row, so that a path for column current is set up during access time only in the column which belongs to a particular group including a particular memory to be accessed.
摘要翻译：存储器矩阵在列的方向上分割成多组存储器单元。存储器单元可以通过各自的前面的字线访问，每个字线是为矩阵的每一行提供的，并且通常是存储器单元的所有组以及每个组和每行提供的组字线，因此在访问时间期间仅在属于包括要访问的特定存储器的特定组的列中建立列电流的路径。

2. 再颁专利

USRE33280E Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：USRE33280E
公开(公告)日：1990-07-31
申请号：US123106
申请日：1987-11-19
申请人： Masahiko Yoshimoto , Tsutomu Yoshihara , Kenji Anami , Hirofumi Shinohara
发明人： Masahiko Yoshimoto , Tsutomu Yoshihara , Kenji Anami , Hirofumi Shinohara
IPC分类号： G11C5/06 , G11C8/14
CPC分类号： G11C5/063 , G11C8/14
摘要： A memory matrix is segmented in the direction of columns into a plurality of groups of memory cells. The memory cells are accessible through respective preceding word lines each of which is provided for each of the rows of the matrix and commonly to all of the groups of the memory cells and group word lines each of which is provided per group and per row, so that a path for column current is set up during access time only in the column which belongs to a particular group including a particular memory to be accessed.

3. 再颁专利

USRE32993E Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：USRE32993E
公开(公告)日：1989-07-18
申请号：US97770
申请日：1987-09-17
申请人： Kenji Anami , Masahiko Yoshimoto , Hirofumi Shinohara , Osamu Tomisawa
发明人： Kenji Anami , Masahiko Yoshimoto , Hirofumi Shinohara , Osamu Tomisawa
IPC分类号： G11C11/417 , G11C5/02 , G11C5/06 , G11C8/12 , G11C8/14 , G11C11/41
CPC分类号： G11C5/06 , G11C5/02 , G11C8/12 , G11C8/14
摘要： A semiconductor memory device is improved as regards current consumption and access time by dividing the memory cells into a plurality of columner groups and providing group selecting lines. Front-end word lines flow resistance are connected to outputs of row decoders, and AND gates receive selecting signals on the group selecting lines and the outputs of the front-end word lines. Word lines of a comparatively short length are connected to the AND outputs.

4. 发明授权

US4521704A Differential amplifying circuit 失效
标题翻译：差分放大电路
公开(公告)号：US4521704A
公开(公告)日：1985-06-04
申请号：US462204
申请日：1983-01-31
申请人： Hirofumi Shinohara , Osamu Tomisawa , Kenji Anami , Masahiko Yoshimoto
发明人： Hirofumi Shinohara , Osamu Tomisawa , Kenji Anami , Masahiko Yoshimoto
IPC分类号： G11C11/417 , H03F3/26 , H03F3/45 , H03K5/02
CPC分类号： H03F3/265 , H03F3/45076 , H03F2203/45318 , H03F2203/45394
摘要： A differential amplifying circuit includes a pair of main amplifying circuits (5a, 5b) each having at least three input terminals and at least one output terminal, and a pair of auxiliary amplifying circuits (6a, 6b) each having at least one input terminal. Complimentary inputs (D1, D1) are connected to the input terminals of said pair of auxiliary amplifying circuits (6a, 6b), the outputs (D2, D2) of the main amplifying circuits (5a, 5b) are connected as crossing feedback inputs to at least a pair of input terminals of said pair of main amplifying circuits (5a, 5b), the complimentary inputs (D2, D2) are also connected to the other at least one pair of input terminals, and the outputs of said auxiliary amplifying circuits (6a, 6b) are further connected to the further at least pair of input terminals.
摘要翻译：差分放大电路包括一对主放大电路（5a，5b），每一个具有至少三个输入端和至少一个输出端，以及一对辅助放大电路（6a，6b），每一个具有至少一个输入端。免费输入（D1，＆amp; upbar＆D）连接到所述一对辅助放大电路（6a，6b）的输入端，主放大电路（5a，5b）的输出（D2，＆amp; upbar＆D）输入到所述一对主放大电路（5a，5b）中的至少一对输入端，所述互补输入（D2，＆amp;上和下）也连接到另一个至少一对输入端，并且所述输出辅助放大电路（6a，6b）进一步连接到另外的至少一对输入端。

5. 发明授权

US4542486A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4542486A
公开(公告)日：1985-09-17
申请号：US500608
申请日：1983-06-02
申请人： Kenji Anami , Masahiko Yoshimoto , Hirofumi Shinohara , Osamu Tomisawa
发明人： Kenji Anami , Masahiko Yoshimoto , Hirofumi Shinohara , Osamu Tomisawa
IPC分类号： G11C11/417 , G11C5/02 , G11C5/06 , G11C8/12 , G11C8/14 , G11C11/41 , G11C11/40
CPC分类号： G11C5/06 , G11C5/02 , G11C8/12 , G11C8/14
摘要： A semiconductor memory device is improved as regards current consumption and access time by dividing the memory cells into a plurality of columner groups and providing group selecting lines. Front-end word lines of low resistance are connected to outputs of row decoders, and AND gates receive selecting signals on the group selecting lines and the outputs of the front-end word lines. Word lines of a comparatively short length are connected to the AND outputs.
摘要翻译：通过将存储单元划分成多个电容器组并提供组选择线，半导体存储器件关于电流消耗和存取时间被改进。低电阻的前端字线连接到行解码器的输出，与门接收组选择线上的选择信号和前端字线的输出。长度相对较短的字线连接到AND输出。

6. 发明授权

US4772930A Complementary metal oxide semiconductor integrated circuit with unequal reference voltages 失效
标题翻译：具有不等参考电压的互补金属氧化物半导体集成电路
公开(公告)号：US4772930A
公开(公告)日：1988-09-20
申请号：US48509
申请日：1987-05-04
申请人： Kenji Anami , Masahiko Yoshimoto , Satoru Kamoto
发明人： Kenji Anami , Masahiko Yoshimoto , Satoru Kamoto
IPC分类号： H01L27/08 , H01L21/74 , H01L23/528 , H01L23/535 , H01L27/092 , H01L27/02
CPC分类号： H01L27/0921 , H01L21/743 , H01L23/5286 , H01L23/535 , H01L2924/0002
摘要： A power supply voltage to be applied to a metallic connection 36a is supplied through an n.sup.+ diffusion region 34a, an N type well 22, an n.sup.+ diffusion region 34c and a metallic connection 36C to a p.sup.+ diffusion region 23b serving as a power supply line. An n.sup.+ diffusion region 73 serving as a ground line is grounded through a metallic connection 76c, a p.sup.+ diffusion region 74c, a P type well 72, a p.sup.+ diffusion region 74b and a metallic connection 76b.
摘要翻译：施加到金属连接36a的电源电压通过n +扩散区域34a，N型阱22，n +扩散区域34c和金属连接件36C提供给用作电源线的p +扩散区域23b。用作接地线的n +扩散区73通过金属连接76c，p +扩散区74c，P型阱72，p +扩散区74b和金属连接76b接地。

7. 发明授权

US08291256B2 Clock stop and restart control to pipelined arithmetic processing units processing plurality of macroblock data in image frame per frame processing period 有权
标题翻译：对每帧处理周期的图像帧处理多个宏块数据的流水线运算处理单元进行时钟停止和重启控制
公开(公告)号：US08291256B2
公开(公告)日：2012-10-16
申请号：US12278015
申请日：2007-02-05
申请人： Masahiko Yoshimoto , Kentaro Kawakami , Jun Takemura
发明人： Masahiko Yoshimoto , Kentaro Kawakami , Jun Takemura
IPC分类号： G06F1/04 , G06F15/80
CPC分类号： G06F1/10 , G06F1/3203 , G06F1/3237 , Y02D10/128
摘要： A digital VLSI circuit is provided with functions in which the number of switching operations to supply electric power to each arithmetic operation unit is reduced in a restricted period of time while electric power supply is controlled for each arithmetic operation unit, so that low power consumption can be achieved in real pipe-line arithmetic operation. The VLSI circuit that performs each stage of the pipe-line arithmetic operation is comprised of a plurality of arithmetic operation units for carrying out arithmetic operations in synchronization with a clock signal, a detecting means for detecting completion of the stage in the arithmetic operation assigned to the arithmetic operation unit, and a clock signal supply control means for controlling supply/stop operation of the clock signal to each arithmetic operation unit, wherein the clock signal supply control means stops supplying the clock signal to a certain arithmetic operation unit when the detecting means detects the completion of the arithmetic operation assigned to the same, and restarts supplying the clock signal to all the arithmetic operation units for a next pipe-line arithmetic operation when the detecting means detects the completion of the arithmetic operations assigned to them.
摘要翻译：数字VLSI电路具有这样的功能，其中在每个算术运算单元控制电力供应时，在限制的时间段内减少向每个算术运算单元供电的开关操作次数，从而低功耗可以在实际管线算术运算中实现。执行管线算术运算的每个阶段的VLSI电路包括用于与时钟信号同步地执行算术运算的多个算术运算单元，检测装置，用于检测分配给算术运算单元，以及时钟信号供给控制单元，用于控制对每个算术运算单元的时钟信号的供给/停止运行，其中，当所述检测单元检测到所述检测单元时，所述时钟信号供给控制单元停止向所述算术运算单元供给所述时钟信号检测到分配给其的算术运算的完成，并且当检测装置检测到分配给它们的算术运算的完成时，重新开始向所有算术运算单元提供时钟信号用于下一个管线算术运算。

8. 发明授权

US07236634B2 Image encoding of moving pictures 失效
标题翻译：运动图像的图像编码
公开(公告)号：US07236634B2
公开(公告)日：2007-06-26
申请号：US10703547
申请日：2003-11-10
申请人： Junichi Miyakoshi , Masayuki Miyama , Masahiko Yoshimoto , Hideo Hashimoto , Kousuke Imamura
发明人： Junichi Miyakoshi , Masayuki Miyama , Masahiko Yoshimoto , Hideo Hashimoto , Kousuke Imamura
IPC分类号： G06K9/36
CPC分类号： H04N19/61 , H04N19/51
摘要： In an encoding method of moving pictures which generates a predictive picture for a current picture based on a reference picture and a motion vector, a macroblock is divided into subblocks. In each of the plurality of subblocks, an initial value of the motion vector is set and an evaluated value E on a difference between the current picture and the reference picture is calculated along a steepest descent direction to determine the minimum value. Then, the smallest evaluated value is selected among the minimum values obtained on the plurality of subblocks to determine the motion vector based on the pixel position of the smallest value.
摘要翻译：在基于参考图像和运动矢量生成当前图像的预测图像的运动图像的编码方法中，宏块被划分为子块。在多个子块中的每一个中，设置运动矢量的初始值，并且沿最陡下降方向计算当前画面与参考画面之间的差值的评估值E，以确定最小值。然后，从在多个子块上获得的最小值中选择最小的评估值，以基于最小值的像素位置来确定运动矢量。

9. 发明授权

US5379257A Semiconductor integrated circuit device having a memory and an operational unit integrated therein 失效
标题翻译：具有集成在其中的存储器和操作单元的半导体集成电路器件
公开(公告)号：US5379257A
公开(公告)日：1995-01-03
申请号：US767767
申请日：1991-09-30
申请人： Tetsuya Matsumura , Hiroshi Segawa , Kazuya Ishihara , Shinichi Uramoto , Masahiko Yoshimoto
发明人： Tetsuya Matsumura , Hiroshi Segawa , Kazuya Ishihara , Shinichi Uramoto , Masahiko Yoshimoto
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C13/00
CPC分类号： G11C7/1006 , G11C2207/104
摘要： A semiconductor integrated circuit device includes a memory cell array for storing data to be processed, and an operational unit for effecting a predetermined operation on the data read from the memory cell array. The memory cell array has first and second regions for storing first and second data words of first and second groups. The first data words and second data words each include a plurality of data bits. The first region includes a plurality of bit arrays for storing data bits of the same digit in the first data words, and the second region includes a plurality of bit arrays for storing data bite of the same digit in the second data words. The bit arrays of the first and second groups are arranged alternately in the order of digits of the data words. The bit arrays storing the data bits of the same digit form one subarray. The data bits in one data word are stored in the same positions of the bit arrays. The operational unit includes operational circuits each corresponding to one of the subarrays. Each operational circuit effects the predetermined operation on the data read from the two bit arrays in the corresponding subarray. Each bit array has selectors responsive to external addresses to select one column from each bit array and connect this column to a corresponding operational circuit.
摘要翻译：半导体集成电路装置包括用于存储要处理的数据的存储单元阵列和用于对从存储单元阵列读取的数据进行预定操作的操作单元。存储单元阵列具有用于存储第一和第二组的第一和第二数据字的第一和第二区域。第一数据字和第二数据字各自包括多个数据位。第一区域包括用于存储第一数据字中相同数位的数据位的多个位阵列，并且第二区域包括用于存储第二数据字中相同数字的数据位的多个位数组。第一组和第二组的位阵列以数据字的数位顺序交替排列。存储相同数位数据位的位数组形成一个子阵列。一个数据字中的数据位存储在位阵列的相同位置。操作单元包括各自对应于一个子阵列的操作电路。每个操作电路对从相应子阵列中的两个位阵列读取的数据执行预定的操作。每个位阵列具有响应于外部地址的选择器，从每个位阵列中选择一个列，并将该列连接到相应的运算电路。

10. 发明授权

US5053999A Semiconductor memory device having redundancy and capable of sequentially selecting memory cell lines 失效
标题翻译：半导体存储器件具有冗余并且能够顺序地选择存储器单元线
公开(公告)号：US5053999A
公开(公告)日：1991-10-01
申请号：US500328
申请日：1990-03-28
申请人： Tetsuya Matsumura , Masahiko Yoshimoto
发明人： Tetsuya Matsumura , Masahiko Yoshimoto
IPC分类号： G06F5/00 , G11C29/00
CPC分类号： G11C29/70 , G11C29/86 , G06F5/00
摘要： First-In First-Out (FIFO) memory device is disclosed. A ring pointer circuit sequentially and repeatedly selects memory cells in a memory cell array. When it is detected that a defective memory cell exists on a memory cell row, selection of that memory cell row is invalidated by the ring pointer circuit by cutting off a laser trimming line. In addition, by selectively cutting off laser trimming lines in a switching circuit and a redundancy ring pointer circuit, a redundancy memory cell row is selectively added in place of the defective memory cell row. Accordingly, stages required for the ring pointer circuit are maintained. In other words, the FIFO memory device having a defective memory cell is saved, resulting in improvement in yield in the manufacture.
摘要翻译：先进先出（FIFO）存储器件被公开。环形指针电路依次重复地选择存储单元阵列中的存储单元。当检测到存储单元行中存在有缺陷的存储单元时，通过切断激光修整线，通过环形指针电路对该存储单元行的选择无效。此外，通过选择性地切断开关电路和冗余环形指针电路中的激光微调线，选择性地添加冗余存储单元行来代替有缺陷的存储单元行。因此，保持环形指针电路所需的阶段。换句话说，具有缺陷存储单元的FIFO存储器件被保存，从而提高了制造中的产量。

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