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1. 发明申请

US20100262813A1 Detecting and Handling Short Forward Branch Conversion Candidates 审中-公开
标题翻译：检测和处理短期分支转换候选人
公开(公告)号：US20100262813A1
公开(公告)日：2010-10-14
申请号：US12423608
申请日：2009-04-14
申请人： Mary D. Brown , Richard W. Doing , Kevin N. Magill , Brian R. Mestan , Wolfram M. Sauer , Balaram Sinharoy , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
发明人： Mary D. Brown , Richard W. Doing , Kevin N. Magill , Brian R. Mestan , Wolfram M. Sauer , Balaram Sinharoy , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
IPC分类号： G06F9/38
CPC分类号： G06F9/30003 , G06F8/433 , G06F9/30058 , G06F9/30072 , G06F9/3017 , G06F9/30174 , G06F9/3844 , G06F9/3846 , G06F9/3855
摘要： Mechanisms, in a processor, are provided for detecting and handling short forward branch conversion candidates. The mechanisms identify a conditional branch in the computer code and determine if the short forward conditional branch is to be converted to a non-branching conditional sequence of instructions. Moreover, the mechanisms convert the conditional branch to a non-branching conditional sequence of instructions comprising a resolve instruction and one or more conditional instructions dependent on the resolve instruction. In addition, the mechanisms execute the non-branching conditional sequence of instructions in place of the conditional branch in the computer code and generate an output of the computer code based on the execution of the non-branching conditional sequence of instructions.
摘要翻译：在处理器中提供用于检测和处理短前进分支转换候选的机制。机制识别计算机代码中的条件分支，并确定短向前向条件分支是否要转换为非分支条件指令序列。此外，机制将条件分支转换为包括解决指令和取决于解析指令的一个或多个条件指令的非分支条件指令序列。此外，这些机制代替计算机代码中的条件分支执行非分支条件指令序列，并且基于非分支条件指令序列的执行生成计算机代码的输出。

2. 发明授权

US08661227B2 Multi-level register file supporting multiple threads 失效
标题翻译：支持多线程的多级寄存器文件
公开(公告)号：US08661227B2
公开(公告)日：2014-02-25
申请号：US12884411
申请日：2010-09-17
申请人： Christopher M. Abernathy , Mary D. Brown , Hung Q. Le , Dung Q. Nguyen
发明人： Christopher M. Abernathy , Mary D. Brown , Hung Q. Le , Dung Q. Nguyen
IPC分类号： G06F9/34
CPC分类号： G06F9/3851 , G06F9/30138
摘要： A processor includes an instruction fetch unit, an issue queue coupled to the instruction fetch unit, an execution unit coupled to the issue queue, and a multi-level register file including a first level register file having lower access latency and a second level register file having higher access latency. Each of the first and second level register files includes a plurality of physical registers for holding operands that is concurrently shared by a plurality of threads. The processor further includes a mapper that, at dispatch of an instruction specifying a source logical register from the instruction fetch unit to the issue queue, initiates a swap of a first operand associated with the source logical register that is in the second level register file with a second operand held in the first level register file. The issue queue, following the swap, issues the instruction to the execution unit for execution.
摘要翻译：处理器包括指令提取单元，耦合到指令获取单元的发行队列，耦合到发行队列的执行单元，以及包括具有较低访问延迟的第一级寄存器文件和第二级寄存器文件的多级寄存器文件具有更高的访问延迟。第一级和第二级寄存器文件中的每一个包括用于保持多个线程同时共享的操作数的多个物理寄存器。处理器还包括映射器，在从指令获取单元向发布队列调度指定源逻辑寄存器的指令时，启动与第二级寄存器文件中的源逻辑寄存器相关联的第一操作数的交换，在第一级寄存器文件中保存的第二个操作数。在交换之后的问题队列向执行单元发出指令以执行。

3. 发明授权

US08099582B2 Tracking deallocated load instructions using a dependence matrix 有权
标题翻译：使用依赖矩阵跟踪取消分配的加载指令
公开(公告)号：US08099582B2
公开(公告)日：2012-01-17
申请号：US12410024
申请日：2009-03-24
申请人： Christopher M. Abernathy , Mary D. Brown , William E. Burky , Todd A. Venton
发明人： Christopher M. Abernathy , Mary D. Brown , William E. Burky , Todd A. Venton
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/3857
摘要： A mechanism is provided for tracking deallocated load instructions. A processor detects whether a load instruction in a set of instructions in an issue queue has missed. Responsive to a miss of the load instruction, an instruction scheduler allocates the load instruction to a load miss queue and deallocates the load instruction from the issue queue. The instruction scheduler determines whether there is a dependence entry for the load instruction in an issue queue portion of a dependence matrix. Responsive to the existence of the dependence entry for the load instruction in the issue queue portion of the dependence matrix, the instruction scheduler reads data from the dependence entry of the issue queue portion of the dependence matrix that specifies a set of dependent instructions that are dependent on the load instruction and writes the data into a new entry in a load miss queue portion of the dependence matrix.
摘要翻译：提供了一种跟踪取消分配的加载指令的机制。处理器检测发送队列中的一组指令中的加载指令是否已经丢失。响应于加载指令的未命中，指令调度器将加载指令分配给加载缺省队列，并从发出队列中释放加载指令。指令调度器确定在依赖矩阵的发布队列部分中是否存在用于加载指令的依赖条目。响应于依赖矩阵的发布队列部分中的加载指令的依赖条目的存在，指令调度器从依赖矩阵的发布队列部分的依赖条目读取数据，该依赖矩阵指定一组依赖的依赖指令在加载指令中，将数据写入依赖矩阵的加载未命中队列部分中的新条目。

4. 发明授权

US08078999B2 Structure for implementing speculative clock gating of digital logic circuits 失效
标题翻译：用于实现数字逻辑电路的推测时钟门控的结构
公开(公告)号：US08078999B2
公开(公告)日：2011-12-13
申请号：US12112063
申请日：2008-04-30
申请人： Bartholomew Blaner , Mary D. Brown , William E. Burky , Todd A. Venton
发明人： Bartholomew Blaner , Mary D. Brown , William E. Burky , Todd A. Venton
IPC分类号： G06F17/50 , G06F1/04
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128
摘要： A design structure embodied in a non-transitory machine readable medium used in a design process includes an apparatus for implementing speculative clock gating of digital logic circuits, including operation valid logic configured to generate, in a first pipeline stage n, a valid control signal input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and speculative valid logic configured to generate, in the first pipeline stage, a speculative valid control signal used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly to the first register. The design structure includes a netlist describing the apparatus for implementing speculative clock gating of digital logic circuits included in a multiple stage pipeline design.
摘要翻译：体现在设计过程中使用的非暂时机器可读介质中的设计结构包括用于实现数字逻辑电路的推测时钟选通的装置，包括操作有效逻辑，其被配置为在第一流水线阶段n中生成有效的控制信号输入指示第二流水线级n + 1中的第一寄存器，指示操作何时由第二流水线级n + 1执行的有效控制信号; 以及推测有效逻辑，其被配置为在所述第一流水线级中产生用于在第二流水线级中对多个附加寄存器门控时钟信号的推测有效控制信号，其中所述推测有效控制信号仅使用用于产生有效控制信号的控制输入的总数，并且其中时钟信号被直接发送到第一寄存器。该设计结构包括描述用于实现包括在多级管道设计中的数字逻辑电路的推测时钟门控的装置的网表。

5. 发明申请

US20100077181A1 System and Method for Issuing Load-Dependent Instructions in an Issue Queue in a Processing Unit of a Data Processing System 有权
标题翻译：用于在数据处理系统的处理单元中的问题队列中发出负载相关指令的系统和方法
公开(公告)号：US20100077181A1
公开(公告)日：2010-03-25
申请号：US12236175
申请日：2008-09-23
申请人： Christopher M. Abernathy , Mary D. Brown , William E. Burky , Todd A. Venton
发明人： Christopher M. Abernathy , Mary D. Brown , William E. Burky , Todd A. Venton
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3824 , G06F9/3838
摘要： A system and method for issuing load-dependent instructions in an issue queue in a processing unit. A load miss queue is provided. The load miss queue comprises a physical address field, an issue queue position field, a valid identifier field, a source identifier field, and a data type field. A load instruction that misses a first level cache is dispatched, and both the physical address field and the data type field are set. A load-dependent instruction is identified. In response to indentifying the load-dependent instruction, each of the issue queue position field, valid identifier field, and source identifier field are set. If the issue queue position field refers to a flushed instruction, the valid identifier field is cleared. The load instruction is recycled, and a value of the valid identifier field is determined. The load-dependent instruction is then selected for issue on a next processing cycle independent of an age of the load-dependent instruction.
摘要翻译：一种用于在处理单元中的发布队列中发布负载相关指令的系统和方法。提供了一个加载缺失队列。负载遗漏队列包括物理地址字段，发布队列位置字段，有效标识符字段，源标识符字段和数据类型字段。调度丢失第一级缓存的加载指令，同时设置物理地址字段和数据类型字段。识别负载相关的指令。响应于确定负载相关指令，设置每个发布队列位置字段，有效标识符字段和源标识符字段。如果问题队列位置字段引用了刷新指令，则清除有效的标识符字段。加载指令被回收，确定有效标识符字段的值。然后选择负载相关的指令用于在下一个处理周期中发出独立于负载相关指令的年龄。

6. 发明申请

US20090193283A1 DESIGN STRUCTURE FOR IMPLEMENTING SPECULATIVE CLOCK GATING OF DIGITAL LOGIC CIRCUITS 失效
标题翻译：实现数字逻辑电路的时钟调节的设计结构
公开(公告)号：US20090193283A1
公开(公告)日：2009-07-30
申请号：US12112063
申请日：2008-04-30
申请人： Bartholomew Blaner , Mary D. Brown , William E. Burky , Todd A. Venton
发明人： Bartholomew Blaner , Mary D. Brown , William E. Burky , Todd A. Venton
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128
摘要： A design structure embodied in a machine readable medium used in a design process includes an apparatus for implementing speculative clock gating of digital logic circuits, including operation valid logic configured to generate, in a first pipeline stage n, a valid control signal that is input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and speculative valid logic configured to generate, in the first pipeline stage, a speculative valid control signal that is used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly to the first register.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括用于实现数字逻辑电路的推测时钟选通的装置，包括操作有效逻辑，其被配置为在第一流水线阶段n中产生输入到在第二流水线级n + 1中的第一寄存器，指示何时由第二流水线级n + 1执行操作的有效控制信号; 以及推测有效逻辑，其被配置为在第一流水线级中生成用于在第二流水线级中将时钟信号选择到多个附加寄存器的推测有效控制信号，其中，仅使用用于产生有效控制信号的控制输入总数的子集，并且其中时钟信号被直接发送到第一寄存器。

7. 发明授权

US08631223B2 Register file supporting transactional processing 失效
标题翻译：注册文件支持事务处理
公开(公告)号：US08631223B2
公开(公告)日：2014-01-14
申请号：US12778235
申请日：2010-05-12
申请人： Christopher M. Abernathy , Mary D. Brown , Hung Q. Le , Dung Q. Nguyen
发明人： Christopher M. Abernathy , Mary D. Brown , Hung Q. Le , Dung Q. Nguyen
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3004 , G06F9/30087 , G06F9/30138 , G06F9/384
摘要： A processor includes an instruction sequencing unit, execution unit, and multi-level register file including a first level register file having a lower access latency and a second level register file having a higher access latency. Responsive to the processor processing a second instruction in a transactional code section to obtain as an execution result a second register value of the logical register, the mapper moves a first register value of the logical register to the second level register file, places the second register value in the first level register file, marks the second register value as speculative, and replaces a first mapping for the logical register with a second mapping. Responsive to unsuccessful termination of the transactional code section, the mapper designates the second register value in the first level register file as invalid so that the first register value in the second level register file becomes the working value.
摘要翻译：处理器包括指令排序单元，执行单元和多级寄存器文件，其包括具有较低访问延迟的第一级寄存器文件和具有较高访问延迟的第二级寄存器文件。响应于处理器处理事务代码部分中的第二指令以获得逻辑寄存器的第二寄存器值作为执行结果，映射器将逻辑寄存器的第一寄存器值移动到第二级寄存器堆，将第二寄存器在第一级寄存器文件中的值，将第二寄存器值标记为推测，并用第二映射替换逻辑寄存器的第一映射。响应于事务代码段的不成功终止，映射器将第一级寄存器文件中的第二寄存器值指定为无效，使得第二级寄存器文件中的第一寄存器值变为工作值。

8. 发明申请

US20120216004A1 THREAD TRANSITION MANAGEMENT 失效
标题翻译：螺纹过渡管理
公开(公告)号：US20120216004A1
公开(公告)日：2012-08-23
申请号：US13032737
申请日：2011-02-23
申请人： Christopher M. Abernathy , Mary D. Brown , Susan E. Eisen , James A. Kahle , Hung Q. Le , Dung Q. Nguyen
发明人： Christopher M. Abernathy , Mary D. Brown , Susan E. Eisen , James A. Kahle , Hung Q. Le , Dung Q. Nguyen
IPC分类号： G06F12/02
CPC分类号： G06F9/30101 , G06F9/30123 , G06F9/3013 , G06F9/384 , G06F9/3851 , G06F9/461
摘要： Various systems, processes, products, and techniques may be used to manage thread transitions. In particular implementations, a system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination.
摘要翻译：可以使用各种系统，过程，产品和技术来管理线程转换。在特定实现中，用于管理线程转换的系统和过程可以包括确定要对两个数据寄存器组的相对使用进行转换的能力，并且基于转换确定来确定是否将线程数据移入至少一个数据寄存器设置为二级寄存器。系统和过程还可以包括基于移动确定将线程数据从至少一个数据寄存器集合移动到第二级寄存器的能力。

9. 发明授权

US08239661B2 System and method for double-issue instructions using a dependency matrix 失效
标题翻译：使用依赖矩阵的双重指令的系统和方法
公开(公告)号：US08239661B2
公开(公告)日：2012-08-07
申请号：US12199853
申请日：2008-08-28
申请人： Christopher M. Abernathy , Mary D. Brown , Todd A. Venton
发明人： Christopher M. Abernathy , Mary D. Brown , Todd A. Venton
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3838 , G06F9/3017 , G06F9/3867
摘要： A method for double-issue complex instructions receives a complex instruction comprising a first portion and a second portion. The method sets a single issue queue slot and allocates an execution unit for the complex instruction, and identifies dependencies in the first and second portions. The method sets a dependency matrix slot and a consumers table slot for the first and section portion. In the event the first portion dependencies have been satisfied, the method issues the first portion and then issues the second portion from the single issue queue slot. In the event the second portion dependencies have not been satisfied, the method cancels the second portion issue.
摘要翻译：一种用于双重复杂指令的方法接收包括第一部分和第二部分的复杂指令。该方法设置单个问题队列插槽，并为复杂指令分配执行单元，并识别第一和第二部分的依赖关系。该方法为第一和部分部分设置依赖矩阵槽和消费者表槽。在满足第一部分依赖性的情况下，该方法发出第一部分，然后从单个问题队列插槽中发出第二部分。在第二部分相关性尚未得到满足的情况下，该方法取消了第二部分问题。

10. 发明授权

US07971161B2 Apparatus and method for implementing speculative clock gating of digital logic circuits 有权
标题翻译：用于实现数字逻辑电路的推测时钟门控的装置和方法
公开(公告)号：US07971161B2
公开(公告)日：2011-06-28
申请号：US12019718
申请日：2008-01-25
申请人： Bartholomew Blaner , Mary D. Brown , William E. Burky , Todd A. Venton
发明人： Bartholomew Blaner , Mary D. Brown , William E. Burky , Todd A. Venton
IPC分类号： G06F17/50 , G06F1/04
CPC分类号： G06F1/3203 , G06F1/10 , G06F1/3237 , Y02D10/128
摘要： A method for implementing speculative clock gating of digital logic circuits in a multiple stage pipeline design includes generating, in a first pipeline stage n, a valid control signal that is input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and generating, in the first pipeline stage, a speculative valid control signal that is used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly, without gating, to the first register in the second pipeline stage.
摘要翻译：一种用于在多级流水线设计中实现数字逻辑电路的推测时钟门控的方法包括在第一流水线级n中产生输入到第二流水线级n + 1中的第一寄存器的有效控制信号，有效控制指示操作何时被第二流水线阶段n + 1执行的信号; 以及在第一流水线级中生成用于在第二流水线级中对多个附加寄存器门控时钟信号的推测有效控制信号，其中，仅使用总数的子集来产生推测有效控制信号用于产生有效控制信号的控制输入，并且其中在第二流水线级中将时钟信号直接发送到第一流水线级的第一寄存器。

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