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1. 发明授权

US08631223B2 Register file supporting transactional processing 失效
标题翻译：注册文件支持事务处理
公开(公告)号：US08631223B2
公开(公告)日：2014-01-14
申请号：US12778235
申请日：2010-05-12
申请人： Christopher M. Abernathy , Mary D. Brown , Hung Q. Le , Dung Q. Nguyen
发明人： Christopher M. Abernathy , Mary D. Brown , Hung Q. Le , Dung Q. Nguyen
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3004 , G06F9/30087 , G06F9/30138 , G06F9/384
摘要： A processor includes an instruction sequencing unit, execution unit, and multi-level register file including a first level register file having a lower access latency and a second level register file having a higher access latency. Responsive to the processor processing a second instruction in a transactional code section to obtain as an execution result a second register value of the logical register, the mapper moves a first register value of the logical register to the second level register file, places the second register value in the first level register file, marks the second register value as speculative, and replaces a first mapping for the logical register with a second mapping. Responsive to unsuccessful termination of the transactional code section, the mapper designates the second register value in the first level register file as invalid so that the first register value in the second level register file becomes the working value.
摘要翻译：处理器包括指令排序单元，执行单元和多级寄存器文件，其包括具有较低访问延迟的第一级寄存器文件和具有较高访问延迟的第二级寄存器文件。响应于处理器处理事务代码部分中的第二指令以获得逻辑寄存器的第二寄存器值作为执行结果，映射器将逻辑寄存器的第一寄存器值移动到第二级寄存器堆，将第二寄存器在第一级寄存器文件中的值，将第二寄存器值标记为推测，并用第二映射替换逻辑寄存器的第一映射。响应于事务代码段的不成功终止，映射器将第一级寄存器文件中的第二寄存器值指定为无效，使得第二级寄存器文件中的第一寄存器值变为工作值。

2. 发明申请

US20120216004A1 THREAD TRANSITION MANAGEMENT 失效
标题翻译：螺纹过渡管理
公开(公告)号：US20120216004A1
公开(公告)日：2012-08-23
申请号：US13032737
申请日：2011-02-23
申请人： Christopher M. Abernathy , Mary D. Brown , Susan E. Eisen , James A. Kahle , Hung Q. Le , Dung Q. Nguyen
发明人： Christopher M. Abernathy , Mary D. Brown , Susan E. Eisen , James A. Kahle , Hung Q. Le , Dung Q. Nguyen
IPC分类号： G06F12/02
CPC分类号： G06F9/30101 , G06F9/30123 , G06F9/3013 , G06F9/384 , G06F9/3851 , G06F9/461
摘要： Various systems, processes, products, and techniques may be used to manage thread transitions. In particular implementations, a system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination.
摘要翻译：可以使用各种系统，过程，产品和技术来管理线程转换。在特定实现中，用于管理线程转换的系统和过程可以包括确定要对两个数据寄存器组的相对使用进行转换的能力，并且基于转换确定来确定是否将线程数据移入至少一个数据寄存器设置为二级寄存器。系统和过程还可以包括基于移动确定将线程数据从至少一个数据寄存器集合移动到第二级寄存器的能力。

3. 发明授权

US08661227B2 Multi-level register file supporting multiple threads 失效
标题翻译：支持多线程的多级寄存器文件
公开(公告)号：US08661227B2
公开(公告)日：2014-02-25
申请号：US12884411
申请日：2010-09-17
申请人： Christopher M. Abernathy , Mary D. Brown , Hung Q. Le , Dung Q. Nguyen
发明人： Christopher M. Abernathy , Mary D. Brown , Hung Q. Le , Dung Q. Nguyen
IPC分类号： G06F9/34
CPC分类号： G06F9/3851 , G06F9/30138
摘要： A processor includes an instruction fetch unit, an issue queue coupled to the instruction fetch unit, an execution unit coupled to the issue queue, and a multi-level register file including a first level register file having lower access latency and a second level register file having higher access latency. Each of the first and second level register files includes a plurality of physical registers for holding operands that is concurrently shared by a plurality of threads. The processor further includes a mapper that, at dispatch of an instruction specifying a source logical register from the instruction fetch unit to the issue queue, initiates a swap of a first operand associated with the source logical register that is in the second level register file with a second operand held in the first level register file. The issue queue, following the swap, issues the instruction to the execution unit for execution.
摘要翻译：处理器包括指令提取单元，耦合到指令获取单元的发行队列，耦合到发行队列的执行单元，以及包括具有较低访问延迟的第一级寄存器文件和第二级寄存器文件的多级寄存器文件具有更高的访问延迟。第一级和第二级寄存器文件中的每一个包括用于保持多个线程同时共享的操作数的多个物理寄存器。处理器还包括映射器，在从指令获取单元向发布队列调度指定源逻辑寄存器的指令时，启动与第二级寄存器文件中的源逻辑寄存器相关联的第一操作数的交换，在第一级寄存器文件中保存的第二个操作数。在交换之后的问题队列向执行单元发出指令以执行。

4. 发明授权

US08725993B2 Thread transition management 失效
标题翻译：线程转换管理
公开(公告)号：US08725993B2
公开(公告)日：2014-05-13
申请号：US13032737
申请日：2011-02-23
申请人： Christopher M. Abernathy , Mary D. Brown , Susan E. Eisen , James A. Kahle , Hung Q. Le , Dung Q. Nguyen
发明人： Christopher M. Abernathy , Mary D. Brown , Susan E. Eisen , James A. Kahle , Hung Q. Le , Dung Q. Nguyen
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/30101 , G06F9/30123 , G06F9/3013 , G06F9/384 , G06F9/3851 , G06F9/461
摘要： Various systems, processes, products, and techniques may be used to manage thread transitions. In particular implementations, a system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination.
摘要翻译：可以使用各种系统，过程，产品和技术来管理线程转换。在特定实现中，用于管理线程转换的系统和过程可以包括确定要对两个数据寄存器组的相对使用进行转换的能力，并且基于转换确定来确定是否将线程数据移入至少一个数据寄存器设置为二级寄存器。系统和过程还可以包括基于移动确定将线程数据从至少一个数据寄存器集合移动到第二级寄存器的能力。

5. 发明授权

US08661228B2 Multi-level register file supporting multiple threads 失效
公开(公告)号：US08661228B2
公开(公告)日：2014-02-25
申请号：US13448024
申请日：2012-04-16
申请人： Christopher M. Abernathy , Mary D. Brown , Hung Q. Le , Dung Q. Nguyen
发明人： Christopher M. Abernathy , Mary D. Brown , Hung Q. Le , Dung Q. Nguyen
IPC分类号： G06F9/34
CPC分类号： G06F9/3851 , G06F9/30138
摘要： A processor includes an instruction fetch unit, an issue queue coupled to the instruction fetch unit, an execution unit coupled to the issue queue, and a multi-level register file including a first level register file having lower access latency and a second level register file having higher access latency. Each of the first and second level register files includes a plurality of physical registers for holding operands that is concurrently shared by a plurality of threads. The processor further includes a mapper that, at dispatch of an instruction specifying a source logical register from the instruction fetch unit to the issue queue, initiates a swap of a first operand associated with the source logical register that is in the second level register file with a second operand held in the first level register file. The issue queue, following the swap, issues the instruction to the execution unit for execution.

6. 发明授权

US08037366B2 Issuing instructions in-order in an out-of-order processor using false dependencies 有权
标题翻译：使用错误的依赖关系在乱序处理器中按顺序发布指令
公开(公告)号：US08037366B2
公开(公告)日：2011-10-11
申请号：US12409981
申请日：2009-03-24
申请人： Christopher M. Abernathy , Mary D. Brown , Dung Q. Nguyen , Todd A. Venton
发明人： Christopher M. Abernathy , Mary D. Brown , Dung Q. Nguyen , Todd A. Venton
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F9/3838 , G06F9/3851 , G06F9/3863 , G06F9/3885 , G06F11/0721
摘要： A mechanism is provided for issuing instructions. An instruction dispatch unit receives an instruction for dispatch to one of a plurality of execution units. The instruction dispatch unit analyzes a tag register to determine whether a previous tag associated with a previous instruction has been stored in the tag register. Responsive to the previous tag associated with the previous instruction failing to be stored in the tag register, the instruction dispatch unit storing a tag corresponding to the instruction in the tag register. The instruction dispatch unit dispatches the instruction to an issue queue for issue to the one of the plurality of execution units.
摘要翻译：提供了发出指令的机制。指令调度单元接收用于发送到多个执行单元之一的指令。指令调度单元分析标签寄存器以确定与先前指令相关联的先前标签是否已经存储在标签寄存器中。指令调度单元响应于与先前指令相关联的先前的标签不能存储在标签寄存器中，存储与标签寄存器中的指令相对应的标签。指令调度单元将指令发送到多个执行单元中的一个执行单元。

7. 发明申请

US20080195850A1 Method and System for Restoring Register Mapper States for an Out-Of-Order Microprocessor 失效
标题翻译：用于为无序微处理器恢复寄存器映射器状态的方法和系统
公开(公告)号：US20080195850A1
公开(公告)日：2008-08-14
申请号：US11674754
申请日：2007-02-14
申请人： Christopher M. Abernathy , Mary D. Brown , Dung Q. Nguyen , Joel A. Silberman
发明人： Christopher M. Abernathy , Mary D. Brown , Dung Q. Nguyen , Joel A. Silberman
IPC分类号： G06F9/38
CPC分类号： G06F9/3863 , G06F9/3802 , G06F9/384 , G06F9/3842 , G06F9/3885
摘要： A method of restoring register mapper states for an out-of-order microprocessor. A processor maps a logical register to a physical register in a map table in response to a first instruction. Instruction sequencing logic records a second speculatively executed instruction as a most recently dispatched instruction in the map table when the second instruction maps the same logical register of the first instruction. The instruction sequencing logic sets an evictor instruction tag (ITAG) of the first instruction in the map table when the second instruction maps a same logical register of the first instruction. The instruction sequencing logic detects mispredicted speculative instructions, determines which instructions in the map table were dispatched prior to the mispredicted speculative instructions, and restores the map table to a state prior to the mispredicted speculative instructions by utilizing the evictor ITAG to restore one or more A bits in the map table data structure.
摘要翻译：一种恢复无序微处理器的寄存器映射器状态的方法。处理器响应于第一指令将逻辑寄存器映射到地图表中的物理寄存器。当第二指令映射第一指令的相同逻辑寄存器时，指令排序逻辑将第二推测执行指令记录为映射表中最近调度的指令。当第二指令映射第一指令的相同逻辑寄存器时，指令排序逻辑设置映射表中的第一指令的撤销指令标签（ITAG）。指令排序逻辑检测误预测的推测指令，确定映射表中的哪些指令在误预测的推测指令之前被分派，并且通过利用驱逐者ITAG恢复一个或多个A，将映射表恢复到误预测的推测指令之前的状态位图中的数据结构。

8. 发明申请

US20100251016A1 Issuing Instructions In-Order in an Out-of-Order Processor Using False Dependencies 有权
标题翻译：在使用虚假依赖关系的乱序处理器中发布使用说明书
公开(公告)号：US20100251016A1
公开(公告)日：2010-09-30
申请号：US12409981
申请日：2009-03-24
申请人： Christopher M. Abernathy , Mary D. Brown , Dung Q. Nguyen , Todd A. Venton
发明人： Christopher M. Abernathy , Mary D. Brown , Dung Q. Nguyen , Todd A. Venton
IPC分类号： G06F9/30 , G06F11/07
CPC分类号： G06F11/0793 , G06F9/3838 , G06F9/3851 , G06F9/3863 , G06F9/3885 , G06F11/0721
摘要： A mechanism is provided for issuing instructions. An instruction dispatch unit receives an instruction for dispatch to one of a plurality of execution units. The instruction dispatch unit analyzes a tag register to determine whether a previous tag associated with a previous instruction has been stored in the tag register. Responsive to the previous tag associated with the previous instruction failing to be stored in the tag register, the instruction dispatch unit storing a tag corresponding to the instruction in the tag register. The instruction dispatch unit dispatches the instruction to an issue queue for issue to the one of the plurality of execution units.
摘要翻译：提供了发出指令的机制。指令调度单元接收用于发送到多个执行单元之一的指令。指令调度单元分析标签寄存器以确定与先前指令相关联的先前标签是否已经存储在标签寄存器中。指令调度单元响应于与先前指令相关联的先前的标签不能存储在标签寄存器中，存储与标签寄存器中的指令相对应的标签。指令调度单元将指令发送到多个执行单元中的一个执行单元。

9. 发明授权

US07689812B2 Method and system for restoring register mapper states for an out-of-order microprocessor 失效
标题翻译：用于恢复无序微处理器的寄存器映射器状态的方法和系统
公开(公告)号：US07689812B2
公开(公告)日：2010-03-30
申请号：US11674754
申请日：2007-02-14
申请人： Christopher M. Abernathy , Mary D. Brown , Dung Q. Nguyen , Joel A. Silberman
发明人： Christopher M. Abernathy , Mary D. Brown , Dung Q. Nguyen , Joel A. Silberman
IPC分类号： G06F15/00 , G06F9/00
CPC分类号： G06F9/3863 , G06F9/3802 , G06F9/384 , G06F9/3842 , G06F9/3885
摘要： A method of restoring register mapper states for an out-of-order microprocessor. A processor maps a logical register to a physical register in a map table in response to a first instruction. Instruction sequencing logic records a second speculatively executed instruction as a most recently dispatched instruction in the map table when the second instruction maps the same logical register of the first instruction. The instruction sequencing logic sets an evictor instruction tag (ITAG) of the first instruction in the map table when the second instruction maps a same logical register of the first instruction. The instruction sequencing logic detects mispredicted speculative instructions, determines which instructions in the map table were dispatched prior to the mispredicted speculative instructions, and restores the map table to a state prior to the mispredicted speculative instructions by utilizing the evictor ITAG to restore one or more A bits in the map table data structure.
摘要翻译：一种恢复无序微处理器的寄存器映射器状态的方法。处理器响应于第一指令将逻辑寄存器映射到地图表中的物理寄存器。当第二指令映射第一指令的相同逻辑寄存器时，指令排序逻辑将第二推测执行指令记录为映射表中最近调度的指令。当第二指令映射第一指令的相同逻辑寄存器时，指令排序逻辑设置映射表中的第一指令的撤销指令标签（ITAG）。指令排序逻辑检测误预测的推测指令，确定映射表中的哪些指令在误预测的推测指令之前被分派，并且通过利用驱逐者ITAG恢复一个或多个A，将映射表恢复到误预测的推测指令之前的状态位图中的数据结构。

10. 发明申请

US20100257341A1 Selective Execution Dependency Matrix 审中-公开
标题翻译：选择性执行依赖矩阵
公开(公告)号：US20100257341A1
公开(公告)日：2010-10-07
申请号：US12417801
申请日：2009-04-03
申请人： Mary D. Brown , James W. Bishop , William E. Burky , John B. Griswell, JR. , Dung Q. Nguyen , Todd A. Venton
发明人： Mary D. Brown , James W. Bishop , William E. Burky , John B. Griswell, JR. , Dung Q. Nguyen , Todd A. Venton
IPC分类号： G06F9/30
CPC分类号： G06F9/3838
摘要： A processor having a dependency matrix comprises a first array comprising a plurality of cells arranged in a plurality of columns and a plurality of rows. Each row represents an instruction in a processor execution queue and each cell represents a dependency relationship between two instructions in the processor execution queue. A first latch couples to the first array and comprises a first bit, the first bit indicating a first status. A second latch couples to the first array and comprises a second bit, the second bit indicating a second status. A first read port couples to the first array, comprising a first read wordline and a first read bitline. The first read wordline couples to the first latch and a first column and asserts a first available signal based on the first bit. The first read bitline couples to a first row and generates a first ready signal based on the first available signal and a first cell. A second read port couples to the first array and comprises a second read wordline and a second read bitline. The second read wordline couples to the second latch and the first column and asserts a second available signal based on the second bit. The second read bitline couples to the first row and generates a second ready signal based on the second read wordline and the first cell.
摘要翻译：具有依赖矩阵的处理器包括第一阵列，其包括以多个列排列的多个单元和多个行。每行表示处理器执行队列中的指令，每个单元表示处理器执行队列中的两个指令之间的依赖关系。第一锁存器耦合到第一阵列并且包括第一位，第一位指示第一状态。第二锁存器耦合到第一阵列并且包括第二位，第二位指示第二状态。第一读取端口耦合到第一阵列，包括第一读取字线和第一读取位线。第一读取字线耦合到第一锁存器和第一列，并基于第一位置位第一可用信号。第一读取位线耦合到第一行并且基于第一可用信号和第一单元产生第一就绪信号。第二读取端口耦合到第一阵列并且包括第二读取字线和第二读取位线。第二读取字线耦合到第二锁存器和第一列，并基于第二位置位第二可用信号。第二读取位线耦合到第一行，并且基于第二读取字线和第一单元产生第二就绪信号。

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