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1. 发明授权

US07436019B2 Non-volatile memory cells shaped to increase coupling to word lines 有权
标题翻译：非易失性存储单元成形为增加与字线的耦合
公开(公告)号：US07436019B2
公开(公告)日：2008-10-14
申请号：US11622634
申请日：2007-01-12
申请人： Jeffrey W. Lutze , Tuan Pham , Masaaki Higashitani
发明人： Jeffrey W. Lutze , Tuan Pham , Masaaki Higashitani
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11521
摘要： A non-volatile memory array has word lines coupled to floating gates, the floating gates having an upper portion that is adapted to provide increased surface area, and thereby, to provide increased coupling to the word lines. Shielding between floating gates is also provided. The upper portion covers part of a lower portion of the floating gate and leaves a part of the lower portion uncovered. A control gate is coplanar with a top surface of the upper portion, a vertical side of the upper portion, and the uncovered portion of the lower portion.
摘要翻译：非易失性存储器阵列具有耦合到浮动栅极的字线，浮动栅极具有适于提供增加的表面积的上部部分，从而提供增加的与字线的耦合。还提供了浮动门之间的屏蔽。上部覆盖浮动门的下部的一部分并且使下部的未被覆盖的部分离开。控制栅极与上部的上表面，上部的垂直侧和下部的未覆盖部分共面。

2. 发明申请

US20080248621A1 Integrated Non-Volatile Memory And Peripheral Circuitry Fabrication 有权
标题翻译：集成非易失性存储器和外围电路制造
公开(公告)号：US20080248621A1
公开(公告)日：2008-10-09
申请号：US12058512
申请日：2008-03-28
申请人： James Kai , Tuan Pham , Masaaki Higashitani , George Matamis , Takashi Orimoto
发明人： James Kai , Tuan Pham , Masaaki Higashitani , George Matamis , Takashi Orimoto
IPC分类号： H01L21/336
CPC分类号： H01L27/11529 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11536 , H01L27/11539
摘要： Non-volatile memory and integrated memory and peripheral circuitry fabrication processes are provided. Sets of charge storage regions, such as NAND strings including multiple non-volatile storage elements, are formed over a semiconductor substrate using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates for the charge storage regions and the gate regions of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions of these devices can be formed from the layer forming the control gates of the memory array.
摘要翻译：提供非易失性存储器和集成存储器和外围电路制造工艺。使用诸如第一多晶硅层的电荷存储材料层在半导体衬底上形成诸如包括多个非易失性存储元件的NAND串的电荷存储区的集合。中间电介质层设置在电荷存储区域的上方。将诸如第二多晶硅层的导电材料层沉积在衬底上并被蚀刻以形成用于存储元件组的选择晶体管的电荷存储区域和栅极区域的控制栅极。从衬底的一部分去除第一层多晶硅，便于仅从第二层多晶硅制造选择晶体管栅极区。外围电路形成也被并入到制造过程中以形成诸如高电压和逻辑晶体管的器件的栅极区域。这些器件的栅极区域可以由形成存储器阵列的控制栅极的层形成。

3. 发明申请

US20080074920A1 Nonvolatile Memory with Reduced Coupling Between Floating Gates 审中-公开
标题翻译：浮动闸门耦合减少的非易失性存储器
公开(公告)号：US20080074920A1
公开(公告)日：2008-03-27
申请号：US11534139
申请日：2006-09-21
申请人： Henry Chien , George Matamis , Tuan Pham , Masaaki Higashitani , Hidetaka Horiuchi , Jeffrey W. Lutze , Nima Mokhlesi , Yupin Kawing Fong
发明人： Henry Chien , George Matamis , Tuan Pham , Masaaki Higashitani , Hidetaka Horiuchi , Jeffrey W. Lutze , Nima Mokhlesi , Yupin Kawing Fong
IPC分类号： G11C5/06
CPC分类号： H01L27/115 , H01L27/11521
摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.
摘要翻译：非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。相邻的串由浅沟槽隔离结构隔离。具有倒T形浮置栅极的阵列可以以自对准的方式形成。

4. 发明申请

US20070087504A1 Integration process flow for flash devices with low gap fill aspect ratio 有权
标题翻译：具有低间隙填充宽高比的闪存器件的集成工艺流程
公开(公告)号：US20070087504A1
公开(公告)日：2007-04-19
申请号：US11254142
申请日：2005-10-18
申请人： Tuan Pham , Masaaki Higashitani
发明人： Tuan Pham , Masaaki Higashitani
IPC分类号： H01L21/336 , H01L21/76
CPC分类号： H01L27/11526 , H01L21/31111 , H01L21/3212 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11531
摘要： A non-volatile memory is formed having shallow trench isolation structures between floating gates and having control gates extending between floating gates where shallow trench isolation dielectric is etched. Control of etch depth is achieved using ion implantation to create a layer of dielectric with a high etch rate compared with the underlying dielectric. A conductive layer overlies the substrate during implantation. A substrate having small polysilicon features in a memory array and large polysilicon features in a peripheral area is accurately planarized using protrusions in the peripheral area and a soft chemical mechanical polishing step that stops when protrusions are removed.
摘要翻译：形成在浮动栅极之间具有浅沟槽隔离结构并且具有在浮动栅极之间延伸的控制栅极的非易失性存储器，其中浅沟槽隔离电介质被蚀刻。使用离子注入实现蚀刻深度的控制，以与下层电介质相比形成具有高蚀刻速率的电介质层。在植入期间，导电层覆盖衬底。存储器阵列中具有小的多晶硅特征的基板和外围区域中的大多晶硅特征使用周边区域中的突起精细地平坦化，并且当突起被去除时停止的软化学机械抛光步骤。

5. 发明授权

US08853763B2 Integrated circuits with sidewall nitridation 有权
标题翻译：具有侧壁氮化的集成电路
公开(公告)号：US08853763B2
公开(公告)日：2014-10-07
申请号：US13607375
申请日：2012-09-07
申请人： Tuan Pham , Sanghyun Lee , Masato Horiike , Klaus Schuegraf , Masaaki Higashitani , Keiichi Isono
发明人： Tuan Pham , Sanghyun Lee , Masato Horiike , Klaus Schuegraf , Masaaki Higashitani , Keiichi Isono
IPC分类号： H01L29/76 , H01L27/115 , H01L29/66 , H01L21/28
CPC分类号： H01L27/11548 , H01L21/2815 , H01L27/11529 , H01L29/66825
摘要： Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.
摘要翻译：半导体器件设置有用于在制造工艺期间保护侧壁特征的封装膜，例如蚀刻以形成隔离区域。在非易失性闪速存储器中，例如，沟槽隔离工艺被分成段以沿着电荷存储材料的侧壁并入封装膜。在层堆叠上形成图案，随后蚀刻电荷存储材料，以形成沿着衬底的列方向延伸的条带，其间具有隧道介电材料层。在蚀刻基板之前，沿着电荷存储材料条的侧壁形成封装膜。封装膜可以在随后的清洁，氧化和蚀刻工艺期间保护电荷存储材料的侧壁。在另一个实例中，同时形成封装膜，同时蚀刻以形成电荷存储材料条和隔离槽。

6. 发明申请

US20120326220A1 Integrated Circuits With Sidewall Nitridation 有权
标题翻译：集成电路与侧壁氮化
公开(公告)号：US20120326220A1
公开(公告)日：2012-12-27
申请号：US13607375
申请日：2012-09-07
申请人： Tuan Pham , Sanghyun Lee , Masato Horiike , Klaus Schuegraf , Masaaki Higashitani , Keiichi Isono
发明人： Tuan Pham , Sanghyun Lee , Masato Horiike , Klaus Schuegraf , Masaaki Higashitani , Keiichi Isono
IPC分类号： H01L29/78
CPC分类号： H01L27/11548 , H01L21/2815 , H01L27/11529 , H01L29/66825
摘要： Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.
摘要翻译：半导体器件设置有用于在制造工艺期间保护侧壁特征的封装膜，例如蚀刻以形成隔离区域。在非易失性闪速存储器中，例如，沟槽隔离工艺被分成段以沿着电荷存储材料的侧壁并入封装膜。在层堆叠上形成图案，随后蚀刻电荷存储材料，以形成沿着衬底的列方向延伸的条带，其间具有隧道介电材料层。在蚀刻基板之前，沿着电荷存储材料条的侧壁形成封装膜。封装膜可以在随后的清洁，氧化和蚀刻工艺期间保护电荷存储材料的侧壁。在另一个实例中，同时形成封装膜，同时蚀刻以形成电荷存储材料条和隔离槽。

7. 发明申请

US20110111583A1 METHOD OF REDUCING COUPLING BETWEEN FLOATING GATES IN NONVOLATILE MEMORY 有权
标题翻译：降低非易失性存储器中浮动栅之间耦合的方法
公开(公告)号：US20110111583A1
公开(公告)日：2011-05-12
申请号：US13010563
申请日：2011-01-20
申请人： Henry Chien , George Matamis , Tuan Pham , Masaaki Higashitani , Hidetaka Horiuchi , Jeffrey W. Lutze , Nima Mokhlesi , Yupin Kawing Fong
发明人： Henry Chien , George Matamis , Tuan Pham , Masaaki Higashitani , Hidetaka Horiuchi , Jeffrey W. Lutze , Nima Mokhlesi , Yupin Kawing Fong
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures.
摘要翻译：非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。相邻的串由浅沟槽隔离结构隔离。

8. 发明授权

US07704832B2 Integrated non-volatile memory and peripheral circuitry fabrication 有权
标题翻译：集成的非易失性存储器和外围电路制造
公开(公告)号：US07704832B2
公开(公告)日：2010-04-27
申请号：US12058512
申请日：2008-03-28
申请人： James Kai , Tuan Pham , Masaaki Higashitani , George Matamis , Takashi Orimoto
发明人： James Kai , Tuan Pham , Masaaki Higashitani , George Matamis , Takashi Orimoto
IPC分类号： H01L21/8247
CPC分类号： H01L27/11529 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11536 , H01L27/11539
摘要： Non-volatile memory and integrated memory and peripheral circuitry fabrication processes are provided. Sets of charge storage regions, such as NAND strings including multiple non-volatile storage elements, are formed over a semiconductor substrate using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates for the charge storage regions and the gate regions of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions of these devices can be formed from the layer forming the control gates of the memory array.
摘要翻译：提供非易失性存储器和集成存储器和外围电路制造工艺。使用诸如第一多晶硅层的电荷存储材料层在半导体衬底上形成诸如包括多个非易失性存储元件的NAND串的电荷存储区的集合。中间电介质层设置在电荷存储区域的上方。将诸如第二多晶硅层的导电材料层沉积在衬底上并被蚀刻以形成用于存储元件组的选择晶体管的电荷存储区域和栅极区域的控制栅极。从衬底的一部分去除第一层多晶硅，便于仅从第二层多晶硅制造选择晶体管栅极区。外围电路形成也被并入到制造过程中以形成诸如高电压和逻辑晶体管的器件的栅极区域。这些器件的栅极区域可以由形成存储器阵列的控制栅极的层形成。

9. 发明授权

US07365018B2 Fabrication of semiconductor device for flash memory with increased select gate width 有权
标题翻译：具有增加选择栅极宽度的闪存半导体器件制造
公开(公告)号：US07365018B2
公开(公告)日：2008-04-29
申请号：US11319895
申请日：2005-12-28
申请人： Masaaki Higashitani , Tuan Pham , Masayuki Ichige , Koji Hashimoto , Satoshi Tanaka , Kikuko Sugimae
发明人： Masaaki Higashitani , Tuan Pham , Masayuki Ichige , Koji Hashimoto , Satoshi Tanaka , Kikuko Sugimae
IPC分类号： H01L21/302
CPC分类号： H01L21/28123 , H01L21/32139 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A non-volatile memory device having memory elements with a channel length of, e.g., 45-55 nm or less, is fabricated using existing lithographic techniques. In one approach, patterns of first and second photomasks are transferred to the same photoresist layer. The first photomask can have openings with a given feature size F that are spaced apart by the feature size F, for instance. The second photomask has an opening which is sized to create a desired inter-select gate gap, such as 3 F or 5 F. A third photomask is used to provide protective portions in a second photoresist layer over the select gate structures. The final structure has memory elements of width F spaced apart by a distance F, and select gates of width 3 F spaced apart by 3 F or 5 F. In another approach, the patterns of three photomasks are transferred to respective photoresist layers to create an analogous final structure.
摘要翻译：使用现有的光刻技术制造具有例如45-55nm或更小的通道长度的存储元件的非易失性存储器件。在一种方法中，第一和第二光掩模的图案被转移到相同的光致抗蚀剂层。第一光掩模可以具有例如由特征尺寸F间隔开的具有给定特征尺寸F的开口。第二光掩模具有一个开口，其尺寸被设计成产生期望的选择性间隙，例如3F或5F。第三光掩模用于在选择栅极结构上的第二光致抗蚀剂层中提供保护部分。最终结构具有间隔开距离F的宽度为F的存储元件，并且以3F或5F隔开的宽度3F的选择栅极。另一种方法是将三个光掩模的图案转移到相应的光致抗蚀剂层，以形成类似的最终结构。

10. 发明授权

US07183153B2 Method of manufacturing self aligned non-volatile memory cells 有权
标题翻译：制造自对准非易失性存储单元的方法
公开(公告)号：US07183153B2
公开(公告)日：2007-02-27
申请号：US10799060
申请日：2004-03-12
申请人： Jeffrey W. Lutze , Tuan Pham , Masaaki Higashitani
发明人： Jeffrey W. Lutze , Tuan Pham , Masaaki Higashitani
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11521
摘要： A method of forming an array of non-volatile memory cells includes forming a plurality of floating gate structures and shaping the plurality of floating gate structures to reduce the width of upper parts of floating gate structures. A first process forms floating gates by etching an upper portion of a polysilicon structure with masking elements in place to shape the floating gate. A second process etches recesses and protrusions in a polysilicon structure prior to etching the structure to form individual floating gates.
摘要翻译：形成非易失性存储单元阵列的方法包括形成多个浮置栅极结构并使多个浮动栅极结构成形以减小浮动栅极结构的上部的宽度。第一工艺通过用掩蔽元件蚀刻多晶硅结构的上部来形成浮栅来形成浮栅，以形成浮栅。在蚀刻结构之前，第二工艺蚀刻多晶硅结构中的凹陷和突起以形成单独的浮动栅极。

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