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1. 发明授权

US5193092A Integrated parity-based testing for integrated circuits 失效
标题翻译：集成电路综合基于奇异度的测试
公开(公告)号：US5193092A
公开(公告)日：1993-03-09
申请号：US632281
申请日：1990-12-20
申请人： Mark R. Hartoog , James A. Rowson , Robert D. Shur , Kenneth D. Van Egmond
发明人： Mark R. Hartoog , James A. Rowson , Robert D. Shur , Kenneth D. Van Egmond
IPC分类号： G01R31/3185
CPC分类号： G01R31/3185 , G06F2201/83
摘要： An integrated circuit includes parity chains which serve as test logic. Each parity chain has a series of XOR gates, where one input to each succeeding XOR gate in a chain is tied to the output of the preceding XOR gate. The remaining inputs are tied to nodes of the main logic, thus defining test points. An error at any one of the test points is reflected in the output of the parity chain. The outputs of the parity chains are arranged as parallel inputs to a linear feedback shift register which provides a serial signature which can be analyzed to detect integrated circuit defects.
摘要翻译：集成电路包括用作测试逻辑的奇偶校验链。每个奇偶校验链具有一系列XOR门，其中链中的每个后续XOR门的一个输入被连接到先前XOR门的输出。剩余的输入与主逻辑的节点相连，从而定义测试点。任何一个测试点的错误反映在奇偶校验链的输出中。奇偶校验链的输出被布置为线性反馈移位寄存器的并行输入，其提供可被分析以检测集成电路缺陷的串行签名。

2. 发明授权

US5197015A System and method for setting capacitive constraints on synthesized logic circuits 失效
标题翻译：用于设置合成逻辑电路电容约束的系统和方法
公开(公告)号：US5197015A
公开(公告)日：1993-03-23
申请号：US631600
申请日：1990-12-20
申请人： Mark R. Hartoog , Thomas J. Schaefer , Robert D. Shur
发明人： Mark R. Hartoog , Thomas J. Schaefer , Robert D. Shur
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/505
摘要： In a computer aided design system, capacitative constraints are defined for the nodes of an integrated circuit. A netlist specifies the integrated circuit's components and a set of interconnecting nodes. Also provided are a set of timing constraints for propagation of signals from specified input nodes to specified output nodes, and a set of signal delays associated with the circuit's components. The process begins by assigning a time delay value and a corresponding initial maximum capacitance value to each circuit node, consistent with the specified timing constraints. Next, a routing difficulty value for the entire circuit, equal to a sum of routing difficulty values associated with the circuits's nodes is computed. Each routing difficulty value is a predefined function of the maximum capacitance value for a corresponding node and the number of circuit components coupled to that node. Then, the following steps are repeated until changes in the computed routing difficulty value for the entire circuit meet predefined criteria. Beginning with components coupled to output nodes and progressing toward components adjacent input nodes, the time delay associated with a component's output node is decreased by decreasing its maximum capacitance value and the time delay associated with each of component's input node is increased by a corresponding amount. Then the routing difficulty value is recomputed and the changed time delays are retained only when the change has caused the computed routing difficulty to decrease.
摘要翻译：在计算机辅助设计系统中，为集成电路的节点定义了电容约束。网表指定集成电路的组件和一组互连节点。还提供了用于将信号从指定输入节点传播到指定输出节点的一组时序约束，以及与电路组件相关联的一组信号延迟。该过程开始于将时间延迟值和对应的初始最大电容值分配给每个电路节点，与指定的时序约束一致。接下来，计算整个电路的路由难度值，其等于与电路节点相关联的路由难度值的总和。每个路由难度值是相应节点的最大电容值的预定义函数和耦合到该节点的电路组件的数量。然后，重复以下步骤，直到整个电路的计算出的路由难度值的变化满足预定义的标准。从耦合到输出节点的组件开始并且朝着与输入节点相邻的组件前进，与组件的输出节点相关联的时间延迟通过减小其最大电容值而减小，并且与每个组件的输入节点相关联的时间延迟增加相应的量。然后，重新计算路由难度值，并且只有当该改变导致计算出的路由难度降低时才保留改变的时间延迟。

3. 发明授权

US5295088A Method for predicting capacitance of connection nets on an integrated circuit 失效
标题翻译：用于预测集成电路上连接网电容的方法
公开(公告)号：US5295088A
公开(公告)日：1994-03-15
申请号：US89385
申请日：1993-07-09
申请人： Mark R. Hartoog , Robert D. Shur
发明人： Mark R. Hartoog , Robert D. Shur
IPC分类号： G06F11/34 , G06F17/50 , H01L23/522 , G06F15/60
CPC分类号： H04L41/147 , G06F17/5036 , H01L23/5222 , H01L2924/0002
摘要： A method estimates the interconnect capacitance of a first net in an integrated circuit. The first step of the method includes the generation of a value which indicates how tightly connected to one another are components connected to the first net. The second step of the method includes the prediction of interconnect capacitance of the first net based on the value generated in the first step and a number representing how many components are connected to the first net.
摘要翻译：一种方法估计集成电路中的第一网络的互连电容。该方法的第一步包括产生一个值，该值指示彼此之间的紧密连接是连接到第一网络的组件。该方法的第二步骤包括基于在第一步骤中生成的值来预测第一网络的互连电容，以及表示多少组件连接到第一网络的数量。

4. 再颁专利

USRE35671E Predictive capacitance layout method for integrated circuits 失效
标题翻译：集成电路的预测电容布局方法
公开(公告)号：USRE35671E
公开(公告)日：1997-11-25
申请号：US683618
申请日：1996-07-17
申请人： Mark R. Hartoog
发明人： Mark R. Hartoog
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5022 , G06F17/5072
摘要： A method for designing a circuit layout which includes the steps of supplying a predictive capacitance value for at least one net of a circuit layout, and placing and routing all nets of the circuit layout using at least one predictive capacitance value as a layout design constraint.
摘要翻译：一种用于设计电路布局的方法，包括以下步骤：为电路布局的至少一个网络提供预测电容值，并使用至少一个预测电容值将所有电路布局的网布置和布线作为布局设计约束。

5. 发明授权

US5367469A Predictive capacitance layout method for integrated circuits 失效
标题翻译：集成电路的预测电容布局方法
公开(公告)号：US5367469A
公开(公告)日：1994-11-22
申请号：US627085
申请日：1990-12-13
申请人： Mark R. Hartoog
发明人： Mark R. Hartoog
IPC分类号： G06F17/50 , G06F15/60
CPC分类号： G06F17/5077 , G06F17/5022 , G06F17/5072
摘要： A method for designing a circuit layout which includes the steps of supplying a predictive capacitance value for at least one net of a circuit layout, and placing and routing all nets of the circuit layout using at least one predictive capacitance value as a layout design constraint.
摘要翻译：一种用于设计电路布局的方法，包括以下步骤：为电路布局的至少一个网络提供预测电容值，并使用至少一个预测电容值将所有电路布局的网布置和布线作为布局设计约束。

6. 发明授权

US5856927A Method for automatically routing circuits of very large scale integration (VLSI) 失效
标题翻译：自动布线大规模集成电路（VLSI）的方法
公开(公告)号：US5856927A
公开(公告)日：1999-01-05
申请号：US432236
申请日：1995-05-01
申请人： Jacob Greidinger , Mark R. Hartoog , Ara Markosian , Christine Fawcett , Eugenia Gelfund , Prasad Sakhamuri
发明人： Jacob Greidinger , Mark R. Hartoog , Ara Markosian , Christine Fawcett , Eugenia Gelfund , Prasad Sakhamuri
IPC分类号： H01L21/82 , G06F17/50 , H01L27/02 , G06F15/00 , H01L27/10
CPC分类号： G06F17/5077 , H01L27/0207
摘要： An automated routing tool for routing interconnections between circuit elements, standard cells and/or cell blocks of cell-based designs which incorporates the best features of both currently known gate array routing techniques with currently known cell-based routing techniques. The invention eliminates the disadvantages of permitting the detailed router to adjust the relative positions of the circuit elements, standard cells and/or cell blocks during the detailed routing process. The method employs a topology manager which iteratively compacts the circuit topology while at the same time optimizing the routing of the interconnections among the circuit elements, standard cells and/or cell blocks of the circuit design. The method employs bin-based global routing, which identifies expandable boundaries and which provides input to a compaction routine which expands or contracts the expandable areas in accordance with the result of the global routing process. The detailed routing step is not performed until after the relative positions of the circuit elements, cells and/or cell blocks have been already fixed.
摘要翻译：一种用于在电路元件，基于单元的设计的标准单元和/或单元块之间路由互连的自动布线工具，其包含当前已知的门阵列路由技术与当前已知的基于单元的路由技术的最佳特征。本发明消除了允许详细路由器在详细路由过程期间调整电路元件，标准单元和/或单元块的相对位置的缺点。该方法采用拓扑管理器，其迭代地压缩电路拓扑，同时优化电路设计的电路元件，标准单元和/或单元块之间的互连的路由。该方法采用基于bin的全局路由，其识别可扩展边界，并且向压缩例程提供输入，该压缩例程根据全局路由过程的结果来扩展或收缩可扩展区域。在电路元件，单元和/或单元块的相对位置已经固定之前，才执行详细的路由步骤。

7. 发明授权

US5638291A Method and apparatus for making integrated circuits by inserting buffers into a netlist to control clock skew 失效
标题翻译：通过将缓冲器插入网表来控制时钟偏差来制造集成电路的方法和装置
公开(公告)号：US5638291A
公开(公告)日：1997-06-10
申请号：US324049
申请日：1994-10-14
申请人： Ying-Meng Li , Sunil V. Ashtaputre , Jacob Greidinger , Mark R. Hartoog , Moazzem M. Hossain , Siu-Tong Hui
发明人： Ying-Meng Li , Sunil V. Ashtaputre , Jacob Greidinger , Mark R. Hartoog , Moazzem M. Hossain , Siu-Tong Hui
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5045 , G06F17/5077
摘要： The present invention discloses a method and an apparatus for making digital integrated circuits by considering ramp delay and clock skew as constraints while minimizing the number of inserted buffers and overall wire length connecting components for large clock trees. The invention includes developing a set of circuit specifications including maximum clock skew, minimum driveability, and maximum ramp delay. These specifications are described in a hardware description language on a digital computer system, and a netlist is synthesized from this hardware description. A modified netlist is then formed by analyzing the netlist and inserting buffers into it to satisfy the circuit specifications of skew, driveabilility, and ramp delay. Thereafter, a digital integrated circuit is produced as specified by the modified netlist.
摘要翻译：本发明公开了一种通过考虑斜坡延迟和时钟偏差作为约束来制造数字集成电路的方法和装置，同时最小化用于大时钟树的插入缓冲器数量和总线长度连接部件。本发明包括开发一组电路规范，包括最大时钟偏移，最小可驱动性和最大斜坡延迟。这些规格以数字计算机系统上的硬件描述语言描述，并且从该硬件描述合成网表。然后通过分析网表并在其中插入缓冲区来形成修改的网表，以满足偏斜，驱动能力和斜坡延迟的电路规范。此后，通过修改的网表指定产生数字集成电路。

8. 发明授权

US5521836A Method for determining instance placements in circuit layouts 失效
标题翻译：确定电路布局中实例布局的方法
公开(公告)号：US5521836A
公开(公告)日：1996-05-28
申请号：US355310
申请日：1994-12-12
申请人： Mark R. Hartoog , James A. Rowson
发明人： Mark R. Hartoog , James A. Rowson
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A process for producing placement information for layouts of circuit elements of networks that are initially represented by netlists such that datapaths can be advantageously placed into a regular array. In one preferred embodiment, the method includes steps of encoding datapath information in instance names of a netlist generated by a datapath compiler; using the encoded datapath information for defining partitioned areas that preserve datapaths; and generating circuit layouts from the netlist, which layouts contain floor plans of the datapaths.
摘要翻译：一种生成用于网络电路元件的布局的布置信息的过程，该网络元件最初由网表列出，使得数据路径可以有利地放置在规则阵列中。在一个优选实施例中，该方法包括以下步骤：对由数据路径编译器生成的网表的实例名称中的数据路径信息进行编码; 使用编码的数据路径信息来定义保留数据路径的分区区域; 并从网表生成电路布局，其布局包含数据路径的平面图。

9. 发明授权

US5974245A Method and apparatus for making integrated circuits by inserting buffers into a netlist 失效
标题翻译：通过将缓冲器插入网表来制造集成电路的方法和装置
公开(公告)号：US5974245A
公开(公告)日：1999-10-26
申请号：US866835
申请日：1997-05-30
申请人： Ying-Meng Li , Sunil V. Ashtaputre , Jacob Greidinger , Mark R. Hartoog , Moazzem M. Hossain , Siu-Tong Hui
发明人： Ying-Meng Li , Sunil V. Ashtaputre , Jacob Greidinger , Mark R. Hartoog , Moazzem M. Hossain , Siu-Tong Hui
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5077
摘要： The present invention discloses a method and an apparatus for making digital integrated circuits by considering ramp delay and clock skew as constraints while minimizing the number of inserted buffers and overall wire length connecting components for large clock trees. The invention includes developing a set of circuit specifications including maximum clock skew, minimum driveability, and maximum ramp delay. These specifications are described in a hardware description language on a digital computer system, and a netlist is synthesized from this hardware description. A modified netlist is then formed by analyzing the netlist and inserting buffers into it to satisfy the circuit specifications of skew, driveability, and ramp delay. Thereafter, a digital integrated circuit is produced as specified by the modified netlist.
摘要翻译：本发明公开了一种通过考虑斜坡延迟和时钟偏差作为约束来制造数字集成电路的方法和装置，同时最小化用于大时钟树的插入缓冲器数量和总线长度连接部件。本发明包括开发一组电路规范，包括最大时钟偏移，最小可驱动性和最大斜坡延迟。这些规格以数字计算机系统上的硬件描述语言描述，并且从该硬件描述合成网表。然后通过分析网表并将缓冲器插入其中来形成经修改的网表，以满足歪斜，驾驶性能和斜坡延迟的电路规范。此后，通过修改的网表指定产生数字集成电路。

10. 发明授权

US5313079A Gate array bases with flexible routing 失效
标题翻译：门阵列基座，灵活布线
公开(公告)号：US5313079A
公开(公告)日：1994-05-17
申请号：US953032
申请日：1992-09-25
申请人： Daniel R. Brasen , James D. Shiffer, II , Mark R. Hartoog , Sunil Asktaputre
发明人： Daniel R. Brasen , James D. Shiffer, II , Mark R. Hartoog , Sunil Asktaputre
IPC分类号： H01L27/118 , H01L27/10
CPC分类号： H01L27/11807 , Y10S257/909
摘要： Flexible routing of gate arrays increases routing efficiency, provides for the routing of functional blocks with other gates in the gate array, and provides structures for flexible power routing, particularly of gate arrays having functional blocks. In particular, a gate-array-implemented integrated circuit is designed using a computer by representing in computer memory a gate array base, placing gate array cells on the gate array base in placement rows each having a uniform height and separated by routing channels in which no gate array cells are placed, and routing in the routing channel connections between placement rows according to a netlist, during routing increasing the size of a routing channel if required and decreasing the size of a routing channel if possible by changing the placement of at least one placement row by an amount less than half the height of the placement row. Routing channel size is therefore flexibly adjusted "on-the-fly" during routing, increasing routing efficiency. The adjustment of routing channels in small (5 track) increments is made possible by defining "tall" macros (four transistor rows high) made of "small" (5 track high) transistors.
摘要翻译：门阵列的灵活路由提高了路由效率，为门阵列中的其他门提供了功能块的路由，并提供了灵活的功率路由结构，特别是具有功能块的门阵列。特别地，使用计算机设计的门阵列实现的集成电路通过在计算机存储器中表示门阵列基座，将门阵列单元放置在栅阵列基底上，每个放置行具有均匀的高度，并由路由通道分开，没有门阵列单元被放置，并且根据网表在路由信道中在布置行之间的连接中的路由，在路由期间增加路由信道的大小（如果需要），如果可能的话减小路由信道的大小，至少改变至少的位置一个展示位置行的数量少于展示位置行高度的一半。因此，路由通道的大小可以在路由过程中“即时”灵活调整，从而提高路由效率。通过定义由“小”（5轨高））晶体管制成的“高”宏（四个晶体管行高），可以实现小（5轨）增量的路由通道调整。

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