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1. 发明授权

US07596751B2 Contact sheet based image management 失效
标题翻译：基于联系表的图像管理
公开(公告)号：US07596751B2
公开(公告)日：2009-09-29
申请号：US11112892
申请日：2005-04-22
申请人： James A. Rowson , Eamonn O'Brien-Strain , John C. Schettino, Jr. , Gary E. Herman
发明人： James A. Rowson , Eamonn O'Brien-Strain , John C. Schettino, Jr. , Gary E. Herman
IPC分类号： G06F17/00
CPC分类号： G06F17/30244 , G06F17/241
摘要： Methods, systems and machine-readable instructions for managing images are described. In one aspect, images are segmented into image clusters. A page layout for a contact sheet comprising thumbnail clusters each comprising thumbnails of the images in respective ones of the image clusters is generated. The page layout divides at least a portion of the contact sheet into regions each containing a respective one of the thumbnail clusters and at least one associated user input field. A description of the page layout is stored on a machine-readable medium.
摘要翻译：描述了用于管理图像的方法，系统和机器可读指令。在一个方面，图像被分割成图像簇。生成包括缩略图集合的联系表的页面布局，每个缩略图包括图像簇中相应图像中的图像的缩略图。页面布局将联系表的至少一部分分成各自包含相应的一个缩略图簇和至少一个关联的用户输入字段的区域。页面布局的描述存储在机器可读介质上。

2. 发明授权

US07529370B1 Digital media-playing device and a method of playing digital media therein 有权
标题翻译：数字媒体播放设备及其中播放数字媒体的方法
公开(公告)号：US07529370B1
公开(公告)日：2009-05-05
申请号：US10835891
申请日：2004-04-29
申请人： Kan Zhang , James A. Rowson
发明人： Kan Zhang , James A. Rowson
IPC分类号： G06F21/00
CPC分类号： G06F21/10 , G06Q20/085
摘要： An aspect of the present invention is a digital media-playing device. The digital media-playing device includes a controller and a compensation-enabled component for playing digital media coupled to the controller wherein the compensation-enabled component is non-bypassable.
摘要翻译：本发明的一个方面是一种数字媒体播放装置。数字媒体播放设备包括控制器和用于播放耦合到控制器的数字媒体的补偿使能分量，其中补偿使能分量是不可旁路的。

3. 发明授权

US5490082A Method of graphically designing circuits 失效
标题翻译：图形设计电路的方法
公开(公告)号：US5490082A
公开(公告)日：1996-02-06
申请号：US612282
申请日：1990-11-07
申请人： James A. Rowson
发明人： James A. Rowson
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： The present invention relates to methods for designing circuits using graphical representations of control and data flow paths. Such representations afford a circuit designer an opportunity early in the design phase to view the data flow and control flow of a proposed circuit layout. Further, such representations are relatively easy to automatically scan, analyze and reduce into a set of logical notations suitable for input to known, standard logic synthesizers.
摘要翻译：本发明涉及使用控制和数据流路径的图形表示来设计电路的方法。这样的表示使电路设计者在设计阶段的早期有机会观察所提出的电路布局的数据流和控制流程。此外，这种表示相对容易地自动扫描，分析和减少成适合于输入到已知的标准逻辑合成器的一组逻辑符号。

4. 发明授权

US5187784A Integrated circuit placement method using netlist and predetermined ordering constraints to produce a human readable integrated circuit schematic diagram 失效
标题翻译：集成电路放置方法使用网表和预定的排序约束来生成可读的集成电路原理图
公开(公告)号：US5187784A
公开(公告)日：1993-02-16
申请号：US297353
申请日：1989-01-13
申请人： James A. Rowson
发明人： James A. Rowson
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/509 , G06F2217/06
摘要： A method is disclosed for determining the placement of circuit elements in an integrated circuit where the circuit elements are initially represented by a netlist. The method preferably includes the steps of providing predetermined ordering constraints that indicate the preferred relative locations of the circuit elements that are represented in the netlist, partitioning the circuit elements from the netlist in accordance with a predetermined balancing criterion; determining the value of a cost function associated with the partitioning steps, and selecting a particular partition based upon the value of the cost function.
摘要翻译：公开了一种用于确定电路元件在集成电路中的布置的方法，其中电路元件最初由网表表示。该方法优选地包括以下步骤：提供指示在网表中表示的电路元件的优选相对位置的预定排序限制，根据预定的平衡标准将电路元件与网表划分; 确定与划分步骤相关联的成本函数的值，以及基于成本函数的值来选择特定分区。

5. 发明授权

US08275745B2 Secure incremental updates to hierarchicaly structured information 有权
标题翻译：针对分层结构化信息安全增量更新
公开(公告)号：US08275745B2
公开(公告)日：2012-09-25
申请号：US10860977
申请日：2004-06-04
申请人： Prakash Reddy , James A. Rowson , Eamonn O'Brien-Strain , Robert N. Mayo , Yuhon Xiong
发明人： Prakash Reddy , James A. Rowson , Eamonn O'Brien-Strain , Robert N. Mayo , Yuhon Xiong
IPC分类号： G06F17/30
CPC分类号： H04L63/0428 , G06F21/6218 , G06F2221/2145
摘要： Techniques for performing an incremental update to a set of hierarchically structured information that do not expose the structure and content of the hierarchically structured information to unauthorized parties. The present techniques include encrypting the hierarchically structured information such that an arrangement of nodes and corresponding data of the hierarchically structured information is not exposed and each node includes a corresponding node identifier that is not encrypted and updating the hierarchically structured information by referring to the nodes using the node identifiers.
摘要翻译：用于对未分层结构化信息的结构和内容暴露于未授权方的对一组分层结构化信息执行增量更新的技术。本技术包括对分层结构化信息进行加密，使得不暴露分层结构化信息的节点和对应数据的布置，并且每个节点包括未被加密的相应节点标识符，并通过参考节点来更新分层结构化信息节点标识符。

6. 发明授权

US08255953B1 Arrangement of content within a custom television channel 有权
标题翻译：定制电视频道内容的安排
公开(公告)号：US08255953B1
公开(公告)日：2012-08-28
申请号：US11174260
申请日：2005-06-30
申请人： James A. Rowson , Richard C. Gossweiler, III , Kurt W. MacDonald
发明人： James A. Rowson , Richard C. Gossweiler, III , Kurt W. MacDonald
IPC分类号： G06F3/00
CPC分类号： H04N21/4147 , H04N21/4532 , H04N21/4622 , H04N21/4825
摘要： Techniques for content arrangement with a custom television (TV) channel in a custom TV system for providing a viewer with custom channels of content based on viewer preferences is described. Various examples of channel content ordering criteria upon which arrangement of content selections within a custom TV channel is based are also described. The custom TV system is suitable for execution on a digital video recorder.
摘要翻译：描述了在定制电视系统中使用定制电视（TV）频道进行内容安排的技术，用于基于观众偏好向观众提供定制的内容频道。还描述了定制TV频道内的内容选择的排列所基于的频道内容排序标准的各种示例。定制电视系统适合在数字录像机上执行。

7. 发明授权

US07751627B2 Image dominant line determination and use 有权
标题翻译：图像主导线确定和使用
公开(公告)号：US07751627B2
公开(公告)日：2010-07-06
申请号：US11496808
申请日：2006-07-31
申请人： Simon Widdowson , James A. Rowson , Eamonn O'Brien-Strain , Parkesh Reddy
发明人： Simon Widdowson , James A. Rowson , Eamonn O'Brien-Strain , Parkesh Reddy
IPC分类号： G06K9/62 , G06K9/36
CPC分类号： G06T13/80 , G06K9/3208 , G06K9/4647 , G06T7/75 , G06T7/77
摘要： In a method of evaluating an image for a dominant line, warped mesh information regarding saliency of the image is received. Displacements of components of the warped mesh information are determined relative to corresponding components in un-warped mesh information. Statistical representations of the displacements are utilized to evaluate the image for a dominant line.
摘要翻译：在评估主导图像的方法中，接收到关于图像显着性的扭曲网格信息。相对于未翘曲网状信息中的相应部件确定翘曲网格信息的分量的位移。使用位移的统计表示来评估主导线的图像。

8. 发明授权

US5251159A Circuit simulation interface methods 失效
标题翻译：电路仿真接口方法
公开(公告)号：US5251159A
公开(公告)日：1993-10-05
申请号：US672257
申请日：1991-03-20
申请人： James A. Rowson
发明人： James A. Rowson
IPC分类号： G06F17/50 , G06F19/00 , G06F15/20
CPC分类号： G06F17/5022 , Y10S715/97
摘要： In a process for analyzing simulation results and providing such results in terms that are familiar to the circuit designer, user-defined primitives, or tiles, are used to reduce large quantities of simulation data into meaningful information. Incremental simulation results which are acquired during the simulation are distributed to the appropriate tiles using a specialized data structure that includes reporting simulation results from the simulator using a node index.
摘要翻译：在用于分析仿真结果并以电路设计者熟悉的术语提供这些结果的过程中，用户定义的基元或瓦片被用于将大量的仿真数据减少为有意义的信息。在仿真期间获取的增量仿真结果使用专门的数据结构分布到适当的瓦片，该数据结构包括使用节点索引来报告来自仿真器的仿真结果。

9. 发明授权

US5193092A Integrated parity-based testing for integrated circuits 失效
标题翻译：集成电路综合基于奇异度的测试
公开(公告)号：US5193092A
公开(公告)日：1993-03-09
申请号：US632281
申请日：1990-12-20
申请人： Mark R. Hartoog , James A. Rowson , Robert D. Shur , Kenneth D. Van Egmond
发明人： Mark R. Hartoog , James A. Rowson , Robert D. Shur , Kenneth D. Van Egmond
IPC分类号： G01R31/3185
CPC分类号： G01R31/3185 , G06F2201/83
摘要： An integrated circuit includes parity chains which serve as test logic. Each parity chain has a series of XOR gates, where one input to each succeeding XOR gate in a chain is tied to the output of the preceding XOR gate. The remaining inputs are tied to nodes of the main logic, thus defining test points. An error at any one of the test points is reflected in the output of the parity chain. The outputs of the parity chains are arranged as parallel inputs to a linear feedback shift register which provides a serial signature which can be analyzed to detect integrated circuit defects.
摘要翻译：集成电路包括用作测试逻辑的奇偶校验链。每个奇偶校验链具有一系列XOR门，其中链中的每个后续XOR门的一个输入被连接到先前XOR门的输出。剩余的输入与主逻辑的节点相连，从而定义测试点。任何一个测试点的错误反映在奇偶校验链的输出中。奇偶校验链的输出被布置为线性反馈移位寄存器的并行输入，其提供可被分析以检测集成电路缺陷的串行签名。

10. 发明授权

US4745084A Method of making a customized semiconductor integrated device 失效
标题翻译：制造定制半导体集成器件的方法
公开(公告)号：US4745084A
公开(公告)日：1988-05-17
申请号：US930305
申请日：1986-11-12
申请人： James A. Rowson , Stephen M. Trimberger
发明人： James A. Rowson , Stephen M. Trimberger
IPC分类号： G06F17/50 , H01L21/765 , H01L23/528 , H01L27/118 , H01L21/70
CPC分类号： G06F17/5068 , H01L21/765 , H01L23/528 , H01L27/11807 , H01L2924/0002
摘要： A method of fabricating a plurality of electronic circuits with transistors in schematic form in a customizable semiconductor integrated device, such as a base array, is disclosed. The base array has a plurality of chains of continuously electrically connected transistors, all of the same type, with the drain of a transistor connected to the source of an adjacent transistor. The schematic transistors are grouped by diffusion line tracing to form a plurality of groups. Each group of schematic transistors is assigned to physical transistors in the base array. The cost function associated with each group of physical transistors is calculated. The total cost function is optimized by changing the assignment of one or more groups of the schematic transistors to the physical transistors. The electrical interconnection from one group of physical transistors to another group of physical transistors is routed to form the physical layout of the circuit. Isolation transistors are also provided to isolate physical layouts of the circuit from one another or to provide isolation between groups of physical transistors where isolation is needed. The gate of each isolation transistors is connected to a voltage source thereby isolating the physical layouts of the circuits.
摘要翻译：公开了一种在可定制的半导体集成器件（例如基极阵列）中以示意形式制造具有晶体管的多个电子电路的方法。基极阵列具有多个连续电连接的晶体管链，全部相同类型，晶体管的漏极连接到相邻晶体管的源极。示意性晶体管通过扩散线追踪分组以形成多个组。每组示意性晶体管分配给基极阵列中的物理晶体管。计算与每组物理晶体管相关联的成本函数。通过将一个或多个原理图晶体管组分配给物理晶体管来优化总成本函数。从一组物理晶体管到另一组物理晶体管的电互连被路由以形成电路的物理布局。还提供隔离晶体管以将电路的物理布局彼此隔离或者在需要隔离的物理晶体管组之间提供隔离。每个隔离晶体管的栅极连接到电压源，从而隔离电路的物理布局。

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