专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5193092A Integrated parity-based testing for integrated circuits 失效
标题翻译：集成电路综合基于奇异度的测试
公开(公告)号：US5193092A
公开(公告)日：1993-03-09
申请号：US632281
申请日：1990-12-20
申请人： Mark R. Hartoog , James A. Rowson , Robert D. Shur , Kenneth D. Van Egmond
发明人： Mark R. Hartoog , James A. Rowson , Robert D. Shur , Kenneth D. Van Egmond
IPC分类号： G01R31/3185
CPC分类号： G01R31/3185 , G06F2201/83
摘要： An integrated circuit includes parity chains which serve as test logic. Each parity chain has a series of XOR gates, where one input to each succeeding XOR gate in a chain is tied to the output of the preceding XOR gate. The remaining inputs are tied to nodes of the main logic, thus defining test points. An error at any one of the test points is reflected in the output of the parity chain. The outputs of the parity chains are arranged as parallel inputs to a linear feedback shift register which provides a serial signature which can be analyzed to detect integrated circuit defects.
摘要翻译：集成电路包括用作测试逻辑的奇偶校验链。每个奇偶校验链具有一系列XOR门，其中链中的每个后续XOR门的一个输入被连接到先前XOR门的输出。剩余的输入与主逻辑的节点相连，从而定义测试点。任何一个测试点的错误反映在奇偶校验链的输出中。奇偶校验链的输出被布置为线性反馈移位寄存器的并行输入，其提供可被分析以检测集成电路缺陷的串行签名。

2. 发明授权

US5197015A System and method for setting capacitive constraints on synthesized logic circuits 失效
标题翻译：用于设置合成逻辑电路电容约束的系统和方法
公开(公告)号：US5197015A
公开(公告)日：1993-03-23
申请号：US631600
申请日：1990-12-20
申请人： Mark R. Hartoog , Thomas J. Schaefer , Robert D. Shur
发明人： Mark R. Hartoog , Thomas J. Schaefer , Robert D. Shur
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/505
摘要： In a computer aided design system, capacitative constraints are defined for the nodes of an integrated circuit. A netlist specifies the integrated circuit's components and a set of interconnecting nodes. Also provided are a set of timing constraints for propagation of signals from specified input nodes to specified output nodes, and a set of signal delays associated with the circuit's components. The process begins by assigning a time delay value and a corresponding initial maximum capacitance value to each circuit node, consistent with the specified timing constraints. Next, a routing difficulty value for the entire circuit, equal to a sum of routing difficulty values associated with the circuits's nodes is computed. Each routing difficulty value is a predefined function of the maximum capacitance value for a corresponding node and the number of circuit components coupled to that node. Then, the following steps are repeated until changes in the computed routing difficulty value for the entire circuit meet predefined criteria. Beginning with components coupled to output nodes and progressing toward components adjacent input nodes, the time delay associated with a component's output node is decreased by decreasing its maximum capacitance value and the time delay associated with each of component's input node is increased by a corresponding amount. Then the routing difficulty value is recomputed and the changed time delays are retained only when the change has caused the computed routing difficulty to decrease.
摘要翻译：在计算机辅助设计系统中，为集成电路的节点定义了电容约束。网表指定集成电路的组件和一组互连节点。还提供了用于将信号从指定输入节点传播到指定输出节点的一组时序约束，以及与电路组件相关联的一组信号延迟。该过程开始于将时间延迟值和对应的初始最大电容值分配给每个电路节点，与指定的时序约束一致。接下来，计算整个电路的路由难度值，其等于与电路节点相关联的路由难度值的总和。每个路由难度值是相应节点的最大电容值的预定义函数和耦合到该节点的电路组件的数量。然后，重复以下步骤，直到整个电路的计算出的路由难度值的变化满足预定义的标准。从耦合到输出节点的组件开始并且朝着与输入节点相邻的组件前进，与组件的输出节点相关联的时间延迟通过减小其最大电容值而减小，并且与每个组件的输入节点相关联的时间延迟增加相应的量。然后，重新计算路由难度值，并且只有当该改变导致计算出的路由难度降低时才保留改变的时间延迟。

3. 发明授权

US5295088A Method for predicting capacitance of connection nets on an integrated circuit 失效
标题翻译：用于预测集成电路上连接网电容的方法
公开(公告)号：US5295088A
公开(公告)日：1994-03-15
申请号：US89385
申请日：1993-07-09
申请人： Mark R. Hartoog , Robert D. Shur
发明人： Mark R. Hartoog , Robert D. Shur
IPC分类号： G06F11/34 , G06F17/50 , H01L23/522 , G06F15/60
CPC分类号： H04L41/147 , G06F17/5036 , H01L23/5222 , H01L2924/0002
摘要： A method estimates the interconnect capacitance of a first net in an integrated circuit. The first step of the method includes the generation of a value which indicates how tightly connected to one another are components connected to the first net. The second step of the method includes the prediction of interconnect capacitance of the first net based on the value generated in the first step and a number representing how many components are connected to the first net.
摘要翻译：一种方法估计集成电路中的第一网络的互连电容。该方法的第一步包括产生一个值，该值指示彼此之间的紧密连接是连接到第一网络的组件。该方法的第二步骤包括基于在第一步骤中生成的值来预测第一网络的互连电容，以及表示多少组件连接到第一网络的数量。

4. 发明授权

US5956257A Automated optimization of hierarchical netlists 失效
标题翻译：自动优化分层网表
公开(公告)号：US5956257A
公开(公告)日：1999-09-21
申请号：US40738
申请日：1993-03-31
申请人： Arnold Ginetti , Thomas J. Schaefer , Robert D. Shur , Christopher H. Kingsley
发明人： Arnold Ginetti , Thomas J. Schaefer , Robert D. Shur , Christopher H. Kingsley
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method of automatically optimizing a hierarchical netlist of integrated circuit cells comprising at least one upper-level cell containing a multiplicity of subsidiary cells of lower hierachical level includes receiving data defining said netlist and timing constraints for it, and establishing abstract timing models for all the subsidiary cells. Timing constraints are propagated to at least one selected subsidiary cell and this cell is optimized by means of a flat optimizer to produced an optimized version of the selected subsidiary cell. The optimized version of the selected cell is inserted into the netlist. The timing constraints denote arrival times for signals at inputs of a cell and required times for signals at outputs of a cell and each abstract timing model of a cell comprises timing parameters which enable a delay time between a specified input of a cell to a specified output of a cell to be computed.
摘要翻译：一种自动优化集成电路单元的分级网表的方法，包括至少一个包含较低层级的多个辅助单元的上级单元，包括接收定义所述网表和为其定时约束的数据，以及建立抽象定时模型辅助细胞。定时约束被传播到至少一个所选择的辅助小区，并且该小区通过平坦优化器被优化以产生所选择的辅助小区的优化版本。所选单元格的优化版本插入到网表中。时序约束表示单元输入端的信号的到达时间和单元输出端的信号的所需时间，单元的每个抽象定时模型包括定时参数，这些定时参数使单元格的指定输入与指定输出之间的延迟时间的计算单元格。

5. 发明授权

US5068812A Event-controlled LCC stimulation 失效
标题翻译：事件控制的LCC刺激
公开(公告)号：US5068812A
公开(公告)日：1991-11-26
申请号：US381548
申请日：1989-07-18
申请人： Thomas J. Schaefer , Robert D. Shur
发明人： Thomas J. Schaefer , Robert D. Shur
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method for simulating a levelized logic circuit including an event-controlled feature for marking components to be reevaluated. An evaluation list is formed which lists signals and corresponding components of the logic circuit which are to be reevaluated. A second list is formed of each component and its corresponding output signals. The external input signals are also listed. Each external input signal is tested for change from a previous evaluation and, if so, the corresponding components in the re-evaluation list are marked for reevaluation. Each component, in levelized order, is then tested to determine whether that component is marked for re-evaluation and, if so, that component is re-evaluated and unmarked, and each signal in the component output signal list which has a non-empty re-evaluation list is tested to determine if the value of the signal has changed since the previous evaluation and, if so, all of the components in that signal's reevaluation list are marked for re-evaluation. Evaluation marks are stored as a marking bit in a memory location associated with a component. The components associated with frequently changing input signals are evaluated without setting or testing their evaluation marks. All reevaluation marks are cleared at the beginning of the execution of the simulation.
摘要翻译：一种用于模拟包括用于标记要被重新评估的组件的事件控制特征的均衡逻辑电路的方法。形成了列出要重新评估的逻辑电路的信号和相应部件的评估表。第二个列表由每个组件及其相应的输出信号组成。还列出了外部输入信号。测试每个外部输入信号，以从先前的评估中进行更改，如果是，重新评估列表中的相应组件被标记为重新评估。然后测试每个组件的顺序，以确定该组件是否被标记为重新评估，如果是，该组件被重新评估和未标记，并且组件输出信号列表中的每个信号具有非空测试重新评估列表，以确定自上次评估以来信号的值是否发生变化，如果是，则将信号重新评估列表中的所有组件标记为重新评估。评估标记作为标记位存储在与组件相关联的存储器位置中。与频繁变化的输入信号相关的组件被评估，而不设置或测试其评估标记。所有的重新评估标记在模拟执行开始时被清除。

6. 发明授权

US5402357A System and method for synthesizing logic circuits with timing constraints 失效
标题翻译：用时序约束合成逻辑电路的系统和方法
公开(公告)号：US5402357A
公开(公告)日：1995-03-28
申请号：US801793
申请日：1991-12-02
申请人： Thomas J. Schaefer , Robert D. Shur
发明人： Thomas J. Schaefer , Robert D. Shur
IPC分类号： G06F17/50 , G06F15/60
CPC分类号： G06F17/505 , G06F17/5068
摘要： In a computer aided design system, a netlist specifies the integrated circuit's components and a set of interconnecting nodes. Also provided are a set of timing constraints for propagation of signals from specified input nodes to specified output nodes, and a set of signal delays associated with the circuit's components. The automatic circuit layout synthesis process begins by assigning an initial capacitance value to each node. Next, a routing difficulty value is computed, this value comprises a sum of routing difficulty values associated with each of the nodes in the integrated circuit. Capacitance values for the integrated circuit are then adjusted so as to reduce the computed routing difficulty. Finally, the netlist and adjusted capacitance values are passed to a silicon compiler for automatic placement and routing of a circuit having capacitance values not exceeding the adjusted capacitance values.
摘要翻译：在计算机辅助设计系统中，网表规定了集成电路的组件和一组互连节点。还提供了用于将信号从指定输入节点传播到指定输出节点的一组时序约束，以及与电路组件相关联的一组信号延迟。自动电路布局合成过程通过为每个节点分配初始电容值开始。接下来，计算路由难度值，该值包括与集成电路中的每个节点相关联的路由难度值的总和。然后调整集成电路的电容值，以减少计算出的路由难度。最后，将网表和调整后的电容值传递给硅编译器，用于自动放置和布线电容值不超过调整后的电容值的电路。

7. 发明授权

US5062067A Levelized logic simulator with fenced evaluation 失效
标题翻译：具有栅栏评估的等级化逻辑模拟器
公开(公告)号：US5062067A
公开(公告)日：1991-10-29
申请号：US324283
申请日：1989-03-15
申请人： Thomas J. Schaefer , Robert D. Shur
发明人： Thomas J. Schaefer , Robert D. Shur
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A simulator for a levelized logic circuit reduces the number of evaluations required. The simulator associates certain lists of signals, called fences, with each component of a logic circuit. A fence is evaluated to determine whether it is active or inactive. Active fences contain signals which have charged since a previous evaluation. Components for active fences are then evaluated by the simulator. Fences are formed by starting with a seed set of signals. If all of the input signals to a component are in one or more fences, a final fence for a component is formed which is the union of the one or more fences. Only signals which can cause an output change on a component are included in fences.
摘要翻译：用于平坦化逻辑电路的模拟器减少了所需的评估次数。模拟器将某些称为栅栏的信号列表与逻辑电路的每个组件相关联。评估围栏以确定其是活动还是非活动。活动围栏包含自从以前的评估已经收费的信号。然后由模拟器评估活动栅栏的组件。栅栏通过从种子信号组开始形成。如果组件的所有输入信号都在一个或多个栅栏中，则形成一个组件的最终围栏，该组件是一个或多个栅栏的联合。只有可能导致组件输出变化的信号才包含在围栏中。

8. 发明授权

US5787010A Enhanced dynamic programming method for technology mapping of combinational logic circuits 失效
标题翻译：用于组合逻辑电路技术映射的增强型动态编程方法
公开(公告)号：US5787010A
公开(公告)日：1998-07-28
申请号：US870860
申请日：1997-06-06
申请人： Thomas J. Schaefer , Robert D. Shur
发明人： Thomas J. Schaefer , Robert D. Shur
IPC分类号： G06F17/50 , G06F15/00
CPC分类号： G06F17/505
摘要： A circuit optimization method in which a set of cost functions are stored for each node that indicate the cost of getting signals to that node and the cost of a gate at that node. By "cost", is meant some figure of merit, such as: the maximal delay for a signal to arrive at a node G; or the area of the elements needed to produce the signal at node G. These cost functions enable the circuit to be optimized without the need for a pattern library and the pattern matching process that is typical of other optimization processes, such as the DAGON Node Tiling Procedure.
摘要翻译：一种电路优化方法，其中为每个节点存储一组成本函数，其指示获取到该节点的信号的成本和该节点处的门的成本。 “成本”是指一些品质因素，例如：信号到达节点G的最大延迟; 或在节点G处产生信号所需的元件的面积。这些成本函数使电路能够被优化，而不需要模式库和典型的其他优化过程的模式匹配过程，例如DAGON节点平铺程序。

9. 发明授权

US5483544A Vector-specific testability circuitry 失效
标题翻译：向量特定可测性电路
公开(公告)号：US5483544A
公开(公告)日：1996-01-09
申请号：US652167
申请日：1991-02-05
申请人： Robert D. Shur
发明人： Robert D. Shur
IPC分类号： G01R31/3183 , G11C29/10 , G06F11/00
CPC分类号： G11C29/10 , G01R31/318392
摘要： Vector-specific test circuitry is added to an existing circuit design to enable improved fault test coverage by an existing fault test. Each vector-specific test circuit is designed to produce a single output indicative of whether any faults were detected in a plurality of previously unobservable node states produced in response to an associated test vector.
摘要翻译：矢量特定的测试电路被添加到现有的电路设计中，以通过现有的故障测试来改进故障测试覆盖。每个向量特定的测试电路被设计成产生一个单个输出，指示是否在响应于相关联的测试向量产生的多个先前不可观察的节点状态中检测到任何故障。

10. 发明授权

US5402356A Buffer circuit design using back track searching of site trees 失效
标题翻译：缓冲电路设计采用路径搜索现场树
公开(公告)号：US5402356A
公开(公告)日：1995-03-28
申请号：US862895
申请日：1992-04-02
申请人： Thomas J. Schaefer , Robert D. Shur
发明人： Thomas J. Schaefer , Robert D. Shur
IPC分类号： G06F17/50 , G06F15/60
CPC分类号： G06F17/505
摘要： A buffer circuit for fanning out a source signal to a plurality of terminals of specified polarities in accordance with specified time constraints is designed by an automated method in which a circuit template is specified in terms of a tree structure. The terminals are ordered in increasing order of required arrival times of the source signal at each of the terminals. A first terminal in a resulting order is assigned to a highest-level potential terminal site of a same polarity as said first terminal, and buffers on a signal path between said first terminal and the source signal are sized so as to satisfy, if possible, a required arrival time of the source signal at said first terminal. So long as required times of arrival are met, additional terminals are placed in like manner. The method proceeds as far as possible using a straight forward assignment procedure of terminals to potential terminal sites, then backtracks, undoing so much of the previous assignments as necessary and making incremental adjustments to allow the method to proceed further if possible. The method is completed when either all terminals have been successfully assigned or all of the previous assignments have been undone.
摘要翻译：根据规定的时间约束将源信号扇出到具有特定极性的多个端子的缓冲电路是通过自动方法设计的，其中根据树结构指定电路模板。终端以每个终端的源信号的所需到达时间的增加顺序排列。所得到的顺序中的第一个终端被分配给与所述第一终端具有相同极性的最高级别的潜在终端站点，并且在所述第一终端和源信号之间的信号路径上的缓冲器的大小被设定为满足如果可能的话，源信号在所述第一终端的所需到达时间。只要满足所需的到达时间，额外的终端将以相同的方式放置。该方法尽可能地使用终端到潜在终端站点的直接分配过程，然后回溯，根据需要撤消先前分配的大量，并进行增量调整以允许该方法进一步如果可能的话。当所有终端已成功分配或所有先前的分配已被撤销时，该方法完成。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式