专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5856927A Method for automatically routing circuits of very large scale integration (VLSI) 失效
标题翻译：自动布线大规模集成电路（VLSI）的方法
公开(公告)号：US5856927A
公开(公告)日：1999-01-05
申请号：US432236
申请日：1995-05-01
申请人： Jacob Greidinger , Mark R. Hartoog , Ara Markosian , Christine Fawcett , Eugenia Gelfund , Prasad Sakhamuri
发明人： Jacob Greidinger , Mark R. Hartoog , Ara Markosian , Christine Fawcett , Eugenia Gelfund , Prasad Sakhamuri
IPC分类号： H01L21/82 , G06F17/50 , H01L27/02 , G06F15/00 , H01L27/10
CPC分类号： G06F17/5077 , H01L27/0207
摘要： An automated routing tool for routing interconnections between circuit elements, standard cells and/or cell blocks of cell-based designs which incorporates the best features of both currently known gate array routing techniques with currently known cell-based routing techniques. The invention eliminates the disadvantages of permitting the detailed router to adjust the relative positions of the circuit elements, standard cells and/or cell blocks during the detailed routing process. The method employs a topology manager which iteratively compacts the circuit topology while at the same time optimizing the routing of the interconnections among the circuit elements, standard cells and/or cell blocks of the circuit design. The method employs bin-based global routing, which identifies expandable boundaries and which provides input to a compaction routine which expands or contracts the expandable areas in accordance with the result of the global routing process. The detailed routing step is not performed until after the relative positions of the circuit elements, cells and/or cell blocks have been already fixed.
摘要翻译：一种用于在电路元件，基于单元的设计的标准单元和/或单元块之间路由互连的自动布线工具，其包含当前已知的门阵列路由技术与当前已知的基于单元的路由技术的最佳特征。本发明消除了允许详细路由器在详细路由过程期间调整电路元件，标准单元和/或单元块的相对位置的缺点。该方法采用拓扑管理器，其迭代地压缩电路拓扑，同时优化电路设计的电路元件，标准单元和/或单元块之间的互连的路由。该方法采用基于bin的全局路由，其识别可扩展边界，并且向压缩例程提供输入，该压缩例程根据全局路由过程的结果来扩展或收缩可扩展区域。在电路元件，单元和/或单元块的相对位置已经固定之前，才执行详细的路由步骤。

IPRDB

热门服务

关于我们

友情链接

联系方式