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1. 发明申请

US20060106444A1 Drawn strand filled tubing wire 有权
公开(公告)号：US20060106444A1
公开(公告)日：2006-05-18
申请号：US11203986
申请日：2005-08-15
申请人： Mark Michael , Hans-Juergen Wachter , Robert Myers
发明人： Mark Michael , Hans-Juergen Wachter , Robert Myers
IPC分类号： A61N1/05
CPC分类号： A61N1/056 , A61N1/05 , A61N1/0563 , H01B13/0006 , Y10T29/49117
摘要： A wire for use in medical applications. The wire is formed by forming a bundle from a plurality of metallic strands and positioning the bundle within an outer tube. The tube and strands are then drawn down to a predetermined diameter to form a wire for use in medical devices. The wire may be covered with an insulating material.

2. 发明申请

US20060106443A1 Drawn strand filled tubing wire 有权
标题翻译：拉丝线填充管线
公开(公告)号：US20060106443A1
公开(公告)日：2006-05-18
申请号：US10524387
申请日：2004-09-13
申请人： Mark Michael , Hans-Juergen Wachter , Robert Myers
发明人： Mark Michael , Hans-Juergen Wachter , Robert Myers
IPC分类号： A61N1/05
CPC分类号： A61N1/056 , H01B13/0006
摘要： A wire for use in medical applications. The wire is formed by forming a bundle from a plurality of drawn filled tubing strands and positioning the bundle within an outer tubing. The tubing and strands are then drawn down to a predetermined diameter to form a wire for use in the medical devices. The wire may be covered with an insulating material.
摘要翻译：用于医疗应用的电线。电线通过从多个拉伸填充的管线形成束并且将束定位在外管内而形成。然后将管道和股线拉下至预定直径以形成用于医疗装置的线材。导线可以用绝缘材料覆盖。

3. 发明申请

US20070279064A1 CONTACT RESISTANCE TEST STRUCTURE AND METHODS OF USING SAME 有权
标题翻译：接触电阻测试结构及其使用方法
公开(公告)号：US20070279064A1
公开(公告)日：2007-12-06
申请号：US11421217
申请日：2006-05-31
申请人： Mark Michael , Raymond Stephany
发明人： Mark Michael , Raymond Stephany
IPC分类号： G01R31/327
CPC分类号： G01R31/2884
摘要： The present invention is directed to a contact resistance test structure and methods of using same. In one illustrative embodiment, the method includes forming a test structure comprised of two gate electrode structures, forming a plurality of conductive contacts to a doped region between the two gate electrode structures, forcing a current through the test structure and determining a resistance of at least one of the conductive contacts based upon, in part, the forced current.
摘要翻译：本发明涉及一种接触电阻测试结构及其使用方法。在一个说明性实施例中，该方法包括形成由两个栅极电极结构组成的测试结构，在两个栅电极结构之间的掺杂区域上形成多个导电触点，迫使通过测试结构的电流和至少确定电阻导电触点之一部分地基于强制电流。

4. 发明授权

US07271047B1 Test structure and method for measuring the resistance of line-end vias 失效
标题翻译：用于测量线端通孔电阻的测试结构和方法
公开(公告)号：US07271047B1
公开(公告)日：2007-09-18
申请号：US11327641
申请日：2006-01-06
申请人： Jianhong Zhu , Mark Michael , David Wu
发明人： Jianhong Zhu , Mark Michael , David Wu
IPC分类号： H01L21/8238
CPC分类号： H01L22/34 , H01L22/14
摘要： A test structure and methods of using and making the same are provided. In one aspect, a test structure is provided that includes a first conductor that has a first end and a second conductor that has a second end positioned above the first end. A third conductor is positioned between the first end of the first conductor and the second end of the second conductor. A first electrode is coupled to the first conductor at a first distance from the third conductor and a second electrode coupled to the first conductor at a second distance from the third conductor. A third electrode is coupled to the second conductor at a third distance from the third conductor and a fourth electrode is coupled to the second conductor at a fourth distance from the third conductor. The first through fourth electrodes provide voltage sense taps and the first and second conductors provide current sense taps from which the resistance of the third conductor may be derived.
摘要翻译：提供了测试结构及其使用和制造方法。在一个方面，提供一种测试结构，其包括具有第一端和第二导体的第一导体，第二导体具有位于第一端上方的第二端。第三导体位于第一导体的第一端和第二导体的第二端之间。第一电极以距离第三导体第一距离的第一导体耦合到第一导体，第二电极以距离第三导体第二距离的方式耦合到第一导体。第三电极以距离第三导体第三距离的方式耦合到第二导体，并且第四电极在距离第三导体的第四距离处耦合到第二导体。第一至第四电极提供电压检测抽头，并且第一和第二导体提供电流检测抽头，从该第三导体提供第三导体的电阻。

5. 发明授权

US07598161B2 Method of forming transistor devices with different threshold voltages using halo implant shadowing 有权
标题翻译：使用光晕植入物阴影形成具有不同阈值电压的晶体管器件的方法
公开(公告)号：US07598161B2
公开(公告)日：2009-10-06
申请号：US11861534
申请日：2007-09-26
申请人： Jingrong Zhou , Mark Michael , Donna Michael, legal representative , David Wu , James F. Buller , Akif Sultan
发明人： Jingrong Zhou , Mark Michael , David Wu , James F. Buller , Akif Sultan
IPC分类号： H01L21/425
CPC分类号： H01L21/26513 , H01L21/26586 , H01L21/823807 , H01L29/1083
摘要： The halo implant technique described herein employs a halo implant mask that creates a halo implant shadowing effect during halo dopant bombardment. A first transistor device structure and a second transistor device structure are formed on a wafer such that they are orthogonally oriented to each other. A common halo implant mask is created with features that prevent halo implantation of the diffusion region of the second transistor device structure during halo implantation of the diffusion region of the first transistor device structure, and with features that prevent halo implantation of the diffusion region of the first transistor device structure during halo implantation of the diffusion region of the second transistor device structure. The orthogonal orientation of the transistor device structures and the pattern of the halo implant mask obviates the need to create multiple implant masks to achieve different threshold voltages for the transistor device structures.
摘要翻译：本文描述的光晕植入技术采用在光晕掺杂剂轰击期间产生晕轮植入物阴影效应的光晕注入掩模。第一晶体管器件结构和第二晶体管器件结构形成在晶片上，使得它们彼此正交地取向。创建了常见的光晕注入掩模，其特征在于，在第一晶体管器件结构的扩散区域的晕圈注入期间防止第二晶体管器件结构的扩散区域的光晕注入，并且具有防止第在第二晶体管器件结构的扩散区的晕圈注入期间的第一晶体管器件结构。晶体管器件结构的正交取向和光晕注入掩模的图案消除了创建多个注入掩模以实现晶体管器件结构的不同阈值电压的需要。

6. 发明申请

US20090193369A1 PROCESS FOR DESIGN OF SEMICONDUCTOR CIRCUITS 有权
标题翻译：半导体电路设计工艺
公开(公告)号：US20090193369A1
公开(公告)日：2009-07-30
申请号：US12022860
申请日：2008-01-30
申请人： Darin A. Chan , Yi Zou , Yuansheng Ma , Marilyn Wright , Mark Michael , Donna Michael
发明人： Darin A. Chan , Yi Zou , Yuansheng Ma , Marilyn Wright , Mark Michael , Donna Michael
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/10
摘要： The present invention generates model scenarios of semiconductor chip design and uses interpolation and Monte Carlo, with random number generation inputs, techniques to iteratively assess the models for a more comprehensive and accurate assessment of design space, and evaluation under projected manufacturing conditions. This evaluation information is then incorporated into design rules in order to improve yield.
摘要翻译：本发明生成半导体芯片设计的模型场景，并使用插值和蒙特卡罗随机数生成输入，迭代评估模型，以更全面，准确地评估设计空间，并在预计制造条件下进行评估。然后将该评估信息并入设计规则以提高产量。

7. 发明授权

US06274415B1 Self-aligned Vt implant 有权
标题翻译：自对准Vt植入物
公开(公告)号：US06274415B1
公开(公告)日：2001-08-14
申请号：US09489068
申请日：2000-01-21
申请人： Jon D. Cheek , Mark Michael , Derick J. Wristers , James F. Buller
发明人： Jon D. Cheek , Mark Michael , Derick J. Wristers , James F. Buller
IPC分类号： H01L21337
CPC分类号： H01L29/66583 , H01L29/105 , H01L29/66537 , H01L29/66545
摘要： Integrated circuits with transistors exhibiting improved junction capacitances and various methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a doped region in an active area of a substrate wherein the doped region has a first conductivity type and a first horizontal junction. A first source/drain region of the first conductivity type is formed in the active area with a second horizontal junction. A second source/drain region of the first conductivity type is formed in the active area with a third horizontal junction and a lateral separation from the first source/drain region that defines a channel region. The second and third horizontal junctions are positioned substantially at the first horizontal junction. The portion of the doped region positioned in the channel region is doped with an impurity of a second conductivity type that is opposite to the first conductivity type. Impurity grading across a source/drain-to-body junction is less abrupt, resulting in improved junction capacitance.
摘要翻译：提供具有改善的结电容的晶体管的集成电路及其制造方法。一方面，提供一种制造方法，其包括在衬底的有源区中形成掺杂区域，其中所述掺杂区域具有第一导电类型和第一水平结。第一导电类型的第一源极/漏极区域形成在具有第二水平结的有源区域中。第一导电类型的第二源极/漏极区域在有源区域中形成有第三水平结和与限定沟道区域的第一源极/漏极区域的横向分离。第二和第三水平接头基本位于第一水平接头处。位于沟道区域中的掺杂区域的部分掺杂有与第一导电类型相反的第二导电类型的杂质。通过源极/漏极到体区结的杂质分级不太突然，导致改善的结电容。

8. 发明授权

US07861195B2 Process for design of semiconductor circuits 有权
标题翻译：半导体电路设计工艺
公开(公告)号：US07861195B2
公开(公告)日：2010-12-28
申请号：US12022860
申请日：2008-01-30
申请人： Darin A. Chan , Yi Zou , Yuansheng Ma , Marilyn Wright , Mark Michael , Donna Michael, legal representative
发明人： Darin A. Chan , Yi Zou , Yuansheng Ma , Marilyn Wright , Mark Michael
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/10
摘要： The present invention generates model scenarios of semiconductor chip design and uses interpolation and Monte Carlo, with random number generation inputs, techniques to iteratively assess the models for a more comprehensive and accurate assessment of design space, and evaluation under projected manufacturing conditions. This evaluation information is then incorporated into design rules in order to improve yield.
摘要翻译：本发明生成半导体芯片设计的模型场景，并使用插值和蒙特卡罗随机数生成输入，迭代评估模型，以更全面，准确地评估设计空间，并在预计制造条件下进行评估。然后将该评估信息并入设计规则以提高产量。

9. 发明授权

US07761838B2 Method for fabricating a semiconductor device having an extended stress liner 有权
标题翻译：制造具有延伸应力衬垫的半导体器件的方法
公开(公告)号：US07761838B2
公开(公告)日：2010-07-20
申请号：US11861492
申请日：2007-09-26
申请人： Zhonghai Shi , Mark Michael , Donna Michael, legal representative , David Wu , James F. Buller , Jingrong Zhou , Akif Sultan
发明人： Zhonghai Shi , Mark Michael , David Wu , James F. Buller , Jingrong Zhou , Akif Sultan
IPC分类号： G06F17/50 , H01L21/8238
CPC分类号： H01L21/823807 , H01L29/78 , H01L29/7843
摘要： The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress.
摘要翻译：本文所述的技术和技术涉及自动创建与半导体基晶体管器件一起使用的应力衬垫的光致抗蚀剂掩模。应力衬垫掩模是利用自动设计工具生成的，其利用与晶片上的特征，器件和结构对应的布局数据。产生的应力衬垫掩模（以及使用应力衬垫掩模制造的晶片）限定了延伸超出晶体管区域的边界并进入晶片的应力不敏感区域的应力衬垫覆盖区域。延伸的应力衬垫通过提供额外的压缩/拉伸应力来进一步提高相应晶体管的性能。

10. 发明授权

US07638837B2 Stress enhanced semiconductor device and methods for fabricating same 有权
标题翻译：应力增强半导体器件及其制造方法
公开(公告)号：US07638837B2
公开(公告)日：2009-12-29
申请号：US11861051
申请日：2007-09-25
申请人： Akif Sultan , Mark Michael , Donna Michael, legal representative , David Wu
发明人： Akif Sultan , Mark Michael , David Wu
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/7843
摘要： A stress-enhanced semiconductor device is provided which includes a substrate having an inactive region and an active region, a first-type stress layer overlying at least a portion of the active region, and a second-type stress layer. The active region includes a first lateral edge which defines a first width of the active region, and a second lateral edge which defines a second width of the active region. The second-type stress layer is disposed adjacent the second lateral edge of the active region.
摘要翻译：提供一种应力增强型半导体器件，其包括具有非活性区域和有源区域的衬底，覆盖有源区域的至少一部分的第一类型应力层和第二类型应力层。有源区域包括限定有源区域的第一宽度的第一侧边缘和限定有源区域的第二宽度的第二侧边缘。第二类应力层设置在活动区域的第二侧边缘附近。

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