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1. 发明授权

US07761838B2 Method for fabricating a semiconductor device having an extended stress liner 有权
标题翻译：制造具有延伸应力衬垫的半导体器件的方法
公开(公告)号：US07761838B2
公开(公告)日：2010-07-20
申请号：US11861492
申请日：2007-09-26
申请人： Zhonghai Shi , Mark Michael , Donna Michael, legal representative , David Wu , James F. Buller , Jingrong Zhou , Akif Sultan
发明人： Zhonghai Shi , Mark Michael , David Wu , James F. Buller , Jingrong Zhou , Akif Sultan
IPC分类号： G06F17/50 , H01L21/8238
CPC分类号： H01L21/823807 , H01L29/78 , H01L29/7843
摘要： The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress.
摘要翻译：本文所述的技术和技术涉及自动创建与半导体基晶体管器件一起使用的应力衬垫的光致抗蚀剂掩模。应力衬垫掩模是利用自动设计工具生成的，其利用与晶片上的特征，器件和结构对应的布局数据。产生的应力衬垫掩模（以及使用应力衬垫掩模制造的晶片）限定了延伸超出晶体管区域的边界并进入晶片的应力不敏感区域的应力衬垫覆盖区域。延伸的应力衬垫通过提供额外的压缩/拉伸应力来进一步提高相应晶体管的性能。

2. 发明授权

US07598161B2 Method of forming transistor devices with different threshold voltages using halo implant shadowing 有权
标题翻译：使用光晕植入物阴影形成具有不同阈值电压的晶体管器件的方法
公开(公告)号：US07598161B2
公开(公告)日：2009-10-06
申请号：US11861534
申请日：2007-09-26
申请人： Jingrong Zhou , Mark Michael , Donna Michael, legal representative , David Wu , James F. Buller , Akif Sultan
发明人： Jingrong Zhou , Mark Michael , David Wu , James F. Buller , Akif Sultan
IPC分类号： H01L21/425
CPC分类号： H01L21/26513 , H01L21/26586 , H01L21/823807 , H01L29/1083
摘要： The halo implant technique described herein employs a halo implant mask that creates a halo implant shadowing effect during halo dopant bombardment. A first transistor device structure and a second transistor device structure are formed on a wafer such that they are orthogonally oriented to each other. A common halo implant mask is created with features that prevent halo implantation of the diffusion region of the second transistor device structure during halo implantation of the diffusion region of the first transistor device structure, and with features that prevent halo implantation of the diffusion region of the first transistor device structure during halo implantation of the diffusion region of the second transistor device structure. The orthogonal orientation of the transistor device structures and the pattern of the halo implant mask obviates the need to create multiple implant masks to achieve different threshold voltages for the transistor device structures.
摘要翻译：本文描述的光晕植入技术采用在光晕掺杂剂轰击期间产生晕轮植入物阴影效应的光晕注入掩模。第一晶体管器件结构和第二晶体管器件结构形成在晶片上，使得它们彼此正交地取向。创建了常见的光晕注入掩模，其特征在于，在第一晶体管器件结构的扩散区域的晕圈注入期间防止第二晶体管器件结构的扩散区域的光晕注入，并且具有防止第在第二晶体管器件结构的扩散区的晕圈注入期间的第一晶体管器件结构。晶体管器件结构的正交取向和光晕注入掩模的图案消除了创建多个注入掩模以实现晶体管器件结构的不同阈值电压的需要。

3. 发明申请

US20090090969A1 ELECTRONIC DEVICE AND METHOD OF BIASING 有权
标题翻译：电子设备和偏置方法
公开(公告)号：US20090090969A1
公开(公告)日：2009-04-09
申请号：US11867743
申请日：2007-10-05
申请人： Ruigang Li , Jingrong Zhou , David Donggang Wu , Zhonghai Shi , James F. Buller , Mark W. Michael , Donna Michael , Akif Sultan , Fred Hause
发明人： Ruigang Li , Jingrong Zhou , David Donggang Wu , Zhonghai Shi , James F. Buller , Mark W. Michael , Donna Michael , Akif Sultan , Fred Hause
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/84 , H01L27/1203
摘要： A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.
摘要翻译：第一偏置电荷被提供给电子器件的第一电平处的第一偏置区域，直接位于第一晶体管下方的第一偏置区域具有与第一偏置区域电隔离的第二电平的沟道区域。第一晶体管的电压阈值基于第一偏置电荷。第二偏置电荷被提供给电子器件的第一电平处的第二偏置区域，第二偏置区域直接位于具有与第一偏置区域电隔离的第二电平的沟道区域的第二晶体管的正下方。第二晶体管的电压阈值基于第二偏置电荷。

4. 发明授权

US08687417B2 Electronic device and method of biasing 有权
标题翻译：电子设备和偏置方法
公开(公告)号：US08687417B2
公开(公告)日：2014-04-01
申请号：US11867743
申请日：2007-10-05
申请人： Ruigang Li , Jingrong Zhou , David Donggang Wu , Zhonghai Shi , James F. Buller , Akif Sultan , Fred Hause , Donna Michael
发明人： Ruigang Li , Jingrong Zhou , David Donggang Wu , Zhonghai Shi , James F. Buller , Mark W. Michael , Akif Sultan , Fred Hause
IPC分类号： G11C11/34 , G11C16/04 , G11C16/02 , G11C16/00
CPC分类号： H01L21/84 , H01L27/1203
摘要： A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.
摘要翻译：第一偏置电荷被提供给电子器件的第一电平处的第一偏置区域，直接位于第一晶体管下方的第一偏置区域具有与第一偏置区域电隔离的第二电平的沟道区域。第一晶体管的电压阈值基于第一偏置电荷。第二偏置电荷被提供给电子器件的第一电平处的第二偏置区域，第二偏置区域直接位于具有与第一偏置区域电隔离的第二电平的沟道区域的第二晶体管的正下方。第二晶体管的电压阈值基于第二偏置电荷。

5. 发明授权

US07638837B2 Stress enhanced semiconductor device and methods for fabricating same 有权
标题翻译：应力增强半导体器件及其制造方法
公开(公告)号：US07638837B2
公开(公告)日：2009-12-29
申请号：US11861051
申请日：2007-09-25
申请人： Akif Sultan , Mark Michael , Donna Michael, legal representative , David Wu
发明人： Akif Sultan , Mark Michael , David Wu
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/7843
摘要： A stress-enhanced semiconductor device is provided which includes a substrate having an inactive region and an active region, a first-type stress layer overlying at least a portion of the active region, and a second-type stress layer. The active region includes a first lateral edge which defines a first width of the active region, and a second lateral edge which defines a second width of the active region. The second-type stress layer is disposed adjacent the second lateral edge of the active region.
摘要翻译：提供一种应力增强型半导体器件，其包括具有非活性区域和有源区域的衬底，覆盖有源区域的至少一部分的第一类型应力层和第二类型应力层。有源区域包括限定有源区域的第一宽度的第一侧边缘和限定有源区域的第二宽度的第二侧边缘。第二类应力层设置在活动区域的第二侧边缘附近。

6. 发明授权

US06727136B1 Formation of ultra-shallow depth source/drain extensions for MOS transistors 有权
标题翻译：形成MOS晶体管的超浅深度源极/漏极延伸
公开(公告)号：US06727136B1
公开(公告)日：2004-04-27
申请号：US10273291
申请日：2002-10-18
申请人： James F. Buller , Derick J. Wristers , David Wu , Akif Sultan
发明人： James F. Buller , Derick J. Wristers , David Wu , Akif Sultan
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/823418 , H01L21/823814 , H01L29/1054 , H01L29/7833
摘要： A method of manufacturing a semiconductor device, comprising sequential steps of: (a) providing a semiconductor substrate including a pre-selected thickness strained lattice layer of a first semiconductor material at an upper surface thereof and an underlying layer of a second semiconductor material; and (b) introducing a dopant-containing species of one conductivity type into at least one pre-selected portion of the strained lattice layer of first semiconductor material to form a dopant-containing region therein with a junction at a depth substantially equal to the pre-selected thickness, wherein the second semiconductor material of the underlying layer inhibits diffusion thereinto of the dopant-containing species from the strained lattice layer, thereby controlling/limiting the depth of the junction to substantially the pre-selected thickness of the strained lattice layer.
摘要翻译：一种制造半导体器件的方法，包括以下顺序的步骤：（a）提供半导体衬底，该半导体衬底在其上表面包括预先选定的第一半导体材料的应变晶格层和第二半导体材料的下层; 和（b）将含有一种导电类型的含掺杂剂的物质引入到第一半导体材料的应变晶格层的至少一个预先选择的部分中，以在其中形成含有掺杂剂的区域，其中接合部的深度基本上等于预先 - 选择的厚度，其中下层的第二半导体材料抑制来自应变晶格层的含掺杂剂物质的扩散，从而将结的深度控制/限制到基本上预应变晶格层的预选厚度。

7. 发明授权

US08076703B2 Semiconductor device and methods for fabricating same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08076703B2
公开(公告)日：2011-12-13
申请号：US12603353
申请日：2009-10-21
申请人： Akif Sultan , James F. Buller , Kaveri Mathur
发明人： Akif Sultan , James F. Buller , Kaveri Mathur
IPC分类号： H01L29/78
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/7843
摘要： A semiconductor device is provided which includes a substrate including an inactive region and an active region, a gate electrode structure having portions overlying the active region, a compressive layer overlying the active region, and a tensile layer overlying the inactive region and located outside the active region. The active region has a lateral edge which defines a width of the active region, and a transverse edge which defines a length of the active region. The gate electrode structure includes: a common portion spaced apart from the active region; a plurality of gate electrode finger portions integral with the common portion, and a plurality of fillet portions integral with the common portion and the gate electrode finger portions. A portion of each gate electrode finger portion overlies the active region. The fillet portions are disposed between the common portion and the gate electrode finger portions, and do not overlie the active region. The compressive layer also overlies the gate electrode finger portions, and the tensile layer is disposed adjacent the transverse edge of the active region.
摘要翻译：提供了一种半导体器件，其包括：基板，其包括非活性区域和有源区域;栅极电极结构，其具有覆盖有源区域的部分;覆盖有源区域的压缩层;以及覆盖非活性区域并位于有源区域外部的拉伸层地区。有源区域具有限定有源区域的宽度的横向边缘和限定有源区域的长度的横向边缘。栅电极结构包括：与有源区间隔开的公共部分; 与公共部分成一体的多个栅极电极指部，以及与公共部分和栅电极指部分成一体的多个圆角部分。每个栅电极指部分的一部分覆盖有源区。圆角部分设置在公共部分和栅极电极指部分之间，并且不覆盖有源区域。压电层也覆盖在栅极电极指部分上，并且拉伸层邻近有源区的横向边缘设置。

8. 发明授权

US08377781B2 Transistor with asymmetric silicon germanium source region 有权
标题翻译：晶体管与不对称硅锗源区
公开(公告)号：US08377781B2
公开(公告)日：2013-02-19
申请号：US13230083
申请日：2011-09-12
申请人： Jian Chen , James F. Buller , Akif Sultan
发明人： Jian Chen , James F. Buller , Akif Sultan
IPC分类号： H01L21/336
CPC分类号： H01L29/78618 , H01L29/665 , H01L29/66636 , H01L29/66659 , H01L29/66772 , H01L29/7848
摘要： The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.
摘要翻译：本发明涉及具有不对称硅锗源区的晶体管及其制造方法。在一个说明性实施例中，晶体管包括形成在由硅构成的半导体衬底之上的栅电极，掺杂源区包括在半导体衬底中形成的锗掺杂的外延生长硅的区域和形成在半导体衬底中的掺杂漏极区基质。

9. 发明授权

US07582493B2 Distinguishing between dopant and line width variation components 有权
标题翻译：区分掺杂剂和线宽变化组分
公开(公告)号：US07582493B2
公开(公告)日：2009-09-01
申请号：US11538872
申请日：2006-10-05
申请人： Akif Sultan , James F. Buller , David Donggang Wu
发明人： Akif Sultan , James F. Buller , David Donggang Wu
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , H01L22/14
摘要： A test structure includes first and second pluralities of transistors. The first plurality of transistors includes gate electrodes of a first length. The second plurality of transistors includes gate electrodes of a second length different than the first length. A channel area of the transistors in the first plurality is substantially equal to a channel area of the transistors in the second plurality. A method for using the test structure includes measuring a performance metric of the first and second pluralities of transistors. Variation in the performance metric associated with the first plurality of transistors is compared to variation in the performance metric associated with the second plurality of transistors to identify a random length variation component associated with the first plurality of transistors.
摘要翻译：测试结构包括第一和第二多个晶体管。第一多个晶体管包括第一长度的栅电极。第二多个晶体管包括与第一长度不同的第二长度的栅电极。第一多个晶体管的沟道面积基本上等于第二多个晶体管的沟道面积。使用该测试结构的方法包括测量第一和第二多个晶体管的性能度量。将与第一多个晶体管相关联的性能度量的变化与与第二多个晶体管相关联的性能度量的变化进行比较，以识别与第一多个晶体管相关联的随机长度变化分量。

10. 发明申请

US20120003802A1 TRANSISTOR WITH ASYMMETRIC SILICON GERMANIUM SOURCE REGION 有权
标题翻译：具有不对称硅锗源区的晶体管
公开(公告)号：US20120003802A1
公开(公告)日：2012-01-05
申请号：US13230083
申请日：2011-09-12
申请人： Jian Chen , James F. Buller , Akif Sultan
发明人： Jian Chen , James F. Buller , Akif Sultan
IPC分类号： H01L21/336
CPC分类号： H01L29/78618 , H01L29/665 , H01L29/66636 , H01L29/66659 , H01L29/66772 , H01L29/7848
摘要： The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.
摘要翻译：本发明涉及具有不对称硅锗源区的晶体管及其制造方法。在一个说明性实施例中，晶体管包括形成在由硅构成的半导体衬底之上的栅电极，掺杂源区包括在半导体衬底中形成的锗掺杂的外延生长硅的区域和形成在半导体衬底中的掺杂漏极区基质。

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