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1. 发明授权

US07598161B2 Method of forming transistor devices with different threshold voltages using halo implant shadowing 有权
标题翻译：使用光晕植入物阴影形成具有不同阈值电压的晶体管器件的方法
公开(公告)号：US07598161B2
公开(公告)日：2009-10-06
申请号：US11861534
申请日：2007-09-26
申请人： Jingrong Zhou , Mark Michael , Donna Michael, legal representative , David Wu , James F. Buller , Akif Sultan
发明人： Jingrong Zhou , Mark Michael , David Wu , James F. Buller , Akif Sultan
IPC分类号： H01L21/425
CPC分类号： H01L21/26513 , H01L21/26586 , H01L21/823807 , H01L29/1083
摘要： The halo implant technique described herein employs a halo implant mask that creates a halo implant shadowing effect during halo dopant bombardment. A first transistor device structure and a second transistor device structure are formed on a wafer such that they are orthogonally oriented to each other. A common halo implant mask is created with features that prevent halo implantation of the diffusion region of the second transistor device structure during halo implantation of the diffusion region of the first transistor device structure, and with features that prevent halo implantation of the diffusion region of the first transistor device structure during halo implantation of the diffusion region of the second transistor device structure. The orthogonal orientation of the transistor device structures and the pattern of the halo implant mask obviates the need to create multiple implant masks to achieve different threshold voltages for the transistor device structures.
摘要翻译：本文描述的光晕植入技术采用在光晕掺杂剂轰击期间产生晕轮植入物阴影效应的光晕注入掩模。第一晶体管器件结构和第二晶体管器件结构形成在晶片上，使得它们彼此正交地取向。创建了常见的光晕注入掩模，其特征在于，在第一晶体管器件结构的扩散区域的晕圈注入期间防止第二晶体管器件结构的扩散区域的光晕注入，并且具有防止第在第二晶体管器件结构的扩散区的晕圈注入期间的第一晶体管器件结构。晶体管器件结构的正交取向和光晕注入掩模的图案消除了创建多个注入掩模以实现晶体管器件结构的不同阈值电压的需要。

2. 发明授权

US08134208B2 Semiconductor device having decreased contact resistance 有权
标题翻译：具有降低的接触电阻的半导体器件
公开(公告)号：US08134208B2
公开(公告)日：2012-03-13
申请号：US11861928
申请日：2007-09-26
申请人： Zhonghai Shi , David Wu , Mark Michael , Donna Michael, legal representative
发明人： Zhonghai Shi , David Wu , Mark Michael
IPC分类号： H01L27/12
CPC分类号： H01L29/41733 , H01L21/28518 , H01L21/76897 , H01L23/485 , H01L27/1203 , H01L29/66772 , H01L29/78654 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.
摘要翻译：提供了具有改善的接触电阻的半导体器件和制造这种半导体器件的方法。这些半导体器件包括半导体器件结构和接触。在半导体器件结构的表面部分和侧壁部分处，触点电耦合到半导体器件结构。

3. 发明授权

US08329519B2 Methods for fabricating a semiconductor device having decreased contact resistance 有权
标题翻译：制造具有降低的接触电阻的半导体器件的方法
公开(公告)号：US08329519B2
公开(公告)日：2012-12-11
申请号：US13305449
申请日：2011-11-28
申请人： Zhonghai Shi , David Wu , Mark Michael , Donna Michael, legal representative
发明人： Zhonghai Shi , David Wu , Mark Michael
IPC分类号： H01L27/12
CPC分类号： H01L29/41733 , H01L21/28518 , H01L21/76897 , H01L23/485 , H01L27/1203 , H01L29/66772 , H01L29/78654 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.
摘要翻译：提供了具有改善的接触电阻的半导体器件和制造这种半导体器件的方法。这些半导体器件包括半导体器件结构和接触。在半导体器件结构的表面部分和侧壁部分处，触点电耦合到半导体器件结构。

4. 发明授权

US07861195B2 Process for design of semiconductor circuits 有权
标题翻译：半导体电路设计工艺
公开(公告)号：US07861195B2
公开(公告)日：2010-12-28
申请号：US12022860
申请日：2008-01-30
申请人： Darin A. Chan , Yi Zou , Yuansheng Ma , Marilyn Wright , Mark Michael , Donna Michael, legal representative
发明人： Darin A. Chan , Yi Zou , Yuansheng Ma , Marilyn Wright , Mark Michael
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/10
摘要： The present invention generates model scenarios of semiconductor chip design and uses interpolation and Monte Carlo, with random number generation inputs, techniques to iteratively assess the models for a more comprehensive and accurate assessment of design space, and evaluation under projected manufacturing conditions. This evaluation information is then incorporated into design rules in order to improve yield.
摘要翻译：本发明生成半导体芯片设计的模型场景，并使用插值和蒙特卡罗随机数生成输入，迭代评估模型，以更全面，准确地评估设计空间，并在预计制造条件下进行评估。然后将该评估信息并入设计规则以提高产量。

5. 发明授权

US07761838B2 Method for fabricating a semiconductor device having an extended stress liner 有权
标题翻译：制造具有延伸应力衬垫的半导体器件的方法
公开(公告)号：US07761838B2
公开(公告)日：2010-07-20
申请号：US11861492
申请日：2007-09-26
申请人： Zhonghai Shi , Mark Michael , Donna Michael, legal representative , David Wu , James F. Buller , Jingrong Zhou , Akif Sultan
发明人： Zhonghai Shi , Mark Michael , David Wu , James F. Buller , Jingrong Zhou , Akif Sultan
IPC分类号： G06F17/50 , H01L21/8238
CPC分类号： H01L21/823807 , H01L29/78 , H01L29/7843
摘要： The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress.
摘要翻译：本文所述的技术和技术涉及自动创建与半导体基晶体管器件一起使用的应力衬垫的光致抗蚀剂掩模。应力衬垫掩模是利用自动设计工具生成的，其利用与晶片上的特征，器件和结构对应的布局数据。产生的应力衬垫掩模（以及使用应力衬垫掩模制造的晶片）限定了延伸超出晶体管区域的边界并进入晶片的应力不敏感区域的应力衬垫覆盖区域。延伸的应力衬垫通过提供额外的压缩/拉伸应力来进一步提高相应晶体管的性能。

6. 发明授权

US07638837B2 Stress enhanced semiconductor device and methods for fabricating same 有权
标题翻译：应力增强半导体器件及其制造方法
公开(公告)号：US07638837B2
公开(公告)日：2009-12-29
申请号：US11861051
申请日：2007-09-25
申请人： Akif Sultan , Mark Michael , Donna Michael, legal representative , David Wu
发明人： Akif Sultan , Mark Michael , David Wu
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/7843
摘要： A stress-enhanced semiconductor device is provided which includes a substrate having an inactive region and an active region, a first-type stress layer overlying at least a portion of the active region, and a second-type stress layer. The active region includes a first lateral edge which defines a first width of the active region, and a second lateral edge which defines a second width of the active region. The second-type stress layer is disposed adjacent the second lateral edge of the active region.
摘要翻译：提供一种应力增强型半导体器件，其包括具有非活性区域和有源区域的衬底，覆盖有源区域的至少一部分的第一类型应力层和第二类型应力层。有源区域包括限定有源区域的第一宽度的第一侧边缘和限定有源区域的第二宽度的第二侧边缘。第二类应力层设置在活动区域的第二侧边缘附近。

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