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1. 发明授权

US6037244A Method of manufacturing a semiconductor device using advanced contact formation 失效
标题翻译：使用高级接触形成制造半导体器件的方法
公开(公告)号：US6037244A
公开(公告)日：2000-03-14
申请号：US821660
申请日：1997-03-19
申请人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz , Frederick N. Hause , Sey-Ping Sun
发明人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz , Frederick N. Hause , Sey-Ping Sun
IPC分类号： H01L21/768 , H01L21/28 , H01L21/31
CPC分类号： H01L21/76895 , H01L21/76807
摘要： A method of forming a semiconductor device by using a pillar to form a contact with an active region of the device. A semiconductor device is formed by forming one or more active regions on a substrate of the semiconductor device and forming a pillar over at least a portion of one of the active regions. An insulating film selective to the pillar is provided over portions of the substrate adjacent the pillar. The pillar is then used to form a conductive contact with the active region over which it is formed. In one embodiment, the pillar is formed from a photoresist, while in other embodiments, the pillar is formed from a conductor material such as a metal. The active region may form a source/drain region or a gate electrode.
摘要翻译：一种通过使用柱形成与器件的有源区的接触形成半导体器件的方法。通过在半导体器件的衬底上形成一个或多个有源区并在一个有源区的至少一部分上形成柱来形成半导体器件。在基板的邻近柱的部分上设置对柱子有选择性的绝缘膜。然后使用该柱与其形成的有源区形成导电接触。在一个实施例中，柱由光致抗蚀剂形成，而在其它实施例中，柱由诸如金属的导体材料形成。有源区可以形成源/漏区或栅电极。

2. 发明授权

US06309936B1 Integrated formation of LDD and non-LDD semiconductor devices 有权
标题翻译： LDD和非LDD半导体器件的集成形成
公开(公告)号：US06309936B1
公开(公告)日：2001-10-30
申请号：US09163965
申请日：1998-09-30
申请人： Mark I. Gardner , Robert Paiz , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Robert Paiz , Thomas E. Spikes, Jr.
IPC分类号： H01L21336
CPC分类号： H01L21/823418 , H01L21/823468
摘要： A method of forming a semiconductor device includes forming a first gate electrode over a substrate and then forming a spacer on at least one sidewall of the first gate electrode. A second gate electrode is formed over the substrate after forming the spacer. A first dopant is implanted into the substrate to form a first heavily doped active region adjacent to the spacer and spaced from the first gate electrode and a second heavily doped active region adjacent to the second gate electrode. The spacer is then removed and a second dopant is implanted into the substrate to form a lightly doped active region adjacent to the first gate electrode. In some instances, gate dielectrics for the first and second gate electrodes are formed using different materials and/or having different thicknesses.
摘要翻译：形成半导体器件的方法包括在衬底上形成第一栅电极，然后在第一栅电极的至少一个侧壁上形成间隔物。在形成间隔物之后，在衬底上形成第二栅电极。将第一掺杂剂注入到衬底中以形成与间隔物相邻的第一重掺杂有源区，并与第一栅极间隔开，并与第二栅电极相邻的第二重掺杂有源区。然后去除间隔物，并将第二掺杂剂注入到衬底中以形成与第一栅电极相邻的轻掺杂有源区。在一些情况下，用于第一和第二栅电极的栅极电介质是使用不同的材料和/或具有不同的厚度来形成的。

3. 发明授权

US5942787A Small gate electrode MOSFET 失效
标题翻译：小栅极电极MOSFET
公开(公告)号：US5942787A
公开(公告)日：1999-08-24
申请号：US751582
申请日：1996-11-18
申请人： Mark I. Gardner , Robert Paiz , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Robert Paiz , Thomas E. Spikes, Jr.
IPC分类号： H01L21/033 , H01L21/28 , H01L21/8234 , H01L21/8232
CPC分类号： H01L21/28132 , H01L21/0337 , H01L21/0338 , H01L21/823437 , Y10S438/926 , Y10S438/947
摘要： A method of lithographically fabricating small line width features in a device in accordance with a desired pattern, the small line width features being smaller than that capable of a lithographic process alone, is disclosed. A first layer of material is provided upon a substrate, the first layer including that in which the small line width features are to be made. A lithographically patterned layer is then provided upon the first layer in accordance with a second pattern defined in conjunction with the desired pattern. The patterned layer includes a second material selected to be compatible with the material of the first layer. A conformal layer is then deposited upon the patterned layer, the conformal layer including a third material selected to be compatible in conjunction with the first material and with the second material. Sidewall spacers are formed in the conformal layer proximate side edges of the patterned layer, the sidewall spacers having a desired line width dimension of the small features to be fabricated. The patterned layer is thereafter selectively removed. The first layer is then directionally etched with a selective etch, using the sidewall spacers to prevent the etching of the first layer in accordance with the desired pattern.
摘要翻译：公开了一种根据期望的图案在装置中光刻地制造小线宽特征的方法，小线宽特征小于仅能够进行光刻工艺的小线宽特征。第一层材料设置在基板上，第一层包括将要制造小线宽特征的第一层。然后根据与期望图案一起限定的第二图案在第一层上提供光刻图案层。图案化层包括选择为与第一层的材料相容的第二材料。然后将保形层沉积在图案化层上，保形层包括选择为与第一材料和第二材料相结合的第三材料。在图案化层的近侧边缘的共形层中形成侧壁间隔物，侧壁间隔物具有要制造的小特征的期望的线宽度尺寸。此后，图案化层被选择性地去除。然后用选择性蚀刻对第一层进行定向蚀刻，使用侧壁间隔物来防止根据所需图案蚀刻第一层。

4. 发明授权

US5946581A Method of manufacturing a semiconductor device by doping an active region after formation of a relatively thick oxide layer 失效
标题翻译：在形成相对厚的氧化物层之后通过掺杂有源区制造半导体器件的方法
公开(公告)号：US5946581A
公开(公告)日：1999-08-31
申请号：US780644
申请日：1997-01-08
申请人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz
发明人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz
IPC分类号： H01L21/336 , H01L21/768
CPC分类号： H01L29/6659 , H01L21/76814
摘要： In a semiconductor device fabrication process, an active region of the semiconductor device is formed by doping an active region after formation of a relatively thick oxide layer. According to the process, a gate electrode is formed on a substrate and a relatively thick oxide layer is formed over the gate electrode. Portions of the relatively thick oxide layer are removed to expose a region of the substrate adjacent the gate electrode. The exposed region is then doped with a dopant to form an active region. The active region may form an LDD region. The relatively thick oxide layer may comprise a contact formation layer.
摘要翻译：在半导体器件制造工艺中，半导体器件的有源区通过在形成相对厚的氧化物层之后掺杂有源区而形成。根据该工序，在基板上形成栅电极，在栅电极上形成较厚的氧化层。去除相对厚的氧化物层的部分以露出与栅电极相邻的衬底的区域。然后用暴露的区域掺杂掺杂剂以形成有源区。有源区域可以形成LDD区域。相对厚的氧化物层可以包括接触形成层。

5. 发明授权

US06194283B1 High density trench fill due to new spacer fill method including isotropically etching silicon nitride spacers 失效
标题翻译：由于新的间隔填充方法包括各向异性蚀刻氮化硅间隔物，高密度沟槽填充
公开(公告)号：US06194283B1
公开(公告)日：2001-02-27
申请号：US08959587
申请日：1997-10-29
申请人： Mark I. Gardner , Robert Paiz , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Robert Paiz , Thomas E. Spikes, Jr.
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method for forming an isolation trench in a semiconductor substrate that is substantially free of voids. The method includes forming a dielectric masking layer above a semiconductor substrate. An opening is preferably formed through the masking layer and partially into the semiconductor substrate forming a shallow trench within the semiconductor substrate. Optionally, thermal oxidation of the trench may be performed to form an oxide layer within the trench. A spacer layer is preferably deposited across the exposed surface of the topography. The spacer layer is preferably etched to form spacers directly adjacent to opposed sidewall surfaces of the trench. The isolation trench may then be filled with an isolation dielectric. The presence of the spacers within the isolation trench preferably causes the lower portions of the trench to fill up faster than the upper portions. In this manner the trench may be filled without the formation of voids.
摘要翻译：一种在半导体衬底中形成基本上没有空隙的隔离沟槽的方法。该方法包括在半导体衬底上形成电介质掩模层。优选地，通过掩模层形成开口，并且部分地形成在半导体衬底内形成浅沟槽的半导体衬底中。可选地，可以进行沟槽的热氧化以在沟槽内形成氧化物层。间隔层优选沉积在地形的暴露表面上。优选蚀刻间隔层以形成与沟槽的相对侧壁表面直接相邻的间隔物。然后可以用隔离电介质填充隔离沟槽。间隔物在隔离沟槽内的存在优选地使得沟槽的下部比上部更快地填充。以这种方式，可以填充沟槽而不形成空隙。

6. 发明授权

US5929496A Method and structure for channel length reduction in insulated gate field effect transistors 失效
标题翻译：绝缘栅场效应晶体管的沟道长度减小的方法和结构
公开(公告)号：US5929496A
公开(公告)日：1999-07-27
申请号：US993767
申请日：1997-12-18
申请人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz
发明人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz
IPC分类号： H01L21/223 , H01L21/265 , H01L21/28 , H01L21/336 , H01L29/423 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/28194 , H01L21/223 , H01L21/26513 , H01L29/42364 , H01L29/6659
摘要： A method and structure are provided for an IGFET which has a highly scalable short conduction channel length. The short channel IGFET functions more rapidly than do longer conduction channel devices. Lightly doped regions provide a graded extension or buffer region to the conduction channel. Thus, the voltage drop is shared by the source/drain and channel, in contrast to an abrupt n+/p junction where the almost the entire voltage drop occurs across the lightly doped (channel) side of the junction. This method and structure preserves the integrity of the IGFET by protecting the gate from "hot electron injection." The method and structure provide an IGFET with increased performance without compromising the IGFET's reliability or longevity.
摘要翻译：提供了一种IGFET的方法和结构，其具有高度可缩放的短导电沟道长度。短通道IGFET的功能比延长的导通通道器件更快。轻掺杂区域为传导通道提供渐变的延伸或缓冲区域。因此，与突然的n + / p结相比，源/漏和沟道的电压降是共同的，其中几乎整个电压降在结点的轻掺杂（沟道）侧上发生。该方法和结构通过保护栅极免受“热电子注入”的影响来保持IGFET的完整性。该方法和结构提供IGFET具有更高的性能，而不会影响IGFET的可靠性或寿命。

7. 发明授权

US06258730B1 Ultra-thin gate oxide formation using an N2O plasma 有权
标题翻译：使用N2O等离子体的超薄栅极氧化物形成
公开(公告)号：US06258730B1
公开(公告)日：2001-07-10
申请号：US09246462
申请日：1999-02-09
申请人： Sey-Ping Sun , Mark I. Gardner , Shengnian Song
发明人： Sey-Ping Sun , Mark I. Gardner , Shengnian Song
IPC分类号： H01L2131
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28211 , H01L21/31662
摘要： A fabrication process for semiconductor devices is disclosed for forming ultra-thin gate oxides, whereby a silicon substrate is subjected to an N2O plasma to form the ultra-thin gate oxide. According to one embodiment, the silicon substrate is heated in a deposition chamber and the N2O plasma is created by applying RF power to a showerhead from which the N2O is dispensed. By reacting an N2O plasma directly with the silicon substrate it is possible to achieve gate oxides with thicknesses less than 20 Å and relative uniformities of less than 1% standard deviation. The oxide growth rate resulting from the presently disclosed N2O plasma treatment is much slower than other known oxide formation techniques. One advantage of the disclosed N2O plasma treatment over thermal oxidation lies in the predictability of oxide growth thickness resulting from reaction with N2O plasma versus the strong variation in oxide formation rates exhibited by thermal oxidation. Following gate oxide formation, a high temperature anneal may be performed, preferably in an RTA apparatus. By combining the N2O plasma treatment with an RTA process, the disclosed method is believed to offer a controllable and reproducible method for fabricating highly uniform, ultra-thin gate oxides, having low trapping state densities.
摘要翻译：公开了用于形成超薄栅极氧化物的半导体器件的制造工艺，由此使硅衬底经受N 2 O等离子体以形成超薄栅极氧化物。根据一个实施例，在沉积室中加热硅衬底，并且通过将RF功率施加到分配N2O的喷头来产生N 2 O等离子体。通过使N2O等离子体直接与硅衬底反应，可以实现厚度小于20的栅极氧化物和小于1％标准偏差的相对均匀性。由本发明的N2O等离子体处理产生的氧化物生长速度比其它已知的氧化物形成技术慢得多。所公开的N2O等离子体处理对热氧化的一个优点在于与N2O等离子体反应产生的氧化物生长厚度与热氧化显示的氧化物形成速率的强烈变化的可预测性。在形成栅极氧化物之后，可以优选在RTA装置中进行高温退火。通过将N2O等离子体处理与RTA工艺结合，所公开的方法被认为是提供具有低陷阱状态密度的制造高度均匀的超薄栅极氧化物的可控和可再现的方法。

8. 发明授权

US6051876A Semiconductor device with a graded passivation layer 失效
标题翻译：具有渐变钝化层的半导体器件
公开(公告)号：US6051876A
公开(公告)日：2000-04-18
申请号：US2651
申请日：1998-01-05
申请人： Mark I. Gardner , Sey Ping Sun , Daniel Kadosh
发明人： Mark I. Gardner , Sey Ping Sun , Daniel Kadosh
IPC分类号： H01L23/31 , H01L23/48
CPC分类号： H01L23/3171 , H01L2924/0002 , H01L2924/13091
摘要： The formation of a graded passivation layer is disclosed. In one embodiment, a method includes four steps. In the first step, at least one transistor on a semiconductor substrate is provided. In the second step, at least one metallization layer is formed over the at least one transistor. In the third step, an oxide layer is deposited over the at least one metallization layer. Finally, in the fourth step, an ion implantation of a predetermined dopant is applied to create a graded passivation film over the at least one metallization layer.
摘要翻译：公开了渐变钝化层的形成。在一个实施例中，一种方法包括四个步骤。在第一步骤中，提供半导体衬底上的至少一个晶体管。在第二步骤中，在至少一个晶体管上形成至少一个金属化层。在第三步骤中，氧化物层沉积在至少一个金属化层上。最后，在第四步骤中，施加预定掺杂剂的离子注入以在至少一个金属化层上产生渐变钝化膜。

9. 发明授权

US06383874B1 In-situ stack for high volume production of isolation regions 有权
标题翻译：原位堆叠用于大批量生产隔离区
公开(公告)号：US06383874B1
公开(公告)日：2002-05-07
申请号：US09800862
申请日：2001-03-07
申请人： Sey-Ping Sun , Mark I. Gardner , Robert W. Anderson
发明人： Sey-Ping Sun , Mark I. Gardner , Robert W. Anderson
IPC分类号： H01L21336
CPC分类号： H01L21/76224
摘要： A device stack for fabrication of an isolation structure and methods of fabricating the same are provided. In one aspect, a method of processing a substrate is provided that includes exposing the substrate to a plasma ambient containing nitrogen and oxygen to form a nitrogen containing interface. An oxide film is formed on the nitrogen containing interface and a silicon rich nitride film is formed on the oxide film. The silicon rich nitride film is exposed to a plasma ambient containing oxygen to convert an upper portion of the silicon rich nitride film to silicon oxynitride. The optical properties of the nitride film are enhanced so that UV lithographic patterning of etch masking is improved.
摘要翻译：提供了用于制造隔离结构的器件堆叠及其制造方法。在一个方面，提供了一种处理衬底的方法，其包括将衬底暴露于含有氮和氧的等离子体环境中以形成含氮界面。在含氮界面上形成氧化膜，在氧化物膜上形成富含氮的氮化物膜。富硅氮化物膜暴露于含有氧的等离子体环境，以将富硅氮化物膜的上部转化为氮氧化硅。氮化膜的光学特性得到增强，从而提高了蚀刻掩模的UV光刻图案。

10. 发明授权

US06259133B1 Method for forming an integrated circuit memory cell and product thereof 有权
标题翻译：用于形成集成电路存储单元的方法及其制造方法
公开(公告)号：US06259133B1
公开(公告)日：2001-07-10
申请号：US09248432
申请日：1999-02-11
申请人： Mark I. Gardner , Sey-Ping Sun
发明人： Mark I. Gardner , Sey-Ping Sun
IPC分类号： H01L218247
CPC分类号： H01L27/11526 , H01L27/0688 , H01L27/115 , H01L27/11541 , H01L27/11551 , H01L29/42324 , H01L29/7883
摘要： A method for fabricating an integrated circuit is presented. In the method, a dielectric layer is formed, and then a conductive layer is formed upon the dielectric layer. A base gate may then be patterned from the conductive layer. An intergate dielectric is preferably formed over and around the base gate. A spacer gate may then be formed such that at least a portion of the spacer gate is elevationally below an upper portion of the base gate. At least a portion of the intergate dielectric layer is preferably interposed between a sidewall surface of the spacer gate and a sidewall surface of the base gate. The final memory cell fabricated in this manner does not need to transfer electrons from a semiconducting substrate during operation.
摘要翻译：提出了一种用于制造集成电路的方法。在该方法中，形成介电层，然后在电介质层上形成导电层。然后可以从导电层图案化基栅。优选地，在基栅上方和周围形成隔间电介质。然后可以形成间隔栅，使得间隔栅的至少一部分在基栅的上部的正上方。隔间电介质层的至少一部分优选插入在间隔栅极的侧壁表面和基栅的侧壁表面之间。以这种方式制造的最终存储单元在操作期间不需要从半导体衬底传输电子。

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