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1. 发明授权

US07247877B2 Integrated carbon nanotube sensors 失效
标题翻译：集成碳纳米管传感器
公开(公告)号：US07247877B2
公开(公告)日：2007-07-24
申请号：US10711083
申请日：2004-08-20
申请人： Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , David P. Vallett
发明人： Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , David P. Vallett
IPC分类号： H01L31/072 , H01L23/48
CPC分类号： H01L29/0665 , B82Y10/00 , G01R31/2884 , H01L27/088 , H01L27/286 , H01L29/0673 , H01L29/78 , H01L51/0048 , H01L51/0512 , Y10S977/761 , Y10S977/762 , Y10S977/765
摘要： A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.
摘要翻译：一种集成电路的方法和结构，包括靠近第一晶体管的第一晶体管和嵌入式碳纳米管场效应晶体管（CNT FET），其中CNT FET的尺寸小于第一晶体管。 CNT FET适于感测来自第一晶体管的信号，其中信号包括温度，电压，电流，电场和磁场信号中的任何一个。此外，CNT FET适于测量集成电路中的应力和应变，其中应力和应变包括机械和热应力和应变中的任何一种。此外，CNT FET适用于检测集成电路内的故障电路。

2. 发明授权

US07089138B1 Canary device for failure analysis 失效
标题翻译：金丝雀装置进行故障分析
公开(公告)号：US07089138B1
公开(公告)日：2006-08-08
申请号：US10906590
申请日：2005-02-25
申请人： Pierre J. Bouchard , Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , James A. Slinkman , David P. Vallett
发明人： Pierre J. Bouchard , Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , James A. Slinkman , David P. Vallett
IPC分类号： G06F11/00
CPC分类号： G01R31/2856 , G01R31/2831 , G01R31/318511 , G01R31/3187
摘要： A diagnostic system and method for testing an integrated circuit during fabrication thereof. The diagnostic system has at least one integrated circuit chip that has an electrical signature associated with it; a sacrificial circuit that is adjacent to the integrated circuit chip and has a known electrical signature associated with it and intentionally mis-designed circuitry; and a comparator adapted to compare the electrical signature of the integrated circuit chip with the known electrical signature of the sacrificial circuit, wherein a match in the electrical signature of the integrated circuit chip with the known electrical signature of the sacrificial circuit indicates that the integrated circuit chip is mis-designed. The diagnostic system further includes a semiconductor wafer that has a plurality of integrated circuit chips and a kerf area separating one integrated circuit chip from another integrated circuit chip. A mis-designed integrated circuit chip has abnormally functioning circuitry.
摘要翻译：一种在其制造期间测试集成电路的诊断系统和方法。诊断系统具有至少一个具有与其相关联的电特征的集成电路芯片; 牺牲电路，其与集成电路芯片相邻并且具有与其相关联的已知电气签名和故意错误设计的电路; 以及比较器，用于将集成电路芯片的电特征与牺牲电路的已知电特征进行比较，其中集成电路芯片的电特征中与牺牲电路的已知电气签名的匹配指示集成电路芯片设计错误。诊断系统还包括具有多个集成电路芯片的半导体晶片和将一个集成电路芯片与另一个集成电路芯片分离的切口区域。错误设计的集成电路芯片具有异常功能的电路。

3. 发明授权

US06307162B1 Integrated circuit wiring 失效
标题翻译：集成电路布线
公开(公告)号：US06307162B1
公开(公告)日：2001-10-23
申请号：US08761515
申请日：1996-12-09
申请人： Mark E. Masters , David P. Vallett
发明人： Mark E. Masters , David P. Vallett
IPC分类号： H01R916
CPC分类号： H01L23/5286 , H01L23/525 , H01L23/528 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated distribution wiring system for a semiconductor substrate having a number of devices. The distribution system includes additional stripes which are arranged parallel to existing rails carrying power or signals to the devices. These stripes being separable from the rails may be used to make engineering changes such as repairs or modifications of the circuits in the devices or characterizing or diagnosing the devices.
摘要翻译：一种用于具有多个器件的半导体衬底的集成分配布线系统。分配系统包括与现有轨道并行布置的附加条带，其承载电力或信号到设备。这些可与轨道分离的条带可用于进行工程变更，例如修理或修改设备中的电路或表征或诊断设备。

4. 发明授权

US07484423B2 Integrated carbon nanotube sensors 失效
标题翻译：集成碳纳米管传感器
公开(公告)号：US07484423B2
公开(公告)日：2009-02-03
申请号：US11696370
申请日：2007-04-04
申请人： Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , David P. Vallett
发明人： Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , David P. Vallett
IPC分类号： G01B7/16 , G01L1/00 , H01L29/06
CPC分类号： H01L29/0665 , B82Y10/00 , G01R31/2884 , H01L27/088 , H01L27/286 , H01L29/0673 , H01L29/78 , H01L51/0048 , H01L51/0512 , Y10S977/761 , Y10S977/762 , Y10S977/765
摘要： A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.
摘要翻译：一种集成电路的方法和结构，包括靠近第一晶体管的第一晶体管和嵌入式碳纳米管场效应晶体管（CNT FET），其中CNT FET的尺寸小于第一晶体管。 CNT FET适于感测来自第一晶体管的信号，其中信号包括温度，电压，电流，电场和磁场信号中的任何一个。此外，CNT FET适于测量集成电路中的应力和应变，其中应力和应变包括机械和热应力和应变中的任何一种。此外，CNT FET适用于检测集成电路内的故障电路。

5. 发明授权

US07005874B2 Utilizing clock shield as defect monitor 有权
标题翻译：利用时钟屏蔽作为缺陷监视器
公开(公告)号：US07005874B2
公开(公告)日：2006-02-28
申请号：US10710222
申请日：2004-06-28
申请人： John M. Cohn , Leah M. P. Pastel , Thomas G. Sopchak , David P. Vallett
发明人： John M. Cohn , Leah M. P. Pastel , Thomas G. Sopchak , David P. Vallett
IPC分类号： G01R31/02
CPC分类号： G01R31/31727 , G01R31/025 , G01R31/30 , G01R31/31725
摘要： Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.
摘要翻译：公开了具有一个或多个时钟信号缓冲器和时钟信号分离器的屏蔽时钟树，时钟信号将时钟信号缓冲器连接到时钟信号分离器。屏蔽与时钟信号接线相邻，接地线将屏蔽接地。屏蔽包括与时钟信号布线相邻并且平行的屏蔽线。本发明提供接地布线中的开关，并且这些开关连接到测试控制器并由其控制。

6. 发明授权

US06452209B2 Semiconductor devices having backside probing capability 失效
标题翻译：具有背面探测能力的半导体器件
公开(公告)号：US06452209B2
公开(公告)日：2002-09-17
申请号：US09771778
申请日：2001-01-29
申请人： David P. Vallett
发明人： David P. Vallett
IPC分类号： H01L2358
CPC分类号： H01L22/32 , G01R31/2884
摘要： Integrated circuits are provided which permit backside probing while being operated. Conductive trenches are fabricated into the surface of semiconductor chip at preselected locations. Access to specific electrically connected nodes of the integrated circuit can be effected through the conductive trenches by backside thinning and milling of the semiconductor chip followed by e-beam probe or mechanical probe usage.
摘要翻译：提供集成电路，其允许在操作时进行背面探测。导电沟槽在预选位置被制成半导体芯片的表面。通过半导体芯片的背面变薄和铣削，然后通过电子束探头或机械探针使用，可以通过导电沟槽实现对集成电路的特定电连接节点的访问。

7. 发明授权

US07088124B2 Utilizing clock shield as defect monitor 失效
公开(公告)号：US07088124B2
公开(公告)日：2006-08-08
申请号：US11280008
申请日：2005-11-16
申请人： John M. Cohn , Leah M. P. Pastel , Thomas G. Sopchak , David P. Vallett
发明人： John M. Cohn , Leah M. P. Pastel , Thomas G. Sopchak , David P. Vallett
IPC分类号： G01R31/02
CPC分类号： G01R31/31727 , G01R31/025 , G01R31/30 , G01R31/31725
摘要： Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.

8. 发明授权

US07078248B2 Method and structure for defect monitoring of semiconductor devices using power bus wiring grids 失效
标题翻译：使用电力总线布线网格的半导体器件缺陷监测的方法和结构
公开(公告)号：US07078248B2
公开(公告)日：2006-07-18
申请号：US10710114
申请日：2004-06-18
申请人： John M. Cohn , Leah Marie P. Pastel , Thomas G. Sopchak , David P. Vallett
发明人： John M. Cohn , Leah Marie P. Pastel , Thomas G. Sopchak , David P. Vallett
IPC分类号： H01L21/66
CPC分类号： G01R31/2884 , G01R31/307 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method for implementing defect inspection of an integrated circuit includes configuring a power bus grid structure on a first metal interconnect level, the power bus grid structure including a first plurality of wire pairs. The first plurality of wire pairs is arranged in a manner such that a first wire in each of the first plurality of wire pairs is electrically coupled to conductive structures beneath the first metal interconnect level, and a second wire in each of the first plurality of wire pairs is initially electrically isolated from the conductive structures beneath the first metal interconnect level. The first wire in each of the first plurality of wire pairs is biased to a known voltage, and a charge contrast inspection is performed between the first wire and the second wire of each of the first plurality of wire pairs.
摘要翻译：用于实现集成电路的缺陷检查的方法包括在第一金属互连级上配置电力总线栅格结构，所述电力总线栅格结构包括第一多个线对。第一组多个线对被布置成使得第一多个线对中的每一个中的第一线电耦合到第一金属互连水平面下方的导电结构，并且在第一多个线中的每一个中的第二线对最初与第一金属互连级别下方的导电结构电隔离。第一多个线对中的每一个中的第一线被偏置到已知电压，并且在第一多个线对中的每一个的第一线和第二线之间执行电荷对比度检查。

9. 发明授权

US07671604B2 Nanoscale fault isolation and measurement system 失效
标题翻译：纳米级故障隔离测量系统
公开(公告)号：US07671604B2
公开(公告)日：2010-03-02
申请号：US12116497
申请日：2008-05-07
申请人： Philip V. Kaszuba , Theodore M. Levin , David P. Vallett
发明人： Philip V. Kaszuba , Theodore M. Levin , David P. Vallett
IPC分类号： H01H31/02 , G01R27/08 , G01R31/02
CPC分类号： G01R1/06705 , G01R1/0466 , G01R31/2844 , G01R31/2886
摘要： Disclosed is a fault isolation and measurement system that provides multiple near-field scanning isolation techniques on a common platform. The system incorporates the use of a specialized holder to supply electrical bias to internal circuit structures located within an area of a device or material. The system further uses a multi-probe assembly. Each probe is mounted to a support structure around a common reference point and is a component of a different measurement or fault isolation tool. The assembly moves such that each probe can obtain measurements from the same fixed location on the device or material. The relative positioning of the support structure and/or the holder can be changed in order to obtain measurements from multiple same fixed locations within the area. Additionally, the system uses a processor for providing layered images associated with each signal and for precisely aligning those images with design data in order to characterize, or isolate fault locations within the device or material.
摘要翻译：公开了一种在公共平台上提供多个近场扫描隔离技术的故障隔离和测量系统。该系统包括使用专门的保持器来为位于设备或材料的区域内的内部电路结构提供电偏压。该系统还使用多探头组件。每个探头安装在围绕公共参考点的支撑结构上，并且是不同测量或故障隔离工具的组件。组件移动使得每个探针可以从设备或材料上的相同固定位置获得测量值。可以改变支撑结构和/或保持器的相对定位，以便从区域内的多个相同的固定位置获得测量值。此外，该系统使用处理器来提供与每个信号相关联的分层图像，并且用于将这些图像与设计数据精确对准，以便表征或隔离设备或材料内的故障位置。

10. 发明授权

US07323278B2 Method of adding fabrication monitors to integrated circuit chips 有权
标题翻译：将制造监控器添加到集成电路芯片的方法
公开(公告)号：US07323278B2
公开(公告)日：2008-01-29
申请号：US11687731
申请日：2007-03-19
申请人： James W. Adkisson , Greg Bazan , John M. Cohn , Matthew S. Grady , Thomas G. Sopchak , David P. Vallett
发明人： James W. Adkisson , Greg Bazan , John M. Cohn , Matthew S. Grady , Thomas G. Sopchak , David P. Vallett
IPC分类号： G03F9/00 , G03C5/00
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.
摘要翻译：一种用于设计的集成电路，方法和系统以及制造集成电路的方法。该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状，集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

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