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    • 10. 发明授权
    • Bipolar transistor with a collector having a protected outer edge portion for reduced based-collector junction capacitance and a method of forming the transistor
    • 具有集电器的双极晶体管具有受保护的外边缘部分,用于降低基极集电极结电容,以及形成晶体管的方法
    • US08546230B2
    • 2013-10-01
    • US13296496
    • 2011-11-15
    • James W. AdkissonDavid L. HarameRobert K. LeidyQizhi Liu
    • James W. AdkissonDavid L. HarameRobert K. LeidyQizhi Liu
    • H01L21/331H01L29/66
    • H01L29/732H01L29/7371
    • Disclosed are embodiments of a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a collector region having a protected upper edge portion for reduced base-collector junction capacitance Cbc. In the embodiments, a collector region is positioned laterally adjacent to a trench isolation region within a substrate. Mask layer(s) cover the trench isolation region and further extend laterally onto the edge portion of the collector region. A first section of an intrinsic base layer is positioned above a center portion of the collector region and a second section of the intrinsic base layer is positioned above the mask layer(s). During processing these mask layer(s) prevent divot formation in the upper corner of the trench isolation region at the isolation region-collector region interface and further limit dopant diffusion from a subsequently formed raised extrinsic base layer into the collector region.
    • 公开了晶体管(例如双极结型晶体管(BJT)或异质结双极晶体管(HBT))的实施例以及形成具有集电极区域的晶体管的方法,该集电极区域具有用于还原的基极 - 集电极结电容Cbc的受保护的上边缘部分。 在实施例中,集电极区域位于衬底内侧向与沟槽隔离区域相邻的位置。 掩模层覆盖沟槽隔离区域并且进一步横向延伸到收集器区域的边缘部分上。 本征基极层的第一部分位于集电极区域的中心部分的上方,并且本征基极层的第二部分位于掩模层之上。 在处理期间,这些掩模层防止在隔离区域 - 集电极区界面处的沟槽隔离区的上角部形成裂缝,并且进一步限制从随后形成的凸起的外在基极层到集电极区域的掺杂剂扩散。