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1. 发明授权

US07247877B2 Integrated carbon nanotube sensors 失效
标题翻译：集成碳纳米管传感器
公开(公告)号：US07247877B2
公开(公告)日：2007-07-24
申请号：US10711083
申请日：2004-08-20
申请人： Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , David P. Vallett
发明人： Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , David P. Vallett
IPC分类号： H01L31/072 , H01L23/48
CPC分类号： H01L29/0665 , B82Y10/00 , G01R31/2884 , H01L27/088 , H01L27/286 , H01L29/0673 , H01L29/78 , H01L51/0048 , H01L51/0512 , Y10S977/761 , Y10S977/762 , Y10S977/765
摘要： A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.
摘要翻译：一种集成电路的方法和结构，包括靠近第一晶体管的第一晶体管和嵌入式碳纳米管场效应晶体管（CNT FET），其中CNT FET的尺寸小于第一晶体管。 CNT FET适于感测来自第一晶体管的信号，其中信号包括温度，电压，电流，电场和磁场信号中的任何一个。此外，CNT FET适于测量集成电路中的应力和应变，其中应力和应变包括机械和热应力和应变中的任何一种。此外，CNT FET适用于检测集成电路内的故障电路。

2. 发明授权

US07089138B1 Canary device for failure analysis 失效
标题翻译：金丝雀装置进行故障分析
公开(公告)号：US07089138B1
公开(公告)日：2006-08-08
申请号：US10906590
申请日：2005-02-25
申请人： Pierre J. Bouchard , Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , James A. Slinkman , David P. Vallett
发明人： Pierre J. Bouchard , Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , James A. Slinkman , David P. Vallett
IPC分类号： G06F11/00
CPC分类号： G01R31/2856 , G01R31/2831 , G01R31/318511 , G01R31/3187
摘要： A diagnostic system and method for testing an integrated circuit during fabrication thereof. The diagnostic system has at least one integrated circuit chip that has an electrical signature associated with it; a sacrificial circuit that is adjacent to the integrated circuit chip and has a known electrical signature associated with it and intentionally mis-designed circuitry; and a comparator adapted to compare the electrical signature of the integrated circuit chip with the known electrical signature of the sacrificial circuit, wherein a match in the electrical signature of the integrated circuit chip with the known electrical signature of the sacrificial circuit indicates that the integrated circuit chip is mis-designed. The diagnostic system further includes a semiconductor wafer that has a plurality of integrated circuit chips and a kerf area separating one integrated circuit chip from another integrated circuit chip. A mis-designed integrated circuit chip has abnormally functioning circuitry.
摘要翻译：一种在其制造期间测试集成电路的诊断系统和方法。诊断系统具有至少一个具有与其相关联的电特征的集成电路芯片; 牺牲电路，其与集成电路芯片相邻并且具有与其相关联的已知电气签名和故意错误设计的电路; 以及比较器，用于将集成电路芯片的电特征与牺牲电路的已知电特征进行比较，其中集成电路芯片的电特征中与牺牲电路的已知电气签名的匹配指示集成电路芯片设计错误。诊断系统还包括具有多个集成电路芯片的半导体晶片和将一个集成电路芯片与另一个集成电路芯片分离的切口区域。错误设计的集成电路芯片具有异常功能的电路。

3. 发明授权

US07484423B2 Integrated carbon nanotube sensors 失效
标题翻译：集成碳纳米管传感器
公开(公告)号：US07484423B2
公开(公告)日：2009-02-03
申请号：US11696370
申请日：2007-04-04
申请人： Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , David P. Vallett
发明人： Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , David P. Vallett
IPC分类号： G01B7/16 , G01L1/00 , H01L29/06
CPC分类号： H01L29/0665 , B82Y10/00 , G01R31/2884 , H01L27/088 , H01L27/286 , H01L29/0673 , H01L29/78 , H01L51/0048 , H01L51/0512 , Y10S977/761 , Y10S977/762 , Y10S977/765
摘要： A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.
摘要翻译：一种集成电路的方法和结构，包括靠近第一晶体管的第一晶体管和嵌入式碳纳米管场效应晶体管（CNT FET），其中CNT FET的尺寸小于第一晶体管。 CNT FET适于感测来自第一晶体管的信号，其中信号包括温度，电压，电流，电场和磁场信号中的任何一个。此外，CNT FET适于测量集成电路中的应力和应变，其中应力和应变包括机械和热应力和应变中的任何一种。此外，CNT FET适用于检测集成电路内的故障电路。

4. 发明授权

US07005874B2 Utilizing clock shield as defect monitor 有权
标题翻译：利用时钟屏蔽作为缺陷监视器
公开(公告)号：US07005874B2
公开(公告)日：2006-02-28
申请号：US10710222
申请日：2004-06-28
申请人： John M. Cohn , Leah M. P. Pastel , Thomas G. Sopchak , David P. Vallett
发明人： John M. Cohn , Leah M. P. Pastel , Thomas G. Sopchak , David P. Vallett
IPC分类号： G01R31/02
CPC分类号： G01R31/31727 , G01R31/025 , G01R31/30 , G01R31/31725
摘要： Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.
摘要翻译：公开了具有一个或多个时钟信号缓冲器和时钟信号分离器的屏蔽时钟树，时钟信号将时钟信号缓冲器连接到时钟信号分离器。屏蔽与时钟信号接线相邻，接地线将屏蔽接地。屏蔽包括与时钟信号布线相邻并且平行的屏蔽线。本发明提供接地布线中的开关，并且这些开关连接到测试控制器并由其控制。

5. 发明授权

US07088124B2 Utilizing clock shield as defect monitor 失效
公开(公告)号：US07088124B2
公开(公告)日：2006-08-08
申请号：US11280008
申请日：2005-11-16
申请人： John M. Cohn , Leah M. P. Pastel , Thomas G. Sopchak , David P. Vallett
发明人： John M. Cohn , Leah M. P. Pastel , Thomas G. Sopchak , David P. Vallett
IPC分类号： G01R31/02
CPC分类号： G01R31/31727 , G01R31/025 , G01R31/30 , G01R31/31725
摘要： Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.

6. 发明授权

US07239167B2 Utilizing clock shield as defect monitor 失效
标题翻译：利用时钟屏蔽作为缺陷监视器
公开(公告)号：US07239167B2
公开(公告)日：2007-07-03
申请号：US11382601
申请日：2006-05-10
申请人： John M. Cohn , Leah M. P. Pastel , Thomas G. Sopchak , David P. Vallett
发明人： John M. Cohn , Leah M. P. Pastel , Thomas G. Sopchak , David P. Vallett
IPC分类号： G01R31/02
CPC分类号： G01R31/31727 , G01R31/025 , G01R31/30 , G01R31/31725
摘要： Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.
摘要翻译：公开了具有一个或多个时钟信号缓冲器和时钟信号分离器的屏蔽时钟树，时钟信号将时钟信号缓冲器连接到时钟信号分离器。屏蔽与时钟信号接线相邻，接地线将屏蔽接地。屏蔽包括与时钟信号布线相邻并且平行的屏蔽线。本发明提供接地布线中的开关，并且这些开关连接到测试控制器并由其控制。

7. 发明授权

US07202689B2 Sensor differentiated fault isolation 失效
标题翻译：传感器差分故障隔离
公开(公告)号：US07202689B2
公开(公告)日：2007-04-10
申请号：US10907787
申请日：2005-04-15
申请人： Kevin L. Condon , Theodore M. Levin , Leah M. P. Pastel , David P. Vallett
发明人： Kevin L. Condon , Theodore M. Levin , Leah M. P. Pastel , David P. Vallett
IPC分类号： G01R31/02
CPC分类号： G01R31/311 , G01R31/302 , G01R31/31728 , G01R31/3187
摘要： Disclosed is an apparatus and method for diagnostically testing circuitry within a device. The apparatus and method incorporate the use of energy (e.g., light, heat, magnetic, electric, etc.) applied directly to any location on the device that can affect the electrical activity within the circuitry being tested in order to produce an indicator of a response. A local sensor (e.g., photonic, magnetic, etc.) is positioned at another location on the device where the sensor can detect the indicator of the response within the circuitry. A correlator is configured with response location correlation software and/or circuit tracing software so that when the indicator is detected, the correlator can determine the exact location of a response causing a device failure and/or trace the connectivity of the circuitry, based upon the location of the energy source and the location of the sensor.
摘要翻译：公开了一种用于诊断测试设备内的电路的装置和方法。该装置和方法包括直接应用于设备上可能影响被测电路内的电活动的任何位置的能量（例如光，热，磁，电等）的使用，以便产生一个响应。本地传感器（例如，光子，磁性等）位于设备上的另一位置处，其中传感器可以检测电路内的响应的指示符。相关器配置有响应位置相关软件和/或电路跟踪软件，使得当检测到指示符时，相关器可基于导致设备故障的确定位置和/或跟踪电路的连通性来确定电路的连接性能源的位置和传感器的位置。

8. 发明授权

US07194706B2 Designing scan chains with specific parameter sensitivities to identify process defects 失效
标题翻译：设计具有特定参数灵敏度的扫描链，以识别过程缺陷
公开(公告)号：US07194706B2
公开(公告)日：2007-03-20
申请号：US10710642
申请日：2004-07-27
申请人： James W. Adkisson , Greg Bazan , John M. Cohn , Matthew S. Grady , Leendert M. Huisman , Mark D. Jaffe , Phillip J. Nigh , Leah M. P. Pastel , Thomas G. Sopchak , David E. Sweenor , David P. Vallett
发明人： James W. Adkisson , Greg Bazan , John M. Cohn , Matthew S. Grady , Leendert M. Huisman , Mark D. Jaffe , Phillip J. Nigh , Leah M. P. Pastel , Thomas G. Sopchak , David E. Sweenor , David P. Vallett
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G01R31/31855 , G01R31/318586 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.
摘要翻译：公开了一种用于设计具有特定参数灵敏度的集成电路芯片中的扫描链的方法，以识别导致测试失败和芯片产量损失的制造工艺缺陷。集成电路芯片中的扫描路径的组成被偏置以允许它们也用作产品过程监视器。该方法增加了分组约束，使得扫描链偏置以在可能的情况下具有共同的锁存单元使用，并且还偏置小区路由以将扫描链路由限制到用于互连的给定受限金属层。该方法组合了对过程变化或完整性敏感的锁存器设计参数列表，并且制定了扫描链设计的计划，该计划确定了扫描链的数量和长度。基于产量和过程完整性的当前状态来制定扫描链设计的模型，其中为芯片上的特定扫描链选择具有主要灵敏度的某些锁存器设计。该模型作为输入参数提供给用于布置扫描链的全局放置和布线程序。然后对芯片上的测试数据进行分析，以确定和分离由特定类型的扫描链的统计学显着失败群体的属性表示的系统产量问题。

9. 发明授权

US06307162B1 Integrated circuit wiring 失效
标题翻译：集成电路布线
公开(公告)号：US06307162B1
公开(公告)日：2001-10-23
申请号：US08761515
申请日：1996-12-09
申请人： Mark E. Masters , David P. Vallett
发明人： Mark E. Masters , David P. Vallett
IPC分类号： H01R916
CPC分类号： H01L23/5286 , H01L23/525 , H01L23/528 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated distribution wiring system for a semiconductor substrate having a number of devices. The distribution system includes additional stripes which are arranged parallel to existing rails carrying power or signals to the devices. These stripes being separable from the rails may be used to make engineering changes such as repairs or modifications of the circuits in the devices or characterizing or diagnosing the devices.
摘要翻译：一种用于具有多个器件的半导体衬底的集成分配布线系统。分配系统包括与现有轨道并行布置的附加条带，其承载电力或信号到设备。这些可与轨道分离的条带可用于进行工程变更，例如修理或修改设备中的电路或表征或诊断设备。

10. 发明授权

US06452209B2 Semiconductor devices having backside probing capability 失效
标题翻译：具有背面探测能力的半导体器件
公开(公告)号：US06452209B2
公开(公告)日：2002-09-17
申请号：US09771778
申请日：2001-01-29
申请人： David P. Vallett
发明人： David P. Vallett
IPC分类号： H01L2358
CPC分类号： H01L22/32 , G01R31/2884
摘要： Integrated circuits are provided which permit backside probing while being operated. Conductive trenches are fabricated into the surface of semiconductor chip at preselected locations. Access to specific electrically connected nodes of the integrated circuit can be effected through the conductive trenches by backside thinning and milling of the semiconductor chip followed by e-beam probe or mechanical probe usage.
摘要翻译：提供集成电路，其允许在操作时进行背面探测。导电沟槽在预选位置被制成半导体芯片的表面。通过半导体芯片的背面变薄和铣削，然后通过电子束探头或机械探针使用，可以通过导电沟槽实现对集成电路的特定电连接节点的访问。

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