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1. 发明授权

US5846708A Optical and electrical methods and apparatus for molecule detection 失效
标题翻译：用于分子检测的光学和电学方法和装置
公开(公告)号：US5846708A
公开(公告)日：1998-12-08
申请号：US872582
申请日：1992-04-23
申请人： Mark A. Hollis , Daniel J. Ehrlich , R. Allen Murphy , Bernard B. Kosicki , Dennis D. Rathman , Richard H. Mathews , Barry E. Burke , Mitch D. Eggers , Michael E. Hogan , Rajender Singh Varma
发明人： Mark A. Hollis , Daniel J. Ehrlich , R. Allen Murphy , Bernard B. Kosicki , Dennis D. Rathman , Richard H. Mathews , Barry E. Burke , Mitch D. Eggers , Michael E. Hogan , Rajender Singh Varma
IPC分类号： G01N21/64 , B01J19/00 , C12M1/00 , C12M1/34 , C12N11/00 , C12N15/09 , C12Q1/02 , C12Q1/68 , C40B40/06 , C40B60/14 , G01N5/02 , G01N21/25 , G01N21/27 , G01N21/78 , G01N22/00 , G01N27/00 , G01N27/02 , G01N27/22 , G01N27/27 , G01N27/327 , G01N29/00 , G01N29/12 , G01N33/483 , G01N33/50 , G01N33/53 , G01N33/543 , G01N33/566 , G01N37/00 , G01N27/26
CPC分类号： G01N33/5438 , B01J19/0046 , B01J19/0093 , B82Y30/00 , C12Q1/6825 , C12Q1/6832 , C12Q1/6837 , C12Q1/6874 , G01N21/253 , G01N21/6454 , G01N27/221 , G01N27/226 , G01N33/54373 , B01J2219/00317 , B01J2219/00511 , B01J2219/00527 , B01J2219/00585 , B01J2219/00596 , B01J2219/00605 , B01J2219/00612 , B01J2219/00617 , B01J2219/00621 , B01J2219/00626 , B01J2219/00637 , B01J2219/00653 , B01J2219/00659 , B01J2219/00689 , B01J2219/00702 , B01J2219/00711 , B01J2219/00713 , B01J2219/00722 , B01J2219/00828 , B01J2219/00853 , C40B40/06 , C40B60/14 , Y10S436/806 , Y10S436/807
摘要： A method and apparatus are disclosed for identifying molecular structures within a sample substance using a monolithic array of test sites formed on a substrate upon which the sample substance is applied. Each test site includes probes formed therein to bond with a predetermined target molecular structure or structures. A signal is applied to the test sites and certain electrical, mechanical and/or optical properties of the test sites are detected to determine which probes have bonded to an associated target molecular structure.
摘要翻译：公开了一种用于使用形成在其上施加样品物质的基底上的测试部位的整体阵列来鉴定样品物质内的分子结构的方法和装置。每个测试部位包括形成在其中的探针，以与预定的靶分子结构结合。将信号施加到测试位点，并检测测试位点的某些电，机械和/或光学性质，以确定哪些探针已经结合到相关的靶分子结构。

2. 发明授权

US5653939A Optical and electrical methods and apparatus for molecule detection 失效
标题翻译：用于分子检测的光学和电学方法和装置
公开(公告)号：US5653939A
公开(公告)日：1997-08-05
申请号：US511649
申请日：1995-08-07
申请人： Mark A. Hollis , Daniel J. Ehrlich , R. Allen Murphy , Bernard B. Kosicki , Dennis D. Rathman , Chang-Lee Chen , Richard H. Mathews , Barry E. Burke , Mitch D. Eggers , Michael E. Hogan , Rajender Singh Varma
发明人： Mark A. Hollis , Daniel J. Ehrlich , R. Allen Murphy , Bernard B. Kosicki , Dennis D. Rathman , Chang-Lee Chen , Richard H. Mathews , Barry E. Burke , Mitch D. Eggers , Michael E. Hogan , Rajender Singh Varma
IPC分类号： G01N21/64 , B01J19/00 , C12M1/00 , C12M1/34 , C12N11/00 , C12N15/09 , C12Q1/02 , C12Q1/68 , C40B40/06 , C40B60/14 , G01N5/02 , G01N21/25 , G01N21/27 , G01N21/78 , G01N22/00 , G01N27/00 , G01N27/02 , G01N27/22 , G01N27/27 , G01N27/327 , G01N29/00 , G01N29/12 , G01N33/483 , G01N33/50 , G01N33/53 , G01N33/543 , G01N33/566 , G01N37/00 , G01N15/06 , C07K1/00
CPC分类号： G01N33/5438 , B01J19/0046 , B01J19/0093 , B82Y30/00 , C12Q1/6825 , C12Q1/6832 , C12Q1/6837 , C12Q1/6874 , G01N21/253 , G01N21/6454 , G01N27/221 , G01N27/226 , G01N33/54373 , B01J2219/00317 , B01J2219/00511 , B01J2219/00527 , B01J2219/00585 , B01J2219/00596 , B01J2219/00605 , B01J2219/00612 , B01J2219/00617 , B01J2219/00621 , B01J2219/00626 , B01J2219/00637 , B01J2219/00653 , B01J2219/00659 , B01J2219/00689 , B01J2219/00702 , B01J2219/00711 , B01J2219/00713 , B01J2219/00722 , B01J2219/00828 , B01J2219/00853 , C40B40/06 , C40B60/14 , Y10S436/806 , Y10S436/807
摘要： A method and apparatus are disclosed for identifying molecular structures within a sample substance using a monolithic array of test sites formed on a substrate upon which the sample substance is applied. Each test site includes probes formed therein to bond with a predetermined target molecular structure or structures. A signal is applied to the test sites and certain electrical, mechanical and/or optical properties of the test sites are detected to determine which probes have bonded to an associated target molecular structure.
摘要翻译：公开了一种用于使用形成在其上施加样品物质的基底上的测试部位的整体阵列来鉴定样品物质内的分子结构的方法和装置。每个测试部位包括形成在其中的探针，以与预定的靶分子结构结合。将信号施加到测试位点，并检测测试位点的某些电，机械和/或光学性质，以确定哪些探针已经结合到相关的靶分子结构。

3. 发明授权

US5834840A Net-shape ceramic processing for electronic devices and packages 失效
标题翻译：电子器件和封装的网状陶瓷加工
公开(公告)号：US5834840A
公开(公告)日：1998-11-10
申请号：US448725
申请日：1995-05-25
申请人： William L. Robbins , John S. Haggerty , Dennis D. Rathman , William D. Goodhue , George B. Kenney , Annamarie Lightfoot , R. Allen Murphy , Wendell E. Rhine , Julia Sigalovsky
发明人： William L. Robbins , John S. Haggerty , Dennis D. Rathman , William D. Goodhue , George B. Kenney , Annamarie Lightfoot , R. Allen Murphy , Wendell E. Rhine , Julia Sigalovsky
IPC分类号： H01L21/48 , H01L23/057 , H01L23/15 , H01L23/66 , H01L23/06 , H01L23/10
CPC分类号： H01L23/66 , H01L21/4807 , H01L21/4857 , H01L23/057 , H01L23/15 , H01L2224/32188 , H01L2224/45124 , H01L2224/45144 , H01L2224/48227 , H01L2224/48472 , H01L24/45 , H01L24/48 , H01L2924/01004 , H01L2924/01012 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/04941 , H01L2924/09701 , H01L2924/12032 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13091 , H01L2924/15153 , H01L2924/1517 , H01L2924/15787 , H01L2924/16195 , H01L2924/19041 , H01L2924/30107 , H01L2924/3025
摘要： An electronic device package is provided, consisting of reaction bonded silicon nitride structural and dielectric components and conductor, resistor, and capacitor elements positioned with the package structural components. The package consists of a ceramic package base characterized by a dielectric constant less than 6, of reaction bonded silicon nitride, or a heat spreader material. An electrical conductor is positioned on, embedded in, or attached to the package base for making electrical contact to an electronic device supported on the base and in preferred embodiments, a resistor is attached to the package base. The invention also provides package sidewalls connected to the package base, preferably of reaction bonded silicon nitride, and at least one electrical conductor extending to an outside surface of the package sidewalls for making electrical contact to an electronic device supported by the package base. The reaction formed electronic device packages of the invention provide the ability to support high device signal frequencies, high device operational temperatures, and high environmental temperatures, due to the characteristics of the package materials. The reaction formed electronic device packages of the invention may be produced with a nitriding process during which the overall package structure exhibits minimal shrinkage. As a result, the reaction formed electronic device packages of the invention may be shaped to finished dimensions before the nitriding process with complicated and tight-tolerance geometries of package structural, conducting, resistive, and capacitive components.
摘要翻译：提供了一种电子器件封装，包括反应结合的氮化硅结构和电介质元件以及与封装结构元件定位的导体，电阻器和电容元件。封装由陶瓷封装基底组成，其特征在于介电常数小于6的反应结合氮化硅或散热器材料。电导体定位在，嵌入或附接到封装基座，用于与支撑在基座上的电子设备进行电接触，并且在优选实施例中，电阻器附接到封装基座。本发明还提供了连接到封装基部，优选反应结合的氮化硅的封装侧壁，以及延伸到封装侧壁的外表面的至少一个电导体，用于与由封装基座支撑的电子器件进行电接触。由于封装材料的特性，本发明的反应形成的电子器件封装提供了支持高器件信号频率，高器件工作温度和高环境温度的能力。本发明的反应形成的电子器件封装可以通过氮化工艺制造，在整个封装结构期间，整个封装结构显示最小的收缩。结果，本发明的反应形成的电子器件封装可以在氮化工艺之前成形为具有封装结构，导电，电阻和电容元件的复杂和紧密公差几何形状的成品尺寸。

4. 发明授权

US5801073A Net-shape ceramic processing for electronic devices and packages 失效
标题翻译：电子器件和封装的网状陶瓷加工
公开(公告)号：US5801073A
公开(公告)日：1998-09-01
申请号：US450692
申请日：1995-05-25
申请人： William L. Robbins , John S. Haggerty , Dennis D. Rathman , William D. Goodhue , George B. Kenney , Annamarie Lightfoot , R. Allen Murphy , Wendell E. Rhine , Julia Sigalovsky
发明人： William L. Robbins , John S. Haggerty , Dennis D. Rathman , William D. Goodhue , George B. Kenney , Annamarie Lightfoot , R. Allen Murphy , Wendell E. Rhine , Julia Sigalovsky
IPC分类号： H01L21/50 , H01L23/057 , H01L23/13 , H01L21/60
CPC分类号： H01L21/50 , H01L23/057 , H01L23/13 , H01L2224/05624 , H01L2224/32188 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/48624 , H01L2224/48724 , H01L24/45 , H01L24/48 , H01L2924/01004 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/04941 , H01L2924/09701 , H01L2924/12032 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/15153 , H01L2924/1517 , H01L2924/16195 , H01L2924/19041 , H01L2924/30107 , H01L2924/3025
摘要： A method of producing electronic device packages is provided, consisting of the steps of shaping a package preform and heating the package preform in a nitrogen-containing atmoshpere to nitride the package preform. The shaped package preform may consist of package base, sidewall, conductor, resistor, or capacitor components. The package base and sidewall components may be formed of silicon powder. The method also accommodates the step of inserting a semiconducting material into the package preform and heating the semiconducting material component along with the package preform. The inserted semiconducting material component may be processed to define active electronic device areas on the component either before or after the step of heating the shaped package preform and inserted semiconducting material component. The package production methods of the invention provide the ability to produce reaction bonded structural and dielectric package components by way of a nitriding process that causes minimal overall shrinkage of the package. As a result, reaction formed electronic device packages of the invention may be shaped to finished dimensions before the nitriding process with complicated and tight-tolerance geometries of package structural, conducting, resistive, and capacitive components. The package production methods of the invention also provide the ability to interleave electronic device and packaging manufacturing sequence steps, resulting in increased manufacturing efficiency, as well as improved performance in the devices and packages produced. Device substrates or partially fabricated devices may be embedded into semi-finished packages, whereby completion of device fabrication coincides with completion of package fabrication. This makes possible the fabrication of active devices and circuits in a fully packaged environment.
摘要翻译：提供了一种制造电子器件封装的方法，其包括以下步骤：将包装预制件成形并在含氮大气中加热包装预制件以氮化包装预制件。成形包装预制件可以由封装基座，侧壁，导体，电阻器或电容器部件组成。封装基部和侧壁部件可以由硅粉末形成。该方法还适应于将半导体材料插入封装预制件中并与封装预制件一起加热半导体材料部件的步骤。可以在加热成形包装预制件和插入的半导体材料部件的步骤之前或之后，处理插入的半导体材料部件以在部件上限定有源电子器件区域。本发明的包装生产方法提供了通过氮化过程产生反应结合的结构和介电包装组分的能力，其导致包装的最小总收缩。结果，本发明的反应形成的电子器件封装可以在氮化处理之前被成形为成品尺寸，其具有封装结构，导电，电阻和电容元件的复杂且严格的公差几何形状。本发明的封装制造方法还提供了交错电子器件和封装制造顺序步骤的能力，从而提高制造效率，以及在所生产的器件和封装中提高性能。器件衬底或部分制造的器件可以嵌入半成品封装中，由此器件制造的完成与封装制造的完成一致。这使得可以在完全封装的环境中制造有源器件和电路。

5. 发明授权

US5032538A Semiconductor embedded layer technology utilizing selective epitaxial growth methods 失效
标题翻译：采用选择性外延生长方法的半导体嵌入层技术
公开(公告)号：US5032538A
公开(公告)日：1991-07-16
申请号：US073912
申请日：1987-07-07
申请人： Carl O. Bozler , Gary D. Alley , William T. Lindley , R. Allen Murphy
发明人： Carl O. Bozler , Gary D. Alley , William T. Lindley , R. Allen Murphy
IPC分类号： H01L21/20 , H01L21/335 , H01L21/74 , H01L23/482 , H01L23/52 , H01L23/535 , H01L29/772 , H01L29/92
CPC分类号： H01L29/66424 , H01L21/743 , H01L23/4824 , H01L23/52 , H01L23/535 , H01L28/40 , H01L29/7722 , H01L2924/0002 , H01L2924/3011 , Y10S148/026 , Y10S148/053 , Y10S148/115 , Y10S148/142 , Y10S148/164
摘要： A permeable base transistor (30) including a metal base layer (34) embedded in a semiconductor crystal (32) to separate collector (38) and emitter (40) regions and form a Schottky barrier with each is disclosed. The metal base layer has at least one opening (37) through which the crystal semiconductor (32) joins the collector (38) and emitter (40) regions. Ohmic contacts (42,44) are made to the emitter (38) and collector (40) regions. The width of all openings (37) in the base layer (34) is of the order of the zero bias depletion width corresponding to the carrier concentration in the opening. The thickness of the metal layer (34) is in the order of 10% of this zero bias depletion width. As a result, a potential barrier in each opening limits current flow over the lower portion of the bias range. With increasing forward base bias the potential in the openings, which is lower than along the metal of the base layer (34), is lowered sufficiently to permit substantial increase in the barrier limited current flow from the collector (38) to emitter (40).A method of fabricating this transistor as well as methods for forming integrated circuit structures are also disclosed. Metal and other layers may be selectively embedded in semiconductor crystal. Embedded metal layers may serve as interconnections between devices. Devices may be in a stacked configuration.
摘要翻译：公开了一种可渗透的基极晶体管（30），其包括嵌入半导体晶体（32）中以分离集电极（38）和发射极（40）区域并形成肖特基势垒的金属基底层（34）。金属基层具有至少一个开口（37），晶体半导体（32）通过该开口连接集电极（38）和发射极（40）区域。欧姆接触（42,44）制成发射极（38）和集电极（40）区域。基底层（34）中的所有开口（37）的宽度为与开口中的载流子浓度相对应的零偏置耗尽宽度的量级。金属层（34）的厚度为该零偏置耗尽宽度的10％量级。结果，每个开口中的势垒限制了偏压范围下部的电流。随着正向基极偏压的增加，开口中比基底层（34）的金属低的电位被充分降低，从而可以显着增加从集电器（38）到发射极（40）的阻挡限制电流，。还公开了一种制造该晶体管的方法以及用于形成集成电路结构的方法。金属等层可以选择性地嵌入在半导体晶体中。嵌入式金属层可用作器件之间的互连。设备可能处于堆叠配置。

6. 发明授权

US07501634B1 Method and system for distribution of an exposure control signal for focal plane arrays 有权
标题翻译：用于焦平面阵列曝光控制信号分配的方法和系统
公开(公告)号：US07501634B1
公开(公告)日：2009-03-10
申请号：US10742285
申请日：2003-12-19
申请人： Robert K. Reich , Bernard Kosicji , Dennis Rathman , Richard Osgood , Michael Rose , R. Allen Murphy , Robert Berger
发明人： Robert K. Reich , Bernard Kosicji , Dennis Rathman , Richard Osgood , Michael Rose , R. Allen Murphy , Robert Berger
IPC分类号： H01L27/146
CPC分类号： H04N5/2353 , H01L27/14609 , H01L27/14643 , H04N5/353
摘要： A large format imager includes an array of pixels for converting electromagnetic radiation into electrical signals and a trigger to from an optical pulse so as to trigger the pixels to generate an integration period. Each pixel includes a photodiode to convert light intensity of high-frequency radiation into an electrical charge, a reset switch to reset the photodiode, circuitry to enable sampling of the electrical charge produced by the photodiode, a photoswitch to convert an optical trigger pulse, received from the trigger, into an electrical signal, an inverter to produce a control signal corresponding to the electrical signal produced by the photoswitch, and control circuitry to locally generate integration control signals. The integration control signals control a start of an integration period for the photodiode, duration of the integration period for the photodiode, and the sampling of the electrical charge produced by the photodiode. The large format imager may also include a trigger for producing an electrical pulse so as to trigger the pixels to generate an integration period and tree type electrical distribution system for propagating the electrical pulse to all the pixels, wherein each pixel includes a global repeater circuit to propagate a first edge of said electrical pulse along said tree type electrical distribution system and a local repeater circuit to provide a local array of pixels with the first edge of the electrical pulse.
摘要翻译：大格式成像器包括用于将电磁辐射转换为电信号的像素阵列和来自光脉冲的触发，以便触发像素以产生积分周期。每个像素包括光电二极管以将高频辐射的光强度转换为电荷，复位开关以复位光电二极管，电路以使得能够对由光电二极管产生的电荷进行采样，光接收器转换光接收脉冲从触发器转换成电信号，逆变器产生对应于由光开关产生的电信号的控制信号，以及控制电路以本地产生积分控制信号。积分控制信号控制光电二极管的积分周期的开始，光电二极管的积分周期的持续时间以及由光电二极管产生的电荷的采样。大格式成像器还可以包括用于产生电脉冲的触发器，以便触发像素以产生积分周期，并且用于将电脉冲传播到所有像素的树型配电系统，其中每个像素包括全局中继器电路沿着所述树型配电系统和本地中继器电路传播所述电脉冲的第一边缘，以向电脉冲的第一边缘提供局部阵列阵列。

7. 发明授权

US5298787A Semiconductor embedded layer technology including permeable base transistor 失效
标题翻译：半导体嵌入层技术包括可渗透晶体管
公开(公告)号：US5298787A
公开(公告)日：1994-03-29
申请号：US678670
申请日：1991-04-01
申请人： Carl O. Bozler , Gary D. Alley , William T. Lindley , R. Allen Murphy
发明人： Carl O. Bozler , Gary D. Alley , William T. Lindley , R. Allen Murphy
IPC分类号： H01L21/20 , H01L21/335 , H01L21/74 , H01L23/482 , H01L23/52 , H01L23/535 , H01L29/772 , H01L29/92 , H01L27/082 , H01L27/102 , H01L29/00 , H01L29/30
CPC分类号： H01L21/02532 , H01L21/02395 , H01L21/0262 , H01L21/02639 , H01L21/743 , H01L23/4824 , H01L23/52 , H01L23/535 , H01L28/40 , H01L29/66424 , H01L29/7722 , H01L2924/0002 , H01L2924/3011
摘要： A permeable base transistor (30) including a metal base layer (34) embedded in a semiconductor crystal (32) to separate collector (38) and emitter (40) regions and form a Schottky barrier with each is diclosed. The metal base layer has at least one opening (37) through which the crystal semiconductor (32) joins the collector (38) and emitter (40) regions. Ohmic contacts (42,44) are made to the emitter (38) and collector (40) regions. The width of all openings (37) in the base layer (34) is of the order of the zero bias depletion width corresponding to the carrier concentration in the opening. The thickness of the metal layer (34) is in the order of 10% of this zero bias depletion width. As a result, a potential barrier in each opening limits current flow over the lower portion of the bias range. With increasing forward base bias the potential in the openings, which is lower than along the metal of the base layer (34), is lowered sufficiently to permit substantial increase in the barrier limited current flow from the collector (38) to emitter (40).
摘要翻译：包含嵌入在半导体晶体（32）中以分离集电极（38）和发射极（40）区域并与其形成肖特基势垒的金属基极层（34）的可渗透基极晶体管（30）被断开。金属基层具有至少一个开口（37），晶体半导体（32）通过该开口连接集电极（38）和发射极（40）区域。欧姆接触（42,44）制成发射极（38）和集电极（40）区域。基底层（34）中的所有开口（37）的宽度为与开口中的载流子浓度相对应的零偏置耗尽宽度的量级。金属层（34）的厚度为该零偏置耗尽宽度的10％量级。结果，每个开口中的势垒限制了偏压范围下部的电流。随着正向基极偏压的增加，开口中比基底层（34）的金属低的电位被充分降低，从而可以显着增加从集电器（38）到发射极（40）的阻挡限制电流，。

8. 发明授权

US4378629A Semiconductor embedded layer technology including permeable base transistor, fabrication method 失效
标题翻译：半导体嵌入层技术包括可渗透晶体管，制造方法
公开(公告)号：US4378629A
公开(公告)日：1983-04-05
申请号：US65514
申请日：1979-08-10
申请人： Carl O. Bozler , Gary D. Alley , William T. Lindley , R. Allen Murphy
发明人： Carl O. Bozler , Gary D. Alley , William T. Lindley , R. Allen Murphy
IPC分类号： H01L29/73 , H01L21/20 , H01L21/331 , H01L21/335 , H01L21/74 , H01L23/482 , H01L23/52 , H01L23/535 , H01L29/10 , H01L29/772 , H01L29/80 , H01L29/92 , H01L21/95
CPC分类号： H01L29/66424 , H01L21/02395 , H01L21/02532 , H01L21/02546 , H01L21/02639 , H01L21/743 , H01L23/4824 , H01L23/52 , H01L23/535 , H01L28/40 , H01L29/7722 , H01L2924/0002 , H01L2924/3011 , Y10S148/164
摘要： A layer of material such as the metal base of a transistor is embedded in single crystal. A layer of the material with small, uniformly dimensioned and uniformly spaced openings is formed on a single crystal substrate, and the single crystal is grown from the exposed portions of the substrate over the layer of material. For best results, the layer of material to be embedded is deposited relative to the crystal orientation to provide a much greater rate of crystal growth laterally across the layer than away from the crystal substrate. The method is particularly useful in fabricating a permeable base transistor having slits formed in the metal base layer. An integrated circuit can be fabricated by forming a pattern of conductive material on a single crystal, that pattern having continuous regions which inhibit further crystal growth and narrow regions or regions having openings therein which permit lateral crystal growth across those regions. In that way, the conductive pattern is selectively embedded with the continuous regions left exposed after crystal growth. Connections can be made between the exposed regions and a pattern on the new crystal layer. This method has particular usefulness in fabricating multi-level integrated circuits.
摘要翻译：诸如晶体管的金属基底的材料层被嵌入在单晶中。在单晶衬底上形成具有小的，均匀尺寸和均匀间隔的开口的材料层，并且单晶从衬底层的暴露部分生长在材料层上。为了获得最佳结果，相对于晶体取向沉积要嵌入的材料层，以提供横跨层的晶体生长比离开晶体衬底的更大的晶体生长速率。该方法在制造具有形成在金属基底层中的狭缝的可渗透的基极晶体管中特别有用。可以通过在单晶上形成导电材料图案来制造集成电路，该图案具有抑制进一步晶体生长的连续区域，并且具有允许在这些区域上横向晶体生长的窄区域或其中具有开口的区域。以这种方式，导电图案被选择性地嵌入在晶体生长后留下的连续区域。可以在曝光区域和新晶体层上的图案之间进行连接。该方法在制造多电平集成电路中具有特别的用途。

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