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1. 发明授权

US06842039B1 Configuration shift register 有权
标题翻译：配置移位寄存器
公开(公告)号：US06842039B1
公开(公告)日：2005-01-11
申请号：US10278177
申请日：2002-10-21
申请人： Mario Guzman , Christopher Lane , Andy Lee , Ninh Ngo
发明人： Mario Guzman , Christopher Lane , Andy Lee , Ninh Ngo
IPC分类号： H03K19/177 , G01R31/28
CPC分类号： H03K19/17752 , H03K19/1774 , H03K19/17744 , H03K19/17756
摘要： An electronic device comprises a first plurality of configuration elements connected as a shift register for programming a subset of the programmable functions of the electronic device. The subset of programmable functions may be reprogrammed by loading configuration data into the first plurality of configuration elements such that the subset of programmable functions may be reprogrammed without necessarily reprogramming other programmable functions of the electronic device.
摘要翻译：电子设备包括作为移位寄存器连接的第一多个配置元件，用于对电子设备的可编程功能的子集进行编程。可编程功能的子集可以通过将配置数据加载到第一多个配置元件中来重新编程，使得可编程功能的子集可以被重新编程，而不必重新编程电子设备的其他可编程功能。

2. 发明申请

US20080052569A1 ERROR DETECTION ON PROGRAMMABLE LOGIC RESOURCES 有权
标题翻译：对可编程逻辑资源的错误检测
公开(公告)号：US20080052569A1
公开(公告)日：2008-02-28
申请号：US11930739
申请日：2007-10-31
申请人： Ninh Ngo , Andy Lee , Kerry Veenstra
发明人： Ninh Ngo , Andy Lee , Kerry Veenstra
IPC分类号： G06F11/00
CPC分类号： H03K19/17764 , G06F11/1004
摘要： Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.
摘要翻译：在可编程逻辑资源上提供错误检测电路。可编程逻辑资源配置数据被加载到可以执行校验和计算的循环冗余校验（CRC）模块中。在一个实施例中，校验和可以与预期值进行比较，期望值是在被编程到数据被编程到可编程逻辑资源之前或数据被编程到数据之前的预计算校验和。在另一个实施例中，期望值可以包括在校验和计算中。可以根据校验和和期望值之间的关系或校验和的值来生成指示是否检测到错误的输出。该输出可以被发送到用户逻辑可访问的输出引脚。

3. 发明授权

US07215140B1 Programmable logic device having regions of non-repairable circuitry within an array of repairable circuitry and associated configuration hardware and method 有权
标题翻译：可编程逻辑器件具有可修复电路阵列内的不可修复电路区域和相关配置硬件和方法
公开(公告)号：US07215140B1
公开(公告)日：2007-05-08
申请号：US10452673
申请日：2003-05-30
申请人： Rahul Saini , Andy Lee , Ninh Ngo
发明人： Rahul Saini , Andy Lee , Ninh Ngo
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , H03K19/17732 , H03K19/17736 , H03K19/17764
摘要： An embodiment of the present invention provides a programmable logic device (“PLD”) including one or more dedicated blocks of circuitry within one or more repairable logic array regions. Aspects of the present invention provide circuitry and methods for controlling shifting of programming data in normal and redundant modes for both dedicated block regions and fully repairable logic array regions during both regular and test programming sequences of a PLD. Other aspects provide circuitry and methods for interface routing between dedicated blocks and repairable logic array regions in both normal and redundant modes. Various other aspects are also disclosed.
摘要翻译：本发明的一个实施例提供一种可编程逻辑器件（“PLD”），其包括一个或多个可修复逻辑阵列区域内的一个或多个专用电路块。本发明的方面提供用于在PLD的规则和测试编程序列期间控制专用块区域和完全可修复的逻辑阵列区域的正常和冗余模式中的编程数据的移位的电路和方法。其他方面提供用于在正常模式和冗余模式中的专用块和可修复逻辑阵列区之间的接口路由的电路和方法。还公开了各种其它方面。

4. 发明申请

US20070040577A1 Apparatus and methods for optimizing the performance of programmable logic devices 有权
标题翻译：用于优化可编程逻辑器件性能的装置和方法
公开(公告)号：US20070040577A1
公开(公告)日：2007-02-22
申请号：US11204570
申请日：2005-08-16
申请人： David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
发明人： David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
IPC分类号： H03K19/177
CPC分类号： G06F17/5081 , G06F17/5077 , H03K19/17784
摘要： A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a second supply voltage. At least one of the first and second supply voltages is determined by a PLD computer-aided design (CAD) flow used to implement the user's design in the PLD.
摘要翻译：可编程逻辑器件（PLD）包括第一和第二电路。第一和第二电路是使用PLD资源实现的用户设计的一部分。第一个电路由第一个电源供电。第二电路由第二电源供电。第一和第二电源电压中的至少一个由用于在PLD中实现用户设计的PLD计算机辅助设计（CAD）流确定。

5. 发明申请

US20080263490A1 APPARATUS AND METHODS FOR OPTIMIZING THE PERFORMANCE OF PROGRAMMABLE LOGIC DEVICES 有权
标题翻译：优化可编程逻辑器件性能的装置和方法
公开(公告)号：US20080263490A1
公开(公告)日：2008-10-23
申请号：US12165664
申请日：2008-07-01
申请人： David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
发明人： David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5077 , H03K19/17784
摘要： A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a second supply voltage. At least one of the first and second supply voltages is determined by a PLD computer-aided design (CAD) flow used to implement the user's design in the PLD.
摘要翻译：可编程逻辑器件（PLD）包括第一和第二电路。第一和第二电路是使用PLD资源实现的用户设计的一部分。第一个电路由第一个电源供电。第二电路由第二电源供电。第一和第二电源电压中的至少一个由用于在PLD中实现用户设计的PLD计算机辅助设计（CAD）流确定。

6. 发明申请

US20120089958A1 Apparatus and Methods for Optimizing the Performance of Programmable Logic Devices 审中-公开
标题翻译：用于优化可编程逻辑器件性能的装置和方法
公开(公告)号：US20120089958A1
公开(公告)日：2012-04-12
申请号：US13326082
申请日：2011-12-14
申请人： David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
发明人： David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5077 , H03K19/17784
摘要： A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a second supply voltage. At least one of the first and second supply voltages is determined by a PLD computer-aided design (CAD) flow used to implement the user's design in the PLD.
摘要翻译：可编程逻辑器件（PLD）包括第一和第二电路。第一和第二电路是使用PLD资源实现的用户设计的一部分。第一个电路由第一个电源供电。第二电路由第二电源供电。第一和第二电源电压中的至少一个由用于在PLD中实现用户设计的PLD计算机辅助设计（CAD）流确定。

7. 发明授权

US08103975B2 Apparatus and methods for optimizing the performance of programmable logic devices using multiple supply voltage 有权
标题翻译：使用多电源电压优化可编程逻辑器件的性能的装置和方法
公开(公告)号：US08103975B2
公开(公告)日：2012-01-24
申请号：US12165664
申请日：2008-07-01
申请人： David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
发明人： David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5077 , H03K19/17784
摘要： A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a second supply voltage. At least one of the first and second supply voltages is determined by a PLD computer-aided design (CAD) flow used to implement the user's design in the PLD.
摘要翻译：可编程逻辑器件（PLD）包括第一和第二电路。第一和第二电路是使用PLD资源实现的用户设计的一部分。第一个电路由第一个电源供电。第二电路由第二电源供电。第一和第二电源电压中的至少一个由用于在PLD中实现用户设计的PLD计算机辅助设计（CAD）流确定。

8. 发明申请

US20070040576A1 Apparatus and methods for power management in integrated circuits 有权
标题翻译：集成电路中电源管理的装置和方法
公开(公告)号：US20070040576A1
公开(公告)日：2007-02-22
申请号：US11316390
申请日：2005-12-22
申请人： David Lewis , Christopher Lane , Sarathy Sribhashyam , Srinivas Perisetty , Tim Vanderhoek , Vaughn Betz , Thomas Wong , Andy Lee
发明人： David Lewis , Christopher Lane , Sarathy Sribhashyam , Srinivas Perisetty , Tim Vanderhoek , Vaughn Betz , Thomas Wong , Andy Lee
IPC分类号： H03K19/177
CPC分类号： G06F17/5081 , G06F17/5077 , H03K19/17784
摘要： A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.
摘要翻译：可编程逻辑器件（PLD）包括非易失性存储器，配置存储器和控制电路。控制电路耦合到非易失性存储器和配置存储器。一组电压从控制电路的输出导出，并被应用于PLD内的电路。

9. 发明授权

US06965249B2 Programmable logic device with redundant circuitry 失效
标题翻译：具有冗余电路的可编程逻辑器件
公开(公告)号：US06965249B2
公开(公告)日：2005-11-15
申请号：US10159581
申请日：2002-05-30
申请人： Christopher Lane , Ketan Zaveri , Hyun Yi , Giles Powell , Paul Leventis , David Jefferson , David Lewis , Triet Nguyen , Vikram Santurkar , Michael Chan , Andy Lee , Brian Johnson , David Cashman
发明人： Christopher Lane , Ketan Zaveri , Hyun Yi , Giles Powell , Paul Leventis , David Jefferson , David Lewis , Triet Nguyen , Vikram Santurkar , Michael Chan , Andy Lee , Brian Johnson , David Cashman
IPC分类号： H01L21/82 , H03K19/177
CPC分类号： H03K19/17764 , H03K19/17736 , H03K19/17744
摘要： A programmable logic device and associated method is provided with repairable regions. In one aspect, general routing interconnect lines are segmented within repairable regions. In another aspect, IO bus lines and associated circuitry are provided that accommodate redundancy in a staggered segmented architecture. In another aspect, a dedicated routing architecture between particular logic regions accommodates shifting to define and utilize repairable regions. Principles of other aspects are illustrated and described in the context of several exemplary embodiments of aspects of the invention.
摘要翻译：可编程逻辑器件和相关方法提供有可修复区域。在一个方面，一般布线互连线在可修复区域内被分段。在另一方面，提供IO总线线路和相关电路，其适应交错分段结构中的冗余。在另一方面，特定逻辑区域之间的专用路由架构适应移位以限定和利用可修复区域。在本发明的方面的几个示例性实施例的上下文中示出和描述了其它方面的原理。

10. 发明申请

US20050127944A1 Versatile logic element and logic array block 有权
公开(公告)号：US20050127944A1
公开(公告)日：2005-06-16
申请号：US11050111
申请日：2005-02-02
申请人： David Lewis , Paul Leventis , Andy Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
发明人： David Lewis , Paul Leventis , Andy Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17764 , H03K19/1737 , H03K19/17728 , H03K19/17736
摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

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