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1. 发明授权

US07215140B1 Programmable logic device having regions of non-repairable circuitry within an array of repairable circuitry and associated configuration hardware and method 有权
标题翻译：可编程逻辑器件具有可修复电路阵列内的不可修复电路区域和相关配置硬件和方法
公开(公告)号：US07215140B1
公开(公告)日：2007-05-08
申请号：US10452673
申请日：2003-05-30
申请人： Rahul Saini , Andy Lee , Ninh Ngo
发明人： Rahul Saini , Andy Lee , Ninh Ngo
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , H03K19/17732 , H03K19/17736 , H03K19/17764
摘要： An embodiment of the present invention provides a programmable logic device (“PLD”) including one or more dedicated blocks of circuitry within one or more repairable logic array regions. Aspects of the present invention provide circuitry and methods for controlling shifting of programming data in normal and redundant modes for both dedicated block regions and fully repairable logic array regions during both regular and test programming sequences of a PLD. Other aspects provide circuitry and methods for interface routing between dedicated blocks and repairable logic array regions in both normal and redundant modes. Various other aspects are also disclosed.
摘要翻译：本发明的一个实施例提供一种可编程逻辑器件（“PLD”），其包括一个或多个可修复逻辑阵列区域内的一个或多个专用电路块。本发明的方面提供用于在PLD的规则和测试编程序列期间控制专用块区域和完全可修复的逻辑阵列区域的正常和冗余模式中的编程数据的移位的电路和方法。其他方面提供用于在正常模式和冗余模式中的专用块和可修复逻辑阵列区之间的接口路由的电路和方法。还公开了各种其它方面。

2. 发明授权

US06842039B1 Configuration shift register 有权
标题翻译：配置移位寄存器
公开(公告)号：US06842039B1
公开(公告)日：2005-01-11
申请号：US10278177
申请日：2002-10-21
申请人： Mario Guzman , Christopher Lane , Andy Lee , Ninh Ngo
发明人： Mario Guzman , Christopher Lane , Andy Lee , Ninh Ngo
IPC分类号： H03K19/177 , G01R31/28
CPC分类号： H03K19/17752 , H03K19/1774 , H03K19/17744 , H03K19/17756
摘要： An electronic device comprises a first plurality of configuration elements connected as a shift register for programming a subset of the programmable functions of the electronic device. The subset of programmable functions may be reprogrammed by loading configuration data into the first plurality of configuration elements such that the subset of programmable functions may be reprogrammed without necessarily reprogramming other programmable functions of the electronic device.
摘要翻译：电子设备包括作为移位寄存器连接的第一多个配置元件，用于对电子设备的可编程功能的子集进行编程。可编程功能的子集可以通过将配置数据加载到第一多个配置元件中来重新编程，使得可编程功能的子集可以被重新编程，而不必重新编程电子设备的其他可编程功能。

3. 发明申请

US20080052569A1 ERROR DETECTION ON PROGRAMMABLE LOGIC RESOURCES 有权
标题翻译：对可编程逻辑资源的错误检测
公开(公告)号：US20080052569A1
公开(公告)日：2008-02-28
申请号：US11930739
申请日：2007-10-31
申请人： Ninh Ngo , Andy Lee , Kerry Veenstra
发明人： Ninh Ngo , Andy Lee , Kerry Veenstra
IPC分类号： G06F11/00
CPC分类号： H03K19/17764 , G06F11/1004
摘要： Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.
摘要翻译：在可编程逻辑资源上提供错误检测电路。可编程逻辑资源配置数据被加载到可以执行校验和计算的循环冗余校验（CRC）模块中。在一个实施例中，校验和可以与预期值进行比较，期望值是在被编程到数据被编程到可编程逻辑资源之前或数据被编程到数据之前的预计算校验和。在另一个实施例中，期望值可以包括在校验和计算中。可以根据校验和和期望值之间的关系或校验和的值来生成指示是否检测到错误的输出。该输出可以被发送到用户逻辑可访问的输出引脚。

4. 发明授权

US07671625B1 Omnibus logic element 有权
标题翻译：综合逻辑元素
公开(公告)号：US07671625B1
公开(公告)日：2010-03-02
申请号：US12043087
申请日：2008-03-05
申请人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Michael Hutton , Andy Lee , Rahul Saini , Henry Kim
发明人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Michael Hutton , Andy Lee , Rahul Saini , Henry Kim
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , G06F7/50 , H03K19/017581
摘要： Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.
摘要翻译：公开了可以提供许多有利特征的LE。例如，LE可以提供LUT和输入共享的高效灵活的使用。 LE还可以灵活地使用一个或多个专用加法器并且包括寄存器功能。

5. 发明授权

US07911230B1 Omnibus logic element for packing or fracturing 有权
$Omnibus logic element for packing or fracturing$
标题翻译：用于包装或压裂的综合逻辑元件
公开(公告)号：US07911230B1
公开(公告)日：2011-03-22
申请号：US12425342
申请日：2009-04-16
申请人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
发明人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
IPC分类号： H03K19/173
CPC分类号： H03K19/17728 , G06F7/50 , H03K19/017581
摘要： Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.
摘要翻译：公开了可以提供多个有利特征的逻辑元件（LE）。例如，LE可以被配置为实现寄存器打包和/或可破碎的查找表。

6. 发明授权

US07538579B1 Omnibus logic element 有权
标题翻译：综合逻辑元素
公开(公告)号：US07538579B1
公开(公告)日：2009-05-26
申请号：US11607171
申请日：2006-12-01
申请人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
发明人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , G06F7/50 , H03K19/017581
摘要： Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.
摘要翻译：公开了可以提供许多有利特征的LE。例如，LE可以提供LUT和输入共享的高效灵活的使用。 LE还可以灵活地使用一个或多个专用加法器并且包括寄存器功能。

7. 发明授权

US08593174B1 Omnibus logic element for packing or fracturing 有权
$Omnibus logic element for packing or fracturing$
标题翻译：用于包装或压裂的综合逻辑元件
公开(公告)号：US08593174B1
公开(公告)日：2013-11-26
申请号：US13539007
申请日：2012-06-29
申请人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
发明人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , G06F7/50 , H03K19/017581
摘要： Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.
摘要翻译：公开了可以提供多个有利特征的逻辑元件（LE）。例如，LE可以被配置为实现寄存器打包和/或可破碎的查找表。

8. 发明授权

US08237465B1 Omnibus logic element for packing or fracturing 有权
$Omnibus logic element for packing or fracturing$
标题翻译：用于包装或压裂的综合逻辑元件
公开(公告)号：US08237465B1
公开(公告)日：2012-08-07
申请号：US13050732
申请日：2011-03-17
申请人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
发明人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , G06F7/50 , H03K19/017581
摘要： Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.
摘要翻译：公开了可以提供多个有利特征的逻辑元件（LE）。例如，LE可以被配置为实现寄存器打包和/或可破碎的查找表。

9. 发明授权

US07167022B1 Omnibus logic element including look up table based logic elements 有权
标题翻译：综合逻辑元素包括基于查询表的逻辑元素
公开(公告)号：US07167022B1
公开(公告)日：2007-01-23
申请号：US10810117
申请日：2004-03-25
申请人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
发明人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , G06F7/50 , H03K19/017581
摘要： Disclosed is an LE that can provide a number of advantageous feature. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.
摘要翻译：公开了可以提供多个有利特征的LE。例如，LE可以提供LUT和输入共享的高效灵活的使用。 LE还可以灵活地使用一个或多个专用加法器并且包括寄存器功能。

10. 发明授权

US07103813B1 Method and apparatus for testing interconnect bridging faults in an FPGA 失效
标题翻译：用于测试FPGA中互连桥接故障的方法和装置
公开(公告)号：US07103813B1
公开(公告)日：2006-09-05
申请号：US10703400
申请日：2003-11-06
申请人： Paul Tracy , Anthony Pang , Andy Lee , Adam Wright , Rahul Saini
发明人： Paul Tracy , Anthony Pang , Andy Lee , Adam Wright , Rahul Saini
IPC分类号： G01R31/02 , G06F11/267
CPC分类号： G01R31/31717 , G01R31/318519
摘要： A bridging fault detection system allows for a high amount of test coverage using a low number of test configurations. The bridging fault detection system automatically creates optimal test configurations and test vectors without the need for precise layout information, and is adaptable to complex programmable device architectures. Testers can specify a precise level of testing coverage to optimize the testing processing. A programmable device with interconnect bias circuitry decreases the number of test configurations and thus the time needed to test for bridging faults. The interconnect bias circuit provides explicit test control over the unused lines in a configuration, driving them both high and low for complete test coverage between each line and all of its possible neighbors. The bridging fault detection system balances the available number of control test points against the number of interconnect segments stitched together by programmable connection to maximize the lines under test per configuration.
摘要翻译：桥接故障检测系统允许使用低数量的测试配置进行大量的测试覆盖。桥接故障检测系统自动创建最佳测试配置和测试向量，而不需要精确的布局信息，并且适用于复杂的可编程设备架构。测试人员可以指定一个精确的测试覆盖水平以优化测试处理。具有互连偏置电路的可编程器件减少测试配置的数量，从而减少测试桥接故障所需的时间。互连偏置电路在配置中对未使用的线路提供显式测试控制，驱动它们高和低以在每条线路与其所有可能的邻居之间完成测试覆盖。桥接故障检测系统通过可编程连接平衡可用数量的控制测试点与拼接在一起的互连段的数量，以最大化每个配置的待测线路。

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