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    • 1. 发明授权
    • High-voltage semiconductor device
    • 高压半导体器件
    • US5497010A
    • 1996-03-05
    • US78281
    • 1993-06-16
    • Manfred VogelWerner HerdenVolkmar DennerAnton Mindl
    • Manfred VogelWerner HerdenVolkmar DennerAnton Mindl
    • F02P7/03H01L27/12H01L29/861H01L29/866H01L29/74H01L31/111
    • F02P7/035H01L27/12
    • The high-voltage semiconductor device includes a single chip having a plurality of semiconductor elements connected in series with each other which includes an insulating substrate (2); a monocrystalline semiconductor carrier (1) of a first conductivity type applied to the insulating substrate (2); at least two terminals (5,6) located on opposite sides of the chip; strip-like areas (3) of a second conductivity type formed in the monocrystalline semiconductor carrier (1), the strip-like areas (3) each extending across the semiconductor carrier (1) at right angles to a longitudinal direction between the at least two terminals, forming pn junctions in the semiconductor carrier (1), being spaced from each other in the longitudinal direction over the single chip and penetrating an entire thickness of the semiconductor carrier; at least one doped region (7) in the strip-like areas (3) forming an at least four layered component in the single chip; and a light responsive device for reducing a switching voltage of the single chip when the pn junctions are irradiated with light.
    • PCT No.PCT / DE91 / 00900 Sec。 371日期:1993年6月16日 102(e)日期1993年6月16日PCT 1991年11月16日PCT PCT。 公开号WO92 / 11659 日期:1992年7月19日。高电压半导体器件包括具有彼此串联连接的多个半导体元件的单个芯片,其包括绝缘基板(2); 施加到所述绝缘基板(2)的第一导电类型的单晶半导体载体(1); 位于所述芯片的相对侧上的至少两个端子(5,6); 在单晶半导体载体(1)中形成的第二导电类型的条状区域(3),每个在半导体载体(1)之间延伸的条状区域(3)与至少在纵向方向成直角 在半导体载体(1)中形成pn结的两个端子在单个芯片上沿纵向彼此间隔开并穿透半导体载体的整个厚度; 所述带状区域(3)中的至少一个掺杂区域(7)在所述单个芯片中形成至少四层分层; 以及用于在用光照射pn结时降低单个芯片的开关电压的光响应装置。
    • 3. 发明授权
    • Monolithically integrated circuit
    • 单片集成电路
    • US5432371A
    • 1995-07-11
    • US167839
    • 1993-12-20
    • Volkmar DennerWolfgang TroelenbergPeter BrauchleWilliam-Neil FoxNeil Davies
    • Volkmar DennerWolfgang TroelenbergPeter BrauchleWilliam-Neil FoxNeil Davies
    • H01L27/04H01L21/822H01L27/02H01L27/088H01L29/78
    • H01L29/7803H01L27/0251H01L2924/0002
    • A monolithically integrated circuit arrangement is arranged in a disc-shaped monocrystalline semiconductor body (100) of a first conductivity type, which semiconductor body consists of silicon and has a first and second main surface. The monolithically integrated circuit arrangement contains a vertical MOSFET power transistor (T1) which consists of a plurality of partial transistors connected in parallel and surrounded by a guard ring (4) of a second conductivity type opposite that of the semiconductor body (100). Proceeding from the first main surface (13), at least one zone (7, 8) of the conductivity type of the semiconductor body (100) but of increased impurity concentration is diffused into the guard ring (4) so as to form at least one active and/or passive peripheral circuit element (T2) which has a protective and/or regulating and/or control function.
    • PCT No.PCT / DE92 / 00479 Sec。 371日期:1993年12月20日 102(e)日期1993年12月20日PCT提交1992年6月10日PCT公布。 公开号WO93 / 00709 日期:1993年1月7日。单片集成电路布置在第一导电类型的盘状单晶体半导体本体(100)中,该半导体主体由硅组成并具有第一和第二主表面。 单片集成电路装置包括垂直MOSFET功率晶体管(T1),其由并联连接并由与半导体本体(100)相反的第二导电类型的保护环(4)包围的多个部分晶体管组成。 从第一主表面(13)开始,半导体主体(100)的导电类型的至少一个区域(7,8)扩散到保护环(4)中,以至少形成 具有保护和/或调节和/或控制功能的一个有源和/或无源外围电路元件(T2)。
    • 4. 发明授权
    • Process for determining the position of a p-n transition
    • 确定p-n转换位置的过程
    • US5256577A
    • 1993-10-26
    • US853768
    • 1992-06-02
    • Christian PluntkeChristoph ThienelVolkmar Denner
    • Christian PluntkeChristoph ThienelVolkmar Denner
    • H01L21/66G01R31/265H01L23/544
    • H01L22/34G01R31/2656
    • The invention relates to a method of determining the position of a p-n junction or the depth of penetration of the diffused electrode in the case of semiconductor devices produced by planar technology. According to the invention, a test pattern which comprises N pairs of windows, the spacing of which increases from pair to pair, is included in exposure. During the diffusion operation, the tubs produced overlap in the pairs of windows lying relatively close together, touch in one pair of windows (n.sub.o) and are separate from each other in pairs of windows lying relatively far apart. With the aid of a resistance measurement, the pair of windows (n.sub.o) in which the two tubs are still just touching is established, from which the lateral depth of penetration Y.sub.j is obtained as half the spacing of this pair of windows. From the lateral depth of penetration, the vertical depth of penetration X.sub.j can be established by means of the relationship X.sub.j =C.multidot.Y.sub.j. In developments of the method, there is also specified a correction possibility for the difference between layout dimension and etching dimension as well as a further possibility of establishing the exact value of the lateral depth of penetration Y.sub.jo. In the case of this possibility, the doping of the material which is diffused into can be determined.
    • 本发明涉及在通过平面技术制造的半导体器件的情况下确定p-n结的位置或扩散电极的穿透深度的方法。 根据本发明,在曝光中包括包括N对窗口的测试图案,其间隔从一对到另一对增加。 在扩散操作期间,在相对靠近在一起的两对窗口中产生的桶重叠,在一对窗口(否)中触摸并且在相对较远的两对窗口中彼此分开。 借助于电阻测量,建立了两个浴缸仍然刚刚接触的一对窗口(否),从而从该窗口获得横向深度Yj作为该对窗口的间隔的一半。 从横向的穿透深度可以通过Xj = CxYj的关系建立垂直的穿透深度Xj。 在该方法的开发中,还规定了布局尺寸和蚀刻尺寸之间的差异的校正可能性,以及建立横向深度穿透Yjo的精确值的另一可能性。 在这种情况下,可以确定扩散的材料的掺杂。