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1. 发明授权

US09153523B2 ASIC element including a via 有权
标题翻译： ASIC元件包括通孔
公开(公告)号：US09153523B2
公开(公告)日：2015-10-06
申请号：US14307108
申请日：2014-06-17
申请人： Heribert Weber , Hartmut Kueppers , Jochen Reinmuth , Neil Davies , Jens Frey
发明人： Heribert Weber , Hartmut Kueppers , Jochen Reinmuth , Neil Davies , Jens Frey
IPC分类号： H01L23/52 , H01L23/48 , B81C3/00
CPC分类号： H01L23/481 , B81C1/00238 , B81C3/001 , B81C2203/0109 , B81C2203/0792 , G01C19/5783 , H01L2924/0002 , H01L2924/00
摘要： In an ASIC element, vias are integrated into the CMOS processing of an ASIC substrate. The ASIC element includes an active front side in which the circuit functions are implemented. The at least one via is intended to establish an electrical connection between the active front side and the rear side of the element. The front side of the via is defined by at least one front-side trench which is completely filled, and the rear side is defined by at least one rear-side trench which is not completely filled. The rear-side trench opens into the filled front-side trench.
摘要翻译：在ASIC元件中，通孔被集成到ASIC基板的CMOS处理中。 ASIC元件包括其中实现电路功能的主动正面。该至少一个通孔旨在在元件的主动前侧和后侧之间建立电连接。通孔的前侧由完全填充的至少一个前侧沟槽限定，并且后侧由未完全填充的至少一个后侧沟槽限定。后侧沟槽穿过填充的前侧沟槽。

2. 发明申请

US20140374917A1 COMPONENT IN THE FORM OF A WAFER LEVEL PACKAGE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译： WAFER LEVEL PACKAGE形式的组件及其制造方法
公开(公告)号：US20140374917A1
公开(公告)日：2014-12-25
申请号：US14307055
申请日：2014-06-17
申请人： Heribert WEBER , Hartmut KUEPPERS , Jens Reutlingen , Neil DAVIES
发明人： Heribert WEBER , Hartmut KUEPPERS , Jens Reutlingen , Neil DAVIES
IPC分类号： H01L23/538 , H01L25/065
CPC分类号： H01L29/0657 , B81C1/00238 , B81C2203/0118 , B81C2203/0792 , H01L23/3114 , H01L25/0657 , H01L25/50 , H01L2224/48091 , H01L2224/48471 , H01L2225/06506 , H01L2225/06568 , H01L2924/00014
摘要： A vertically integrated hybrid component is implemented in the form of a wafer level package including: at least two element substrates assembled one above the other; a molded upper sealing layer made of an electrically insulating casting; and an external electrical contacting of the component being implemented on the top side via at least one contact stamp which is embedded in the sealing layer so that (i) its lower end is connected to a wiring level of an element substrate and (ii) its upper end is exposed in the surface of the sealing layer.
摘要翻译：垂直集成的混合部件以晶片级封装的形式实现，包括：至少两个元件基板，一个彼此组装; 由电绝缘铸件制成的模制上密封层; 并且所述部件的外部电接触通过嵌入在所述密封层中的至少一个接触印模在顶侧上实现，使得（i）其下端连接到元件基板的布线层，以及（ii）其上端暴露在密封层的表面。

3. 发明申请

US20080187602A1 STABILIZED LANTHANUM CARBONATE COMPOSITIONS 审中-公开
标题翻译：稳定的碳酸钙组合物
公开(公告)号：US20080187602A1
公开(公告)日：2008-08-07
申请号：US12100224
申请日：2008-04-09
申请人： Josephine Christine Ferdinando , Petet Neil Davies
发明人： Josephine Christine Ferdinando , Petet Neil Davies
IPC分类号： A61K33/24 , A61P7/00
CPC分类号： A61K33/24 , A61J3/10 , A61K9/0056 , A61K9/2013 , A61K9/2018 , A61K9/2059 , Y10S514/96
摘要： Stabilized lanthanum carbonate compositions containing a monosaccharide or disaccharide stabilizing agent are disclosed. Subjects having hyperphosphatemia can be treated by administering a pharmaceutical composition containing a therapeutically effective amount of the stabilized lanthanum carbonate formulation.
摘要翻译：公开了含有单糖或二糖稳定剂的稳定的碳酸镧组合物。可以通过施用含有治疗有效量的稳定的碳酸镧制剂的药物组合物来治疗具有高磷酸血症的受试者。

4. 外观设计

USD532308S1 Container 失效
公开(公告)号：USD532308S1
公开(公告)日：2006-11-21
申请号：US29207757
申请日：2004-06-17
申请人： Jonathan Neil Davies , William Arthur Hinshelwood Sherman
设计人： Jonathan Neil Davies , William Arthur Hinshelwood Sherman

5. 外观设计

USD529810S1 Bottle 失效
公开(公告)号：USD529810S1
公开(公告)日：2006-10-10
申请号：US29192566
申请日：2003-10-27
申请人： Jonathan Neil Davies , Martyn Noel Wallwork
设计人： Jonathan Neil Davies , Martyn Noel Wallwork

6. 外观设计

USD525131S1 Jar 失效
公开(公告)号：USD525131S1
公开(公告)日：2006-07-18
申请号：US29192568
申请日：2003-10-27
申请人： Jonathan Neil Davies , Martyn Noel Wallwork
设计人： Jonathan Neil Davies , Martyn Noel Wallwork

7. 发明授权

US06614552B2 Producing visual images 失效
标题翻译：制作视觉图像
公开(公告)号：US06614552B2
公开(公告)日：2003-09-02
申请号：US08750217
申请日：1996-12-03
申请人： Neil Davies , Malcolm McCormick
发明人： Neil Davies , Malcolm McCormick
IPC分类号： H04N1387
CPC分类号： H04N1/387 , B41M3/06 , G02B3/0043 , G02B3/005 , G02B3/0056 , G02B3/0062 , G02B27/2214 , G02B27/2228 , G03B35/00 , H04N1/00 , H04N5/74
摘要： A method for reproducing an integral, panoramogramic or full spatial image for viewing using a decoding screen as a 3-D picture comprising representing the image as an array of image points with a density corresponding to high resolution ink printing.
摘要翻译：一种用于使用解码屏幕再现用于观看的整体的全景图或全空间图像作为3-D图像的方法，包括将图像表示为具有对应于高分辨率墨水打印的密度的图像点的阵列。

8. 发明授权

US5654863A Integrated circuit having a gate oxide 失效
标题翻译：具有栅极氧化物的集成电路
公开(公告)号：US5654863A
公开(公告)日：1997-08-05
申请号：US744684
申请日：1996-11-07
申请人： Neil Davies
发明人： Neil Davies
IPC分类号： H01L27/04 , G01R31/26 , G01R31/28 , H01L21/82 , H01L21/822 , H01L27/02 , H01L29/866 , H02H9/04
CPC分类号： G01R31/2884 , G01R31/2621 , H01L27/0251
摘要： An integrated circuit having a gate oxide, preferably for a DMOS circuit having a protective device against electrostatic overvoltages (ESD), is to connect a limiting circuit in series with the protective device. This series circuit means that, during the wafer production, an increased voltage can be applied to the gate of the integrated circuit, for testing the gate oxide, without the circuit being limited to a lower value. After testing, the limiting circuit is connected irreversibly in its low-resistance state, with the result that subsequent ESD interference voltages are limited by the built-in protective device. A zener zapping diode is provided as the limiting circuit. An advantageous result of the arrangement is the fact that an additional bonding connection for connecting the gate connection to the protective device is no longer necessary.
摘要翻译：具有栅极氧化物的集成电路，优选用于具有防静电过电压（ESD）的保护装置的DMOS电路，是将限制电路与保护装置串联连接。该串联电路意味着，在晶片生产期间，可以向集成电路的栅极施加增加的电压，用于测试栅极氧化物，而不将电路限制在较低的值。测试后，限制电路在其低电阻状态下不可逆地连接，结果是后续ESD干扰电压受到内置保护装置的限制。提供齐纳二极管作为限制电路。该布置的有利结果是不再需要用于将栅极连接连接到保护装置的附加接合连接。

9. 发明授权

US5432371A Monolithically integrated circuit 失效
标题翻译：单片集成电路
公开(公告)号：US5432371A
公开(公告)日：1995-07-11
申请号：US167839
申请日：1993-12-20
申请人： Volkmar Denner , Wolfgang Troelenberg , Peter Brauchle , William-Neil Fox , Neil Davies
发明人： Volkmar Denner , Wolfgang Troelenberg , Peter Brauchle , William-Neil Fox , Neil Davies
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/088 , H01L29/78
CPC分类号： H01L29/7803 , H01L27/0251 , H01L2924/0002
摘要： A monolithically integrated circuit arrangement is arranged in a disc-shaped monocrystalline semiconductor body (100) of a first conductivity type, which semiconductor body consists of silicon and has a first and second main surface. The monolithically integrated circuit arrangement contains a vertical MOSFET power transistor (T1) which consists of a plurality of partial transistors connected in parallel and surrounded by a guard ring (4) of a second conductivity type opposite that of the semiconductor body (100). Proceeding from the first main surface (13), at least one zone (7, 8) of the conductivity type of the semiconductor body (100) but of increased impurity concentration is diffused into the guard ring (4) so as to form at least one active and/or passive peripheral circuit element (T2) which has a protective and/or regulating and/or control function.
摘要翻译： PCT No.PCT / DE92 / 00479 Sec。 371日期：1993年12月20日 102（e）日期1993年12月20日PCT提交1992年6月10日PCT公布。公开号WO93 / 00709 日期：1993年1月7日。单片集成电路布置在第一导电类型的盘状单晶体半导体本体（100）中，该半导体主体由硅组成并具有第一和第二主表面。单片集成电路装置包括垂直MOSFET功率晶体管（T1），其由并联连接并由与半导体本体（100）相反的第二导电类型的保护环（4）包围的多个部分晶体管组成。从第一主表面（13）开始，半导体主体（100）的导电类型的至少一个区域（7,8）扩散到保护环（4）中，以至少形成具有保护和/或调节和/或控制功能的一个有源和/或无源外围电路元件（T2）。

10. 发明申请

US20100140618A1 Sensor and method for the manufacture thereof 有权
标题翻译：传感器及其制造方法
公开(公告)号：US20100140618A1
公开(公告)日：2010-06-10
申请号：US12590585
申请日：2009-11-10
申请人： Jochen Reinmuth , Neil Davies , Simon Armbruster , Ando Feyh
发明人： Jochen Reinmuth , Neil Davies , Simon Armbruster , Ando Feyh
IPC分类号： H01L31/103 , H01L31/18
CPC分类号： G01J5/20 , G01J5/08 , G01J5/0853 , H01L27/14649
摘要： A sensor includes at least one micro-patterned diode pixel that has a diode implemented in, on, or under a diaphragm, and the diaphragm in turn being implemented above a cavity. The diode is contacted via supply leads that are implemented at least in part in, on, or under the diaphragm, and the diode is implemented in a polycrystalline semiconductor layer. The diode is implemented by way of two low-doped diode regions or at least one low-doped diode region. At least parts of the supply leads are implemented by way of highly doped supply lead regions of the shared polycrystalline semiconductor layer.
摘要翻译：传感器包括至少一个微图案化的二极管像素，其具有在隔膜内，上或下面实现的二极管，并且隔膜依次在空腔上方实现。二极管通过至少部分地在隔膜中，上或下面实现的电源引线接触，并且二极管实现在多晶半导体层中。二极管通过两个低掺杂二极管区域或至少一个低掺杂二极管区域实现。供电线的至少一部分通过共享多晶半导体层的高掺杂电源引线区实现。

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