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1. 发明专利

JPS5825230A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5825230A
公开(公告)日：1983-02-15
申请号：JP12490481
申请日：1981-08-07
申请人： MITSUBISHI ELECTRIC CORP
发明人： KOTANI HIDEO , OOHAYASHI YOSHIKAZU
IPC分类号： H01L23/52 , H01L21/28 , H01L21/285 , H01L21/3205
摘要： PURPOSE:To prevent the diffusion of Al alloy in the formation of an Al wiring film by decreasing the Si density distribution in an Al alloy target for sputtering with increasing length in a transfer direction of the target or a wafer so as to control the Si density thicknesswise in the evaporated Al alloy wiring film. CONSTITUTION:A multiple of semiconductor wafers 1 are placed on a pallet carrier 2, and an Al alloy wiring film is formed on the wafer 1 by sputtering from an Al target 3 above the carrier 2 being moved in the direction shown. In this process the Si density distribution in the target 3 is adjusted to decrease with increasing length in a transfer direction of the carrier 2. Assume that D is the Si density and S is the transfer length, then D is decreased in the transfer direction as shown in the figure. This constitution prevents Al from penetrating a shallow diffusion layer on the substrate, and also lowers the wiring resistance which improves the adhesion of the bonding portion.

2. 发明专利

JPS5743459A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS5743459A
公开(公告)日：1982-03-11
申请号：JP11997280
申请日：1980-08-28
申请人： Mitsubishi Electric Corp
发明人： OOHAYASHI YOSHIKAZU , DENDA MASAHIKO , KINOSHITA SHIGEJI , SATOU SHINICHI , TSUBOUCHI NATSUO
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10805
摘要： PURPOSE:To improve the speed performance of the transistor of a semiconductor memory and the erroneous operation resistance of the transistor due to alpha rays by increasing the thickness of the epitaxial layer of the transistor, and decreasing the thickness of the epitaxial layer of a capacitor and a bit line. CONSTITUTION:The thicknesses of low spcecific resistance epitaxial layers 2 at the capacitor and the bit line of a memory cell using epitaxial layers are set to (A- DELTAA), (C-DELTAC), and the thickness of the transistor is increased to (B-DELTAB) larger than the above thicknesses. That is, the epitaxial layer 2 is grown to 5-6mum corresponding to the thickness of the transistor, and the parts to become the capacitor and the bit line are decreased in thickness to approx. 1-2mum, for example, by a silicon etching.
摘要翻译：目的：通过增加晶体管的外延层的厚度，并减小电容器的外延层的厚度，提高半导体存储器的晶体管的速度性能和由于α射线导致的晶体管的误操作电阻，以及有点线。构成：使用外延层的电容器和存储器单元的低电阻外延层2的厚度被设置为（A- DELTAA），（C-DELTAC），并且晶体管的厚度增加到（ B-DELTAB）大于上述厚度。也就是说，对应于晶体管的厚度，外延层2生长到5-6μm，成为电容器和位线的部分的厚度减小到大约。例如，通过硅蚀刻。

3. 发明专利

JPS5743425A Forming method for fine pattern 失效
标题翻译：精细图案的形成方法
公开(公告)号：JPS5743425A
公开(公告)日：1982-03-11
申请号：JP11997680
申请日：1980-08-28
申请人： Mitsubishi Electric Corp
发明人： OOHAYASHI YOSHIKAZU , HARADA HIROJI , SHIBAYAMA ISAO , MASUKO YOUJI , NISHIOKA KIYUUSAKU
IPC分类号： H01L21/027
CPC分类号： H01L21/0271
摘要： PURPOSE:To obtain a fine pattern by forming a thin metallic film on a lower thin resist and an upper thick resist on the metallic film, etching the metallic film with the upper resist as a mask, and further etching the metallic film with the lower resist as a mask. CONSTITUTION:A thin metallic film 2 is formed on a glass substrate 1, a thin lower resist layer 6 is coated on the film, is patterned, and the processed part 4 is exposed. Then, a thin metallic film 7 is coated on the lower resist layer 6 including the exposed part, an upper resist layer 8 is coated thereon, and is patterned. With the upper resist layer 8 thus patterned as a mask the intermediate metallic film 7 is dry etched and removed, and the metallic film 2 is positively removed with high accuracy by dry etching with the layer 8, the film 7 and the layer 6 as masks.
摘要翻译：目的：为了通过在金属膜上的下层抗蚀剂和上部厚抗蚀剂上形成薄的金属膜来形成精细图案，用上部抗蚀剂作为掩模蚀刻金属膜，并用下部抗蚀剂进一步蚀刻金属膜作为面具。构成：在玻璃基板1上形成薄的金属膜2，在薄膜上涂布薄的下层抗蚀剂层6，进行图案化，使被处理部4露出。然后，在包括露出部分的下抗蚀剂层6上涂覆薄金属膜7，在其上涂覆上抗蚀剂层8并进行图案化。通过将上抗蚀剂层8图案化为掩模，中间金属膜7被干蚀刻去除，并且通过用层8，膜7和层6作为掩模的干蚀刻以高精度积极地去除金属膜2 。

4. 发明专利

JPS5710234A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5710234A
公开(公告)日：1982-01-19
申请号：JP8484380
申请日：1980-06-19
申请人： MITSUBISHI ELECTRIC CORP
发明人： SHIBAYAMA ISAO , HARADA HIROJI , OOHAYASHI YOSHIKAZU , MASUKO YOUJI , NISHIOKA KIYUUSAKU
IPC分类号： H01L21/027 , G03F7/20 , H01L21/28 , H01L21/30 , H01L21/3205
摘要： PURPOSE:To form an extremely small pattern formed of an Mo film by forming the Mo film on a substrate on which a pattern is provided, selectively injecting oxygen ions to the film, raising the temperature with an energy beam and then removing it. CONSTITUTION:An Mo film 2 is covered on the overall surface of a substrate 1 in the step of forming a mask pattern on the semiconductor substrate 1 so as to form, for example, a diffused region or the like. Then, oxygen ions are injected on the prescribed position of the film 2, and the prescribed position is converted into an oxidized Mo film 3. Subsequently, a laser light is emitted to the film 3, the film 3 is raised an its temperature to 500 deg.C to allow it to sublimate, and the film 3 is thus removed. The influence to the device can be reduced by performing the removing step in vacuum. In this manner, the diffusing mask pattern made of the film 2 and having an opening 4 can be produced without sidewise etching step precisely.

5. 发明专利

JPS56158482A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS56158482A
公开(公告)日：1981-12-07
申请号：JP6430480
申请日：1980-05-12
申请人： MITSUBISHI ELECTRIC CORP
发明人： TSUBOUCHI NATSUO , OOHAYASHI YOSHIKAZU
IPC分类号： H01L21/28 , H01L29/78
摘要： PURPOSE:To reduce the diffused area and to obtain high integration, by providing the first conductive layer which is to become a contact electrode on the region wherein a diffused layer of an FET is formed, then, providing a gate electrodes which is formed so as to cover the gap in the first conductive layer by a gate film and the second conductive layer by self-alignment. CONSTITUTION:The surface of an active region 13 of a substrate 11 which is separated by an oxide film 12 is exposed. For example, a poly Si layer 14 is provided so that it is extended from source and drain regions 19 and 20 to the oxide layer 12. After the oxidizing process, a poly Si gate 17 is formed so as to cover the gap part (corresponding to a gate length 15) of the poly Si layer 14 via a gate film 16a. Then, the processes of the formation of the source and drain diffused layers 19 and 20, the deposition of an insulating layer 21, the formation of an opening part 22, and the formation of wiring layers 23 are performed. In this constitution, since the aligning margin between the patterns can be reduced and the area of the diffused region can be reduced, the highly integrated FET can be obtained. The amount of injection of the minority carriers into the diffused layers is reduced and the erroneous operation of the circuit can be prevented.

6. 发明专利

JPS563679A FORMATION OF METALLIC PATTERN 失效
公开(公告)号：JPS563679A
公开(公告)日：1981-01-14
申请号：JP7989479
申请日：1979-06-22
申请人： MITSUBISHI ELECTRIC CORP
发明人： TSUBOUCHI NATSUO , HARADA KOUJI , ABE HARUHIKO , YONEDA MASAHIRO , OOHAYASHI YOSHIKAZU
IPC分类号： C23F4/00 , C23F1/00 , H01L21/302 , H01L21/3065 , H01L27/00
摘要： PURPOSE:To form a micro-pattern, by etching metal such as aluminum by using metallic oxide such as aluminum oxide as a mask. CONSTITUTION:On a substrate 1, on which a wiring pattern is made, is formed metallic material (aluminum) 2 which constitutes the wiring. Then a glass mask is placed on the substrate in such a way that photosensitive resin 3 is left on the range to be etched, and the substrate is exposed and developed. Subsequently, aluminum oxide coating 4 is formed on the surface of the exposed aluminum 2 by using the photosensitive resin 3 as a mask by oxygen-ion implantation etc. After that, the photosensitive resin 3 is removed, and aluminum 2 is removed by dry etching, the aluminum oxide coating 4 being removed separately. The etching is achieved in plasmatic gas of CCl4 at a pressure of about 0.75 Torr by applying high frequency wave of 13.5MHz.

7. 发明专利

JPS6124467B2 JPS6124467B2 - 失效
公开(公告)号：JPS6124467B2
公开(公告)日：1986-06-11
申请号：JP4912681
申请日：1981-03-30
申请人： Mitsubishi Electric Corp
发明人： KOTANI HIDEO , MIZUGUCHI KAZUO , OOHAYASHI YOSHIKAZU , DENDA MASAHIKO , SATO SHINICHI
IPC分类号： C23C16/50 , C23C16/509 , H01L21/285
CPC分类号： C23C16/5096

8. 发明专利

JPS594120A Manufacture of integrated circuit 失效
标题翻译：集成电路的制造
公开(公告)号：JPS594120A
公开(公告)日：1984-01-10
申请号：JP11503282
申请日：1982-06-30
申请人： Mitsubishi Electric Corp
发明人： NAKAO YOSHIHARU , YONEDA MASAHIRO , NAGATOMO MASAO , OOHAYASHI YOSHIKAZU , SATOU SHINICHI
IPC分类号： H01L29/78 , H01L21/28 , H01L21/306
CPC分类号： H01L21/28
摘要： PURPOSE:To improve the degree of integration of an integrated circuit by a method wherein the gate and the wiring part of said IC is covered by the material having the blocking action against the etching to be performed on the insulated layer such as a silicon nitride film. CONSTITUTION:The upper part of a gate 6 is covered by superimposed layer oxide film 7 and a silicon nitride film 8. As a result, the generation of short- circuit between said gate 6 and the polysilicon wiring 6a corresponding to the conventional aluminum wiring can be eliminated.
摘要翻译：目的：通过一种方法提高集成电路的集成度，其中所述IC的栅极和布线部分被对绝缘层（例如氮化硅膜）进行蚀刻的具有阻挡作用的材料覆盖。构成：栅极6的上部被叠加的氧化膜7和氮化硅膜8覆盖。结果，与常规铝布线对应的所述栅极6和多晶硅布线6a之间的短路产生可以被淘汰。

9. 发明专利

JPS586681A SEMICONDUCTOR IMAGE PICKUP DEVICE 失效
公开(公告)号：JPS586681A
公开(公告)日：1983-01-14
申请号：JP10493681
申请日：1981-07-02
申请人： MITSUBISHI ELECTRIC CORP
发明人： WAKAMIYA WATARU , OOHAYASHI YOSHIKAZU
IPC分类号： H01L27/146 , H01L27/148 , H04N5/335 , H04N5/359
摘要： PURPOSE:To prevent blooming securely by providing a crystal film, applied with a DC bias voltage, over a photodetection part, and effectively stopping the generation of excessive carriers due to incident light. CONSTITUTION:Incident light L through a transparent conductive film 11 generates carriers at the junction part between a P type semiconductor substrate 1 and an N diffused layer 2. Those carriers are applied with a reverse bias voltage from a DC power source 9 to store electrons in the N diffused layer 2 and positive holes in the substrate 1 respectively. As a result, the potential difference between the substrate 1 and layer 2 is decreased gradually according to the incidence of the light. At this time, the potential difference between a liquid- crystal film 10 and the layer 2 increases gradually to the contrary and when the difference exceeds some threshold value, liquid crystal molecules in the film 10 starts random motion through the migration of ions in the liquid crystal, and consequently the incident light L is interrupted, thereby preventing the further generation of carriers.

10. 发明专利

JPS57134553A CHEMICAL VAPOR PHASE GROWING METHOD 失效
公开(公告)号：JPS57134553A
公开(公告)日：1982-08-19
申请号：JP2035681
申请日：1981-02-14
申请人： MITSUBISHI ELECTRIC CORP
发明人： DENDA MASAHIKO , OOHAYASHI YOSHIKAZU , SATOU SHINICHI , KOTANI HIDEO , MIZUGUCHI KAZUO
IPC分类号： C23C16/50 , C23C16/44 , C23C16/509 , H01L21/205 , H01L21/31
摘要： PURPOSE:To prevent the thickness of a formed film of a reaction product from being made ununiform in the manufacture of a semiconductor device by a chemical vapor phase growing method, by simultaneously introducing an etching gas into a part of an apparatus. CONSTITUTION:An upper electrode 3 and a lower electrode 4 are arranged in a reaction chamber 2 formed with a case 1 made of quartz, and the interior of the chamber 2 is kept at prescribed reduded pressure and temp. A high frequency voltage is applied to the electrodes 3, 4 from a power source 5, and gaseous SiH4 or SiCl2H2 and gseous NH3 or N2 are fed from an inlet 6 and converted into plasma by discharge to form an SiN film on a substrate 11 on the electrode 4. At this time, gaseous CF4 mixed optionally with gaseous O2 is simultaneously introduced from an inlet 8 as an etching gas, passed by the underside of the electrode 3, and exhausted from an outlet 9. The deposition of a reaction product on the underside of the electrode 3 is prevented by the etching gas. Accordingly the product does not make the thickness of the SiN film on the substrate 11 ununiform by dropping.

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