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1. 发明申请

US20120075218A1 TOUCH PANEL AND TOUCH DISPLAY DEVICE USING THE SAME 审中-公开
标题翻译：触摸面板和触摸显示设备使用它
公开(公告)号：US20120075218A1
公开(公告)日：2012-03-29
申请号：US13238255
申请日：2011-09-21
申请人： MING-CHUAN LIN , Tien-Nan Wang , Ying-Chi Wang , Yung-Chang Lin , Lin Lin , Wen-Hung Wang , Pei-Fang Tsai , Shyh-Jeng Chen
发明人： MING-CHUAN LIN , Tien-Nan Wang , Ying-Chi Wang , Yung-Chang Lin , Lin Lin , Wen-Hung Wang , Pei-Fang Tsai , Shyh-Jeng Chen
IPC分类号： G06F3/041
CPC分类号： G06F3/044 , G06F3/0418 , G06F2203/04107
摘要： A touch panel comprising a substrate, a touch element, a first grounding electrode, an insulation layer and a second grounding electrode is disclosed. The touch element is disposed on a first surface of the substrate. The first grounding electrode is disposed on the first surface to surround the touch element. The insulation layer is disposed on the first surface to cover the touch element and the first grounding electrode. The second grounding electrode is disposed on the first insulation layer or on a second surface of the substrate opposite to the first surface. Therefore, the ESD can be conducted to the grounding end G of the circuit component through the enclosed first grounding electrode, and the signal interference between the touch panel and display can be shielded by the second grounding electrode to enhance anti-ESD and anti-noise abilities of the touch panel.
摘要翻译：公开了一种包括基板，触摸元件，第一接地电极，绝缘层和第二接地电极的触摸面板。触摸元件设置在基板的第一表面上。第一接地电极设置在第一表面上以围绕触摸元件。绝缘层设置在第一表面上以覆盖触摸元件和第一接地电极。第二接地电极设置在与第一表面相对的第一绝缘层或第二表面上。因此，ESD可以通过封闭的第一接地电极传导到电路部件的接地端G，并且可以通过第二接地电极屏蔽触摸面板和显示器之间的信号干扰，以增强抗ESD和抗噪声触摸屏的能力。

2. 发明申请

US20110157082A1 Matrix Resistive Touch Panel and Design Method Thereof 审中-公开
标题翻译：矩阵电阻式触摸屏及其设计方法
公开(公告)号：US20110157082A1
公开(公告)日：2011-06-30
申请号：US12978789
申请日：2010-12-27
申请人： Yung-Chang Lin , Ming-Chuan Lin , Lin Lin , Chih-Chiang Lin
发明人： Yung-Chang Lin , Ming-Chuan Lin , Lin Lin , Chih-Chiang Lin
IPC分类号： G06F3/045
CPC分类号： G06F3/045
摘要： A matrix resistive touch panel including a plurality of first sensing electrodes, a plurality of second sensing electrodes, a control circuit and a compensating circuit is provided. Each first sensing electrode has a first end and a second end. Each second sensing electrode has a third end and a fourth end. The compensating circuit is electrically connected to the control circuit, the first and the second ends of the first sensing electrodes, and the third and the fourth ends of the second sensing electrodes. The compensating circuit is used for equating a plurality of first impedances between the first ends and the control circuit, equating a plurality of second impedances between the second ends and the control circuit, equating a plurality of third impedances between the third ends and the control circuit, and equating a plurality of fourth impedances between the fourth ends and the control circuit.
摘要翻译：提供了包括多个第一感测电极，多个第二感测电极，控制电路和补偿电路的矩阵电阻式触摸面板。每个第一感测电极具有第一端和第二端。每个第二感测电极具有第三端和第四端。补偿电路电连接到控制电路，第一感测电极的第一端和第二端以及第二感测电极的第三端和第四端。补偿电路用于将第一端和控制电路之间的多个第一阻抗相等，将第二端与控制电路之间的多个第二阻抗相等，将第三端之间的多个第三阻抗与控制电路并且将第四端之间的多个第四阻抗与控制电路相等。

3. 发明授权

US09022392B2 Chuck and semiconductor process using the same 有权
标题翻译：夹头和半导体工艺使用相同
公开(公告)号：US09022392B2
公开(公告)日：2015-05-05
申请号：US13600231
申请日：2012-08-31
申请人： Chung-Sung Jang , Ming-Tse Lin , Yung-Chang Lin
发明人： Chung-Sung Jang , Ming-Tse Lin , Yung-Chang Lin
IPC分类号： H01L21/683
CPC分类号： H01L22/20 , G03F7/20 , G03F7/707 , G03F7/70783 , H01L21/6836 , H01L21/6838 , H01L22/12 , Y10T29/49764 , Y10T279/11
摘要： An apparatus of semiconductor process including a chuck and a vacuum source is provided. The chuck has a plurality of holes for holding a semiconductor substrate, and the vacuum source is used for providing vacuum suction through the holes to make the semiconductor substrate be subjected to varied suction intensities according to a warpage level thereof.
摘要翻译：提供一种包括卡盘和真空源的半导体工艺装置。卡盘具有用于保持半导体衬底的多个孔，并且真空源用于通过孔提供真空吸力，以使半导体衬底根据其翘曲程度受到各种抽吸强度。

4. 发明授权

US08377829B2 Method of manufacturing a capacitor deep trench and of etching a deep trench opening 有权
标题翻译：制造电容器深沟槽并蚀刻深沟槽开口的方法
公开(公告)号：US08377829B2
公开(公告)日：2013-02-19
申请号：US11871166
申请日：2007-10-12
申请人： Ta-Chuan Yeh , Ni-Min Chung , Kao-Su Huang , Yung-Chang Lin , Ruey-Chyr Lee , Chien-Kuo Wang
发明人： Ta-Chuan Yeh , Ni-Min Chung , Kao-Su Huang , Yung-Chang Lin , Ruey-Chyr Lee , Chien-Kuo Wang
IPC分类号： H01L21/302 , H01L21/461 , B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00
CPC分类号： H01L27/1087 , H01L21/76205
摘要： A substrate is provided having an oxide layer, a first nitride-silicon, a STI, and a second nitride-silicon. A pattern poly-silicon layer on the second nitride-silicon layer is etched to form a deep trench opening. Etching the pattern poly-silicon layer also deepens the deep trench opening. Then, a conductive layer is filled in the deep trench opening.
摘要翻译：提供了具有氧化物层，第一氮化硅 - 硅，STI和第二氮化硅 - 硅的衬底。蚀刻第二氮化硅 - 硅层上的图案多晶硅层以形成深沟槽开口。蚀刻图案多晶硅层也加深了深沟槽开口。然后，在深沟槽开口中填充导电层。

5. 发明授权

US08227890B2 Method of forming an electrical fuse and a metal gate transistor and the related electrical fuse 有权
标题翻译：形成电熔丝和金属栅晶体管及相关电熔丝的方法
公开(公告)号：US08227890B2
公开(公告)日：2012-07-24
申请号：US12641322
申请日：2009-12-18
申请人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong
发明人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L21/823807 , H01L21/823814 , H01L27/0629 , H01L27/112 , H01L27/11206 , H01L29/7843 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.
摘要翻译：本发明提供了一种将电熔丝工艺集成到高k /金属栅极工艺中的方法。该方法同时形成晶体管的虚拟栅极堆叠和电子熔丝的虚拟栅极堆叠; 并且同时去除晶体管区域中的虚拟栅极堆叠的多晶硅和电子熔丝区域中的伪栅极堆叠的多晶硅。此后，去除设置在电熔丝区域的开口中的功函数金属层; 并且晶体管区域中的开口和具有金属导电结构的e熔丝区域中的开口被填充以形成晶体管的电熔丝和金属栅极。

6. 发明申请

US20120001813A1 USB Antenna with a Bottle Opener 审中-公开
标题翻译： USB天线与开瓶器
公开(公告)号：US20120001813A1
公开(公告)日：2012-01-05
申请号：US12883403
申请日：2010-09-16
申请人： Yung-Chang Lin
发明人： Yung-Chang Lin
IPC分类号： H01Q1/00 , B67B7/44
CPC分类号： B67B7/16 , H01Q1/2275 , H01Q1/44
摘要： The present invention discloses an USB antenna device with a bottle opener, which comprises a main body being a casing; a connector being mounted on an end of the main body; a bottle opener being concavely disposed on a side of the main body; and a wireless antenna for transmitting and receiving wireless signals or microwaves. In the present invention, the available limited space in the USB antenna device can be used efficiently because the wireless antenna occupying a certain area in the traditional USB antenna device is disposed corresponding to a bottle opener structure. That is, the USB antenna device of the present invention not only is easy to carry, but can also provide a function of opening the bottle.
摘要翻译：本发明公开了一种具有开瓶器的USB天线装置，其包括：主体，其为壳体; 连接器，其安装在所述主体的端部上; 开瓶器凹入地设置在主体的一侧; 以及用于发送和接收无线信号或微波的无线天线。在本发明中，由于在传统的USB天线装置中占据一定区域的无线天线对应于开瓶器结构而设置在USB天线装置中的有限空间可以有效地使用。也就是说，本发明的USB天线装置不仅容易携带，而且还可以提供打开瓶子的功能。

7. 发明授权

US08071437B2 Method of fabricating efuse, resistor and transistor 有权
标题翻译：制造efuse，电阻和晶体管的方法
公开(公告)号：US08071437B2
公开(公告)日：2011-12-06
申请号：US12621518
申请日：2009-11-19
申请人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong , Ching-Hsiang Tseng
发明人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong , Ching-Hsiang Tseng
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823842 , H01L27/0629 , H01L29/7848
摘要： A method of fabricating an efuse, a resistor and a transistor includes the following steps: A substrate is provided. Then, a gate, a resistor and an efuse are formed on the substrate, wherein the gate, the resistor and the efuse together include a first dielectric layer, a polysilicon layer and a hard mask. Later, a source/drain doping region is formed in the substrate besides the gate. After that, the hard mask in the resistor and the efuse is removed. Subsequently, a salicide process is performed to form a silicide layer on the source/drain doping region, the resistor, and the efuse. Then, a planarized second dielectric layer is formed on the substrate and the polysilicon in the gate is exposed. Later, the polysilicon in the gate is removed to form a recess. Finally a metal layer is formed to fill up the recess.
摘要翻译：一种制造efuse，电阻器和晶体管的方法包括以下步骤：提供衬底。然后，在衬底上形成栅极，电阻器和efuse，其中栅极，电阻器和efuse一起包括第一介电层，多晶硅层和硬掩模。之后，在栅极之外的基板中形成源极/漏极掺杂区域。之后，去除电阻和efuse中的硬掩模。随后，执行自对准硅化处理以在源/漏掺杂区域，电阻器和efuse上形成硅化物层。然后，在基板上形成平坦化的第二介质层，露出栅极中的多晶硅。之后，去除栅极中的多晶硅以形成凹陷。最后，形成一个金属层以填充凹槽。

8. 发明申请

US20110147853A1 Method of Forming an Electrical Fuse and a Metal Gate Transistor and the Related Electrical Fuse 有权
标题翻译：形成电保险丝和金属栅晶体管的方法及相关电熔丝
公开(公告)号：US20110147853A1
公开(公告)日：2011-06-23
申请号：US12641322
申请日：2009-12-18
申请人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong
发明人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong
IPC分类号： H01L27/06 , H01L21/768 , H01L21/8234 , H01L23/525
CPC分类号： H01L23/5256 , H01L21/823807 , H01L21/823814 , H01L27/0629 , H01L27/112 , H01L27/11206 , H01L29/7843 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.
摘要翻译：本发明提供了一种将电熔丝工艺集成到高k /金属栅极工艺中的方法。该方法同时形成晶体管的虚拟栅极堆叠和电子熔丝的虚拟栅极堆叠; 并且同时去除晶体管区域中的虚拟栅极堆叠的多晶硅和电子熔丝区域中的伪栅极堆叠的多晶硅。此后，去除设置在电熔丝区域的开口中的功函数金属层; 并且晶体管区域中的开口和具有金属导电结构的e熔丝区域中的开口被填充以形成晶体管的电熔丝和金属栅极。

9. 发明授权

US07351634B2 Trench-capacitor DRAM device and manufacture method thereof 有权
标题翻译：沟槽电容器DRAM器件及其制造方法
公开(公告)号：US07351634B2
公开(公告)日：2008-04-01
申请号：US11420222
申请日：2006-05-25
申请人： Yi-Nan Su , Yung-Chang Lin , Jun-Chi Huang
发明人： Yi-Nan Su , Yung-Chang Lin , Jun-Chi Huang
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087
摘要： A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adjacent trenches are etched into the first, second pad layers, and the semiconductor substrate. The second pad layer and a portion of the STI structure between the two trenches are etched to form a ridge. A liner is formed on interior surface of the trenches. A first polysilicon layer is formed on the liner. A capacitor dielectric layer is formed on the first polysilicon layer. The two adjacent trenches are filled with a second polysilicon layer. The second polysilicon layer is then etched until the capacitor dielectric layer is exposed. The fabrication process is easy to integrate to SoC chip.
摘要翻译：公开了一种制造沟槽电容器的方法。提供具有第一焊盘层的衬底。 STI结构嵌入到第一焊盘层和衬底中。在第一焊盘层和STI结构上沉积第二焊盘层。两个相邻的沟槽被蚀刻到第一，第二焊盘层和半导体衬底中。蚀刻第二焊盘层和两个沟槽之间的STI结构的一部分以形成脊。衬套形成在沟槽的内表面上。在衬套上形成第一多晶硅层。在第一多晶硅层上形成电容器电介质层。两个相邻的沟槽被填充有第二多晶硅层。然后蚀刻第二多晶硅层直到暴露电容器介电层。制造工艺易于集成到SoC芯片。

10. 发明申请

US20070238244A1 TRENCH-CAPACITOR DRAM DEVICE AND MANUFACTURE METHOD THEREOF 有权
标题翻译： TRENCH-CAPACITOR DRAM器件及其制造方法
公开(公告)号：US20070238244A1
公开(公告)日：2007-10-11
申请号：US11279254
申请日：2006-04-11
申请人： Yung-Chang Lin , Sun-Chieh Chien , Chien-Li Kuo , Ruey-Chyr Lee
发明人： Yung-Chang Lin , Sun-Chieh Chien , Chien-Li Kuo , Ruey-Chyr Lee
IPC分类号： H01L21/8242 , H01L21/336 , H01L29/94 , H01L21/20
CPC分类号： H01L29/945 , H01L27/1087 , H01L29/66181
摘要： A trench capacitor structure includes a semiconductor substrate comprising thereon a STI structure. A capacitor deep trench is etched into the semiconductor substrate. Collar oxide layer is disposed on inner surface of the capacitor deep trench. A first doped polysilicon layer is disposed on the collar oxide layer and on the exposed bottom of the capacitor deep trench. A capacitor dielectric layer is formed on the first doped polysilicon layer. A second doped polysilicon layer is formed on the capacitor dielectric layer. A deep ion well is formed in the semiconductor substrate, wherein the deep ion well is electrically connected with the first doped polysilicon layer through the bottom of the capacitor deep trench. A passing gate insulation (PGI) layer is formed on the second doped polysilicon layer and on the STI structure.
摘要翻译：沟槽电容器结构包括其上包括STI结构的半导体衬底。电容器深沟槽被蚀刻到半导体衬底中。环状氧化物层设置在电容器深沟槽的内表面上。第一掺杂多晶硅层设置在轴环氧化物层和电容器深沟槽的暴露的底部上。在第一掺杂多晶硅层上形成电容器电介质层。第二掺杂多晶硅层形成在电容器介电层上。在半导体衬底中形成深离子阱，其中深离子阱通过电容器深沟槽的底部与第一掺杂多晶硅层电连接。在第二掺杂多晶硅层和STI结构上形成通过栅极绝缘（PGI）层。

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