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1. 发明授权

US08071437B2 Method of fabricating efuse, resistor and transistor 有权
标题翻译：制造efuse，电阻和晶体管的方法
公开(公告)号：US08071437B2
公开(公告)日：2011-12-06
申请号：US12621518
申请日：2009-11-19
申请人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong , Ching-Hsiang Tseng
发明人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong , Ching-Hsiang Tseng
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823842 , H01L27/0629 , H01L29/7848
摘要： A method of fabricating an efuse, a resistor and a transistor includes the following steps: A substrate is provided. Then, a gate, a resistor and an efuse are formed on the substrate, wherein the gate, the resistor and the efuse together include a first dielectric layer, a polysilicon layer and a hard mask. Later, a source/drain doping region is formed in the substrate besides the gate. After that, the hard mask in the resistor and the efuse is removed. Subsequently, a salicide process is performed to form a silicide layer on the source/drain doping region, the resistor, and the efuse. Then, a planarized second dielectric layer is formed on the substrate and the polysilicon in the gate is exposed. Later, the polysilicon in the gate is removed to form a recess. Finally a metal layer is formed to fill up the recess.
摘要翻译：一种制造efuse，电阻器和晶体管的方法包括以下步骤：提供衬底。然后，在衬底上形成栅极，电阻器和efuse，其中栅极，电阻器和efuse一起包括第一介电层，多晶硅层和硬掩模。之后，在栅极之外的基板中形成源极/漏极掺杂区域。之后，去除电阻和efuse中的硬掩模。随后，执行自对准硅化处理以在源/漏掺杂区域，电阻器和efuse上形成硅化物层。然后，在基板上形成平坦化的第二介质层，露出栅极中的多晶硅。之后，去除栅极中的多晶硅以形成凹陷。最后，形成一个金属层以填充凹槽。

2. 发明申请

US20110117710A1 METHOD OF FABRICATING EFUSE, RESISTOR AND TRANSISTOR 有权
标题翻译：制造EFUSE，电阻和晶体管的方法
公开(公告)号：US20110117710A1
公开(公告)日：2011-05-19
申请号：US12621518
申请日：2009-11-19
申请人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong , Ching-Hsiang Tseng
发明人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong , Ching-Hsiang Tseng
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823842 , H01L27/0629 , H01L29/7848
摘要： A method of fabricating an efuse, a resistor and a transistor includes the following steps: A substrate is provided. Then, a gate, a resistor and an efuse are formed on the substrate, wherein the gate, the resistor and the efuse together include a first dielectric layer, a polysilicon layer and a hard mask. Later, a source/drain doping region is formed in the substrate besides the gate. After that, the hard mask in the resistor and the efuse is removed. Subsequently, a salicide process is performed to form a silicide layer on the source/drain doping region, the resistor, and the efuse. Then, a planarized second dielectric layer is formed on the substrate and the polysilicon in the gate is exposed. Later, the polysilicon in the gate is removed to form a recess. Finally a metal layer is formed to fill up the recess.
摘要翻译：一种制造efuse，电阻器和晶体管的方法包括以下步骤：提供衬底。然后，在衬底上形成栅极，电阻器和efuse，其中栅极，电阻器和efuse一起包括第一介电层，多晶硅层和硬掩模。之后，在栅极之外的基板中形成源极/漏极掺杂区域。之后，去除电阻和efuse中的硬掩模。随后，执行自对准硅化处理以在源/漏掺杂区域，电阻器和efuse上形成硅化物层。然后，在基板上形成平坦化的第二介质层，露出栅极中的多晶硅。之后，去除栅极中的多晶硅以形成凹陷。最后，形成一个金属层以填充凹槽。

3. 发明授权

US08227890B2 Method of forming an electrical fuse and a metal gate transistor and the related electrical fuse 有权
标题翻译：形成电熔丝和金属栅晶体管及相关电熔丝的方法
公开(公告)号：US08227890B2
公开(公告)日：2012-07-24
申请号：US12641322
申请日：2009-12-18
申请人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong
发明人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L21/823807 , H01L21/823814 , H01L27/0629 , H01L27/112 , H01L27/11206 , H01L29/7843 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.
摘要翻译：本发明提供了一种将电熔丝工艺集成到高k /金属栅极工艺中的方法。该方法同时形成晶体管的虚拟栅极堆叠和电子熔丝的虚拟栅极堆叠; 并且同时去除晶体管区域中的虚拟栅极堆叠的多晶硅和电子熔丝区域中的伪栅极堆叠的多晶硅。此后，去除设置在电熔丝区域的开口中的功函数金属层; 并且晶体管区域中的开口和具有金属导电结构的e熔丝区域中的开口被填充以形成晶体管的电熔丝和金属栅极。

4. 发明申请

US20110147853A1 Method of Forming an Electrical Fuse and a Metal Gate Transistor and the Related Electrical Fuse 有权
标题翻译：形成电保险丝和金属栅晶体管的方法及相关电熔丝
公开(公告)号：US20110147853A1
公开(公告)日：2011-06-23
申请号：US12641322
申请日：2009-12-18
申请人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong
发明人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong
IPC分类号： H01L27/06 , H01L21/768 , H01L21/8234 , H01L23/525
CPC分类号： H01L23/5256 , H01L21/823807 , H01L21/823814 , H01L27/0629 , H01L27/112 , H01L27/11206 , H01L29/7843 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.
摘要翻译：本发明提供了一种将电熔丝工艺集成到高k /金属栅极工艺中的方法。该方法同时形成晶体管的虚拟栅极堆叠和电子熔丝的虚拟栅极堆叠; 并且同时去除晶体管区域中的虚拟栅极堆叠的多晶硅和电子熔丝区域中的伪栅极堆叠的多晶硅。此后，去除设置在电熔丝区域的开口中的功函数金属层; 并且晶体管区域中的开口和具有金属导电结构的e熔丝区域中的开口被填充以形成晶体管的电熔丝和金属栅极。

5. 发明授权

US08399318B2 Method of forming an electrical fuse and a metal gate transistor and the related electrical fuse 有权
标题翻译：形成电熔丝和金属栅晶体管及相关电熔丝的方法
公开(公告)号：US08399318B2
公开(公告)日：2013-03-19
申请号：US13469069
申请日：2012-05-10
申请人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong
发明人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong
IPC分类号： H01L21/8238
CPC分类号： H01L23/5256 , H01L21/823807 , H01L21/823814 , H01L27/0629 , H01L27/112 , H01L27/11206 , H01L29/7843 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.
摘要翻译：本发明提供了一种将电熔丝工艺集成到高k /金属栅极工艺中的方法。该方法同时形成晶体管的虚拟栅极堆叠和电子熔丝的虚拟栅极堆叠; 并且同时去除晶体管区域中的虚拟栅极堆叠的多晶硅和电子熔丝区域中的伪栅极堆叠的多晶硅。此后，去除设置在电熔丝区域的开口中的功函数金属层; 并且晶体管区域中的开口和具有金属导电结构的e熔丝区域中的开口被填充以形成晶体管的电熔丝和金属栅极。

6. 发明申请

US20120225524A1 METHOD OF FORMING AN ELECTRICAL FUSE AND A METAL GATE TRANSISTOR AND THE RELATED ELECTRICAL FUSE 有权
公开(公告)号：US20120225524A1
公开(公告)日：2012-09-06
申请号：US13469069
申请日：2012-05-10
申请人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong
发明人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong
IPC分类号： H01L21/8232
CPC分类号： H01L23/5256 , H01L21/823807 , H01L21/823814 , H01L27/0629 , H01L27/112 , H01L27/11206 , H01L29/7843 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.

7. 发明授权

US08026573B2 Electrical fuse structure 有权
标题翻译：电熔丝结构
公开(公告)号：US08026573B2
公开(公告)日：2011-09-27
申请号：US12335510
申请日：2008-12-15
申请人： Chien-Li Kuo , Yung-Chang Lin , Kuei-Sheng Wu , San-Fu Lin
发明人： Chien-Li Kuo , Yung-Chang Lin , Kuei-Sheng Wu , San-Fu Lin
IPC分类号： H01L23/52
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse structure is disclosed. The electrical fuse structure includes a fuse element disposed on surface of a semiconductor substrate, a cathode electrically connected to one end of the fuse element, and an anode electrically connected to another end of the fuse element. Specifically, a compressive stress layer is disposed on at least a portion of the fuse element.
摘要翻译：公开了电熔丝结构。电熔丝结构包括设置在半导体衬底的表面上的熔丝元件，与熔丝元件的一端电连接的阴极以及与熔丝元件的另一端电连接的阳极。具体而言，压电应力层设置在熔丝元件的至少一部分上。

8. 发明授权

US08035191B2 Contact efuse structure 有权
标题翻译：联系efuse结构
公开(公告)号：US08035191B2
公开(公告)日：2011-10-11
申请号：US12326106
申请日：2008-12-02
申请人： Yung-Chang Lin , Kuei-Sheng Wu , San-Fu Lin , Hui-Shen Shih
发明人： Yung-Chang Lin , Kuei-Sheng Wu , San-Fu Lin , Hui-Shen Shih
IPC分类号： H01L29/00
CPC分类号： H01L27/112 , H01L23/5256 , H01L27/11206 , H01L29/665 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A contact efuse structure includes a silicon layer and a contact contacting the silicon layer with one end. When a voltage is applied to the contact, a void is formed at the end of the contact, and thus the contact is open. Such structure may be utilized in an efuse device or a read only memory. A method of making a contact efuse device and a method of making a read only memory are also disclosed.
摘要翻译：接触式熔点结构包括硅层和接触硅层与一端的接触。当对触点施加电压时，在接触端部形成空隙，因此触点断开。这种结构可以用在efuse设备或只读存储器中。还公开了制造接触式充电装置的方法和制造只读存储器的方法。

9. 发明授权

US08035097B2 Phase change memory 有权
标题翻译：相变记忆
公开(公告)号：US08035097B2
公开(公告)日：2011-10-11
申请号：US12325801
申请日：2008-12-01
申请人： Chien-Li Kuo , Yung-Chang Lin , Kuei-Sheng Wu , Chien-Hsien Chen
发明人： Chien-Li Kuo , Yung-Chang Lin , Kuei-Sheng Wu , Chien-Hsien Chen
IPC分类号： H01L29/06 , H01L47/00
CPC分类号： H01L45/06 , G11C5/063 , G11C13/0004 , H01L27/2445 , H01L27/2463 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148
摘要： A phase change memory is provided, which includes a semiconductor substrate having a first conductive type, buried word lines having a second conductive type, doped semiconductor layers having the first conductive type, memory cells, metal silicide layers, and bit lines. The buried word lines are disposed in the semiconductor substrate. Each buried word line includes a line-shaped main portion extended along a first direction and protrusion portions. Each protrusion portion is connected to one long side of the line-shaped main portion. Each doped semiconductor layer is disposed on one protrusion portion. Each memory cell includes a phase change material layer and is disposed on and electrically connected to one of the doped semiconductor layers. Each metal silicide layer is disposed on one of the line-shaped main portions. Each bit line is connected to memory cells disposed on the word lines in a second direction substantially perpendicular to the first direction.
摘要翻译：提供了一种相变存储器，其包括具有第一导电类型的半导体衬底，具有第二导电类型的埋入字线，具有第一导电类型的掺杂半导体层，存储单元，金属硅化物层和位线。掩埋字线设置在半导体衬底中。每个掩埋字线包括沿着第一方向延伸的线状主体部分和突出部分。每个突起部分连接到线状主体部分的一个长边。每个掺杂半导体层设置在一个突出部分上。每个存储单元包括相变材料层，并且被布置在一个掺杂半导体层上并与其电连接。每个金属硅化物层设置在一个线状主要部分上。每个位线以基本上垂直于第一方向的第二方向连接到设置在字线上的存储单元。

10. 发明授权

US07888668B2 Phase change memory 有权
标题翻译：相变记忆
公开(公告)号：US07888668B2
公开(公告)日：2011-02-15
申请号：US12174642
申请日：2008-07-17
申请人： Chien-Li Kuo , Kuei-Sheng Wu , Yung-Chang Lin
发明人： Chien-Li Kuo , Kuei-Sheng Wu , Yung-Chang Lin
IPC分类号： H01L47/00 , H01L21/82 , G11C11/00
CPC分类号： H01L45/144 , G11C13/0004 , H01L27/2436 , H01L27/2472 , H01L27/249 , H01L45/06 , H01L45/122 , H01L45/1226 , H01L45/126 , H01L45/1666
摘要： A phase change memory and the method for manufacturing the same are disclosed. The phase change memory includes a word line, a phase change element, a plurality of heating parts, and a plurality of bit lines. The phase change material layer is electrically connected to the word line and the heating parts. Each heating part is electrically connected to a respective bit line.
摘要翻译：公开了一种相变存储器及其制造方法。相变存储器包括字线，相变元件，多个加热部件和多个位线。相变材料层电连接到字线和加热部件。每个加热部件电连接到相应的位线。

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