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1. 发明授权

US06613655B2 Method of fabricating system on chip device 失效
标题翻译：制造片上系统的方法
公开(公告)号：US06613655B2
公开(公告)日：2003-09-02
申请号：US10050258
申请日：2002-01-16
申请人： Sun-Chieh Chien , Chien-Li Kuo
发明人： Sun-Chieh Chien , Chien-Li Kuo
IPC分类号： H01L2122
CPC分类号： H01L27/0617 , H01L27/105 , H01L27/1052
摘要： A method of fabricating a system on a chip device. On a substrate having a memory cell region and a peripheral circuit region a gate oxide layer and a polysilicon layer are formed. The peripheral circuit region can further be divided into a logic device region and a hybrid circuit region. A dielectric layer is formed on the peripheral circuit region. A cap layer and a conductive layer are further formed on the polysilicon layer in the memory cell region and on the dielectric layer in the peripheral circuit region. Using the dielectric layer in the peripheral circuit region and the gate oxide layer in the memory cell region as etch stop, the cap layer and the conductive layer in the peripheral circuit region, and the cap layer, the conductive layer and the polysilicon layer are patterned. As a result, at least a gate and a top electrode are formed in the memory cell region and the hybrid circuit region, respectively. Using the gate oxide layer in the peripheral circuit region as an etch stop, the dielectric layer and the conductive layer in the peripheral circuit region are patterned to form a gate in the logic circuit region and the hybrid circuit region, respectively.
摘要翻译：一种在芯片器件上制造系统的方法。在具有存储单元区域和外围电路区域的基板上形成栅氧化层和多晶硅层。外围电路区域还可以分为逻辑器件区域和混合电路区域。在外围电路区域上形成介电层。在存储单元区域的多晶硅层和外围电路区域中的电介质层上还形成有盖层和导电层。使用外围电路区域中的电介质层和存储单元区域中的栅极氧化物层作为蚀刻停止层，外围电路区域中的覆盖层和导电层以及覆盖层，导电层和多晶硅层被图案化。结果，至少在存储单元区域和混合电路区域中分别形成栅极和顶部电极。使用外围电路区域中的栅极氧化层作为蚀刻停止层，对外围电路区域中的电介质层和导电层进行图案化，以分别在逻辑电路区域和混合电路区域中形成栅极。

2. 发明授权

US06468919B2 Method of making a local interconnect in an embedded memory 失效
公开(公告)号：US06468919B2
公开(公告)日：2002-10-22
申请号：US09764326
申请日：2001-01-19
申请人： Sun-Chieh Chien , Chien-Li Kuo
发明人： Sun-Chieh Chien , Chien-Li Kuo
IPC分类号： H01L2100
CPC分类号： H01L21/76897 , H01L21/76889 , H01L21/76895 , H01L27/105 , H01L27/1052
摘要： The present invention provides a method to make a local interconnect in an embedded memory. The method first involves defining both a memory array area and a periphery circuit area on the surface of a semiconductor wafer. Then, a plurality of gates and lightly doped drains (LDD) are separately formed in the memory array area and in the periphery circuit area. A silicon nitride layer and a dielectric layer are then formed, respectively, on the surface of the semiconductor wafer and on each gate. Next, a plurality of landing via holes and local interconnect holes are separately formed in the dielectric layer in the memory array area and in the periphery circuit area, followed by the filling of an electrical conducting layer in each hole to simultaneously form a landing via and local interconnect. Then, the dielectric layer and a portion of the silicon nitride layer in the periphery circuit area are removed to form a spacer on either side of each gate in the periphery circuit area. Finally, a silicide layer is formed on the top surface of the landing via in the memory array area, as well as on the surfaces of each gate and on the surface of the local interconnect in the periphery circuit area.

3. 发明授权

US06432768B1 Method of fabricating memory device and logic device on the same chip 有权
标题翻译：在同一芯片上制造存储器件和逻辑器件的方法
公开(公告)号：US06432768B1
公开(公告)日：2002-08-13
申请号：US09510970
申请日：2000-02-21
申请人： Sun-Chieh Chien , Der-Yuan Wu
发明人： Sun-Chieh Chien , Der-Yuan Wu
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L27/10873 , H01L29/665
摘要： A method of fabricating a memory device and a logic device on the same chip is described, wherein the memory device has a first gate on a first region of the chip, and wherein the logic device has a second gate with a sidewall on a second region of the chip. A conductive layer and a first suicide layer are sequentially formed over the first and the second regions of the chip. Over the first region of the chip, the first silicide layer and the conductive layer are patterned to form the first gate. Ions are first implanted into the first region of the chip, by using the first gate as a mask, to form a first doped region. A dielectric layer is formed to cap the first gate, the first doped region and the first region of the chip. The first silicide layer over the second region of the chip is removed. Over the second region of the chip, the conductive layer is patterned to form the second gate. Ions are second implanted into the second region of the chip, by using the second gate as a mask, to form a second doped region.
摘要翻译：描述了在同一芯片上制造存储器件和逻辑器件的方法，其中存储器件在芯片的第一区域上具有第一栅极，并且其中逻辑器件具有在第二区域上具有侧壁的第二栅极的芯片。在芯片的第一和第二区域上依次形成导电层和第一硅化物层。在芯片的第一区域上，第一硅化物层和导电层被图案化以形成第一栅极。通过使用第一栅极作为掩模，首先将离子注入到芯片的第一区域中，以形成第一掺杂区域。形成介电层，以覆盖芯片的第一栅极，第一掺杂区域和第一区域。去除芯片第二区域上的第一硅化物层。在芯片的第二区域上，对导电层进行图案化以形成第二栅极。通过使用第二栅极作为掩模，将第二注入到芯片的第二区域中，以形成第二掺杂区域。

4. 发明授权

US06368971B2 Method of manufacturing bottom electrode of capacitor 失效
标题翻译：制造电容器底电极的方法
公开(公告)号：US06368971B2
公开(公告)日：2002-04-09
申请号：US09348408
申请日：1999-07-07
申请人： Sun-Chieh Chien , Chien-Li Kuo , Wei-Wu Liao
发明人： Sun-Chieh Chien , Chien-Li Kuo , Wei-Wu Liao
IPC分类号： H01L21302
CPC分类号： H01L28/91 , H01L27/10814
摘要： A method of manufacturing a bottom electrode of a capacitor. A substrate has a contact pad formed thereon, a first dielectric layer is formed on the contact pad, and a node contact penetrates through the first dielectric layer and electrically couples to the contact pad. A second dielectric layer is formed on the first dielectric layer and the node contact. A third dielectric layer is formed on the second dielectric layer. A fourth dielectric layer is formed on the third dielectric layer. A trench is formed to penetrate through the fourth, the third and the second dielectric layer and to expose a surface of the node contact. A conductive layer is formed on the fourth dielectric layer and a sidewall and a bottom of the trench. A fifth dielectric layer is formed on the conductive layer, wherein the fifth dielectric layer fills the trench. A portion of the fifth dielectric layer and a portion of the conductive layer are removed until a surface of the fourth dielectric layer is exposed. The remaining fifth dielectric layer and the fourth dielectric layer are removed.
摘要翻译：一种制造电容器的底部电极的方法。衬底具有形成在其上的接触焊盘，在接触焊盘上形成第一电介质层，并且节点接触件穿过第一电介质层并电耦合到接触焊盘。在第一电介质层和节点接触件上形成第二电介质层。在第二电介质层上形成第三电介质层。在第三电介质层上形成第四电介质层。形成沟槽以穿透第四，第三和第二介电层并暴露节点接触的表面。在第四电介质层和沟槽的侧壁和底部上形成导电层。在导电层上形成第五电介质层，其中第五介电层填充沟槽。去除第五电介质层的一部分和导电层的一部分直到暴露第四电介质层的表面。去除剩余的第五电介质层和第四电介质层。

5. 发明授权

US6030867A Method of fabricating a Fin/HSG DRAM cell capacitor 失效
标题翻译：制造Fin / HSG DRAM单元电容器的方法
公开(公告)号：US6030867A
公开(公告)日：2000-02-29
申请号：US975708
申请日：1997-11-21
申请人： Sun-Chieh Chien , Jason Jenq , Der-Yuan Wu , Chia-Wen Liang
发明人： Sun-Chieh Chien , Jason Jenq , Der-Yuan Wu , Chia-Wen Liang
IPC分类号： H01L21/02 , H01L21/60 , H01L21/768 , H01L21/8242
CPC分类号： H01L24/11 , H01L27/10852 , H01L28/84 , H01L21/76895 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/04941 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/30105
摘要： The DRAM cell is formed by covering the cell's transfer FET with a conformal insulating layer. A self aligned contact etch removes a portion of the conformal insulating layer from above a first source/drain region of the FET and then a first polysilicon layer is deposited over the device. Etching defines a polysilicon pad from the first polysilicon layer with edges of the polysilicon pad disposed over the gate electrode and an adjacent wiring line. A thick, planarized second insulating layer is provided over the device, filling the volume defined by the locally cupped surface of the polysilicon pad. Etching is performed to remove a portion of the planarized insulating layer using the pad polysilicon layer as an etch stop for the process. A second, thick polysilicon layer is next provided to fill the cavity and the layer is patterned to laterally define the lower capacitor electrode. Hemispherical grained silicon (HSG-Si) is deposited on the surface of the patterned polysilicon layer and an etch back process is used to transfer the topology of the HSG-Si layer to the underlying polysilicon. Further processing provides a capacitor dielectric and an upper electrode.
摘要翻译：通过用保形绝缘层覆盖电池的转移FET来形成DRAM单元。自对准接触蚀刻从FET的第一源极/漏极区上方去除保形绝缘层的一部分，然后在器件上沉积第一多晶硅层。蚀刻定义了来自第一多晶硅层的多晶硅焊盘，其中多晶硅焊盘的边缘设置在栅电极和相邻布线之上。在该器件上方提供厚的平坦化的第二绝缘层，填充由多晶硅垫的局部杯形表面限定的体积。使用焊盘多晶硅层作为该工艺的蚀刻停止来执行蚀刻以去除平坦化绝缘层的一部分。接下来提供第二厚的多晶硅层以填充空腔，并且对该层进行图案化以横向限定下部电容器电极。半球形晶粒硅（HSG-Si）沉积在图案化的多晶硅层的表面上，并且使用回蚀工艺将HSG-Si层的拓扑转移到下面的多晶硅。进一步的处理提供电容器电介质和上电极。

6. 发明授权

US6017799A Method of fabricating dynamic random memory 失效
标题翻译：制作动态随机存储器的方法
公开(公告)号：US6017799A
公开(公告)日：2000-01-25
申请号：US40553
申请日：1998-03-18
申请人： Sun-Chieh Chien , Peter Hsue , Der-Yuan Wu
发明人： Sun-Chieh Chien , Peter Hsue , Der-Yuan Wu
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L27/10894
摘要： A method of fabricating a dynamic random memory. On a semiconductor substrate comprising a memory cell region and a periphery circuit region, a first field implantation and a first anti-punch through implantation are performed. Using a photo-resist layer formed to cover the memory cell region as a mask, the periphery circuit region is performed with a second field implantation and a second anti-punch through implantation.
摘要翻译：一种制造动态随机存储器的方法。在包括存储单元区域和外围电路区域的半导体衬底上，执行第一场注入和第一抗穿透注入。使用形成为覆盖存储单元区域作为掩模的光致抗蚀剂层，通过第二场注入和第二抗穿透注入来执行外围电路区域。

7. 发明授权

US6001682A Method of fabricating cylinder capacitors 失效
标题翻译：制造圆柱电容器的方法
公开(公告)号：US6001682A
公开(公告)日：1999-12-14
申请号：US59319
申请日：1998-04-13
申请人： Sun-Chieh Chien
发明人： Sun-Chieh Chien
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/82 , H01L28/90
摘要： A method of fabricating cylinder capacitors is provided comprising forming a first conductive layer and a dielectric layer on the semiconductor substrate. A via is formed in the dielectric layer. Then, a second conductive layer and a top oxide layer are formed on the dielectric layer. Part of the top oxide layer and the second conductive layer is removed by pattering the photoresist layer. A first spacer is formed at a side wall of the top oxide layer and the second conductive layer. The second conductive layer is etched by using the top oxide layer and the first spacer as a mask. Then, the top oxide layer is removed to form a second spacer. The second spacer is used as a mask in etching the second conductive layer to form a cup-shaped lower electrode. Further, a dielectric film layer and an upper electrode are formed to make a cylinder capacitor.
摘要翻译：提供一种制造圆柱形电容器的方法，包括在半导体衬底上形成第一导电层和介电层。在电介质层中形成通孔。然后，在介电层上形成第二导电层和顶部氧化物层。顶部氧化物层和第二导电层的一部分通过图案化光致抗蚀剂层被去除。在顶部氧化物层和第二导电层的侧壁上形成第一间隔物。通过使用顶部氧化物层和第一间隔物作为掩模来蚀刻第二导电层。然后，去除顶部氧化物层以形成第二间隔物。在蚀刻第二导电层时，第二间隔物用作掩模以形成杯形下电极。此外，形成电介质膜层和上电极以制成汽缸电容器。

8. 发明授权

US5966604A Method of manufacturing MOS components having lightly doped drain structures 失效
标题翻译：制造具有轻掺杂漏极结构的MOS器件的方法
公开(公告)号：US5966604A
公开(公告)日：1999-10-12
申请号：US890363
申请日：1997-07-09
申请人： Han Lin , Jengping Lin , Sun-Chieh Chien
发明人： Han Lin , Jengping Lin , Sun-Chieh Chien
IPC分类号： H01L21/265 , H01L21/285 , H01L21/336 , H01L29/10 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/28525 , H01L29/1045 , H01L21/26586 , H01L29/7833
摘要： The present invention relates to a method of manufacturing MOS components having lightly doped drains wherein the implanting type ion used is different than that used in the formation of the source/drain regions. The present invention also includes the use of a tilt implantation angle accompanied by substrate rotation during the implantation process to form lightly doped drain structures on two sides of the source/drain regions. The mask is the same for the formation of the source/drain regions as that for the formation of the lightly doped drain regions. The method of manufacturing MOS components having lightly doped drains according to this invention has fewer manufacturing processes for the formation of spacers than the conventional methods. Moreover, the reduction in spacer production results in an increased contact surface area for subsequent contact window formation, thereby lowering contact resistance.
摘要翻译：本发明涉及一种制造具有轻掺杂漏极的MOS元件的方法，其中使用的注入型离子不同于形成源极/漏极区所用的离子。本发明还包括在注入工艺期间伴随着衬底旋转的倾斜注入角度的使用，以在源极/漏极区域的两侧上形成轻掺杂的漏极结构。掩模与用于形成轻掺杂漏极区的源极/漏极区相同。根据本发明的制造具有轻掺杂漏极的MOS元件的制造方法比常规方法具有更少的用于形成间隔物的制造工艺。此外，间隔物生产的减少导致随后的接触窗形成的接触表面积增加，从而降低接触电阻。

9. 发明授权

US5946571A Method of forming a capacitor 失效
标题翻译：形成电容器的方法
公开(公告)号：US5946571A
公开(公告)日：1999-08-31
申请号：US975495
申请日：1997-11-21
申请人： Chen-Chiu Hsue , Sun-Chieh Chien
发明人： Chen-Chiu Hsue , Sun-Chieh Chien
IPC分类号： H01L21/8242
CPC分类号： H01L27/10852
摘要： A DRAM capacitor is formed having a crown structure with a reduced number of processing steps. A planarized insulating layer is provided over the DRAM cell's transfer FET and a contact via is opened to one of the source/drain regions of the transfer FET. A layer of polysilicon is deposited to fill the contact via and to extend over the surface of the insulating layer, providing a thick polysilicon layer on the insulating layer. Conventional photolithography is used to define a first etching mask with an element on the thick polysilicon aligned over the contact via. The polysilicon layer is etched partially through using the first etching mask and the photoresist mask is removed. A layer of oxide is deposited over the elevated and recessed surfaces of the polysilicon layer and an etch back process is performed to form a second etching mask consisting of oxide spacer structures along the edges of the elevated portion of the polysilicon layer. Etching of the polysilicon layer is performed using the second etching mask, with the etch step proceeding completely through the recessed portions of the polysilicon layer and partially through the elevated portion of the polysilicon layer. The second etch mask is removed and a capacitor dielectric and an upper electrode are provided to complete formation of the charge storage capacitor for the DRAM cell.
摘要翻译：形成具有减少数量的处理步骤的表冠结构的DRAM电容器。在DRAM单元的转移FET上提供平坦化的绝缘层，并且接触通孔对转移FET的源/漏区之一开放。沉积多晶硅层以填充接触通孔并在绝缘层的表面上延伸，在绝缘层上提供厚的多晶硅层。常规的光刻用于限定第一蚀刻掩模，其中厚多晶硅上的元件在接触通孔上对准。通过使用第一蚀刻掩模部分蚀刻多晶硅层，并去除光致抗蚀剂掩模。在多晶硅层的升高和凹陷表面上沉积一层氧化物，并且执行回蚀工艺以形成沿着多晶硅层的升高部分的边缘的氧化物间隔物结构构成的第二蚀刻掩模。使用第二蚀刻掩模进行多晶硅层的蚀刻，蚀刻步骤完全通过多晶硅层的凹陷部分并部分地穿过多晶硅层的升高部分。去除第二蚀刻掩模，并且提供电容器电介质和上电极以完成用于DRAM单元的电荷存储电容器的形成。

10. 发明授权

US5895256A Method for manufacturing LOCOS structure 失效
标题翻译： LOCOS结构的制造方法
公开(公告)号：US5895256A
公开(公告)日：1999-04-20
申请号：US997448
申请日：1997-12-23
申请人： Sun-Chieh Chien
发明人： Sun-Chieh Chien
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76202
摘要： A method for forming a LOCOS structure comprising the steps of providing a substrate, then forming a mask layer above the substrate. Next, the mask layer is patterned to form an opening having a depth not more than the mask layer. Subsequently, the mask layer is patterned to form an active device region exposing the substrate that lies outside the area, wherein the opening is within the active device region. Hence, a mask layer having a thicker peripheral section and a thinner middle section over the active device region is formed. Finally, a dielectric layer is formed over the expose substrate to serve as a device isolation structure. This invention provides a thin mask layer over the active device area to prevent the occurrence of excessive stresses, and hence improve the quality of subsequently formed gate oxide layer. On the other hand, this invention also provides a thick mask layer at the peripheral region of the active device area, thereby preventing the lengthening of the bird's beak region due to a thin mask layer.
摘要翻译：一种形成LOCOS结构的方法，包括以下步骤：提供衬底，然后在衬底上形成掩模层。接下来，对掩模层进行图案化以形成具有不超过掩模层的深度的开口。随后，掩模层被图案化以形成暴露位于区域外部的衬底的有源器件区域，其中开口在有源器件区域内。因此，形成了在有源器件区域上具有较厚的外围部分和较薄的中间部分的掩模层。最后，在曝光衬底上形成介电层以用作器件隔离结构。本发明提供了在有源器件区域上的薄掩模层，以防止发生过大的应力，从而提高随后形成的栅极氧化物层的质量。另一方面，本发明还提供了在有源器件区域的周边区域处的厚掩模层，从而防止了由于薄掩模层而导致的鸟嘴区域的延长。

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