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1. 发明授权

US08377829B2 Method of manufacturing a capacitor deep trench and of etching a deep trench opening 有权
标题翻译：制造电容器深沟槽并蚀刻深沟槽开口的方法
公开(公告)号：US08377829B2
公开(公告)日：2013-02-19
申请号：US11871166
申请日：2007-10-12
申请人： Ta-Chuan Yeh , Ni-Min Chung , Kao-Su Huang , Yung-Chang Lin , Ruey-Chyr Lee , Chien-Kuo Wang
发明人： Ta-Chuan Yeh , Ni-Min Chung , Kao-Su Huang , Yung-Chang Lin , Ruey-Chyr Lee , Chien-Kuo Wang
IPC分类号： H01L21/302 , H01L21/461 , B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00
CPC分类号： H01L27/1087 , H01L21/76205
摘要： A substrate is provided having an oxide layer, a first nitride-silicon, a STI, and a second nitride-silicon. A pattern poly-silicon layer on the second nitride-silicon layer is etched to form a deep trench opening. Etching the pattern poly-silicon layer also deepens the deep trench opening. Then, a conductive layer is filled in the deep trench opening.
摘要翻译：提供了具有氧化物层，第一氮化硅 - 硅，STI和第二氮化硅 - 硅的衬底。蚀刻第二氮化硅 - 硅层上的图案多晶硅层以形成深沟槽开口。蚀刻图案多晶硅层也加深了深沟槽开口。然后，在深沟槽开口中填充导电层。

2. 发明申请

US20070238244A1 TRENCH-CAPACITOR DRAM DEVICE AND MANUFACTURE METHOD THEREOF 有权
标题翻译： TRENCH-CAPACITOR DRAM器件及其制造方法
公开(公告)号：US20070238244A1
公开(公告)日：2007-10-11
申请号：US11279254
申请日：2006-04-11
申请人： Yung-Chang Lin , Sun-Chieh Chien , Chien-Li Kuo , Ruey-Chyr Lee
发明人： Yung-Chang Lin , Sun-Chieh Chien , Chien-Li Kuo , Ruey-Chyr Lee
IPC分类号： H01L21/8242 , H01L21/336 , H01L29/94 , H01L21/20
CPC分类号： H01L29/945 , H01L27/1087 , H01L29/66181
摘要： A trench capacitor structure includes a semiconductor substrate comprising thereon a STI structure. A capacitor deep trench is etched into the semiconductor substrate. Collar oxide layer is disposed on inner surface of the capacitor deep trench. A first doped polysilicon layer is disposed on the collar oxide layer and on the exposed bottom of the capacitor deep trench. A capacitor dielectric layer is formed on the first doped polysilicon layer. A second doped polysilicon layer is formed on the capacitor dielectric layer. A deep ion well is formed in the semiconductor substrate, wherein the deep ion well is electrically connected with the first doped polysilicon layer through the bottom of the capacitor deep trench. A passing gate insulation (PGI) layer is formed on the second doped polysilicon layer and on the STI structure.
摘要翻译：沟槽电容器结构包括其上包括STI结构的半导体衬底。电容器深沟槽被蚀刻到半导体衬底中。环状氧化物层设置在电容器深沟槽的内表面上。第一掺杂多晶硅层设置在轴环氧化物层和电容器深沟槽的暴露的底部上。在第一掺杂多晶硅层上形成电容器电介质层。第二掺杂多晶硅层形成在电容器介电层上。在半导体衬底中形成深离子阱，其中深离子阱通过电容器深沟槽的底部与第一掺杂多晶硅层电连接。在第二掺杂多晶硅层和STI结构上形成通过栅极绝缘（PGI）层。

3. 发明申请

US20070269946A1 Dynamic random access memory and fabrication method thereof 审中-公开
标题翻译：动态随机存取存储器及其制造方法
公开(公告)号：US20070269946A1
公开(公告)日：2007-11-22
申请号：US11437081
申请日：2006-05-19
申请人： Chien-Kuo Wang , Jun-Chi Huang , Ruey-Chyr Lee , Yung-Chang Lin
发明人： Chien-Kuo Wang , Jun-Chi Huang , Ruey-Chyr Lee , Yung-Chang Lin
IPC分类号： H01L21/8244
CPC分类号： H01L27/10861
摘要： A dynamic random access memory including a substrate, an isolation structure, two transistors, two trench capacitors and two passing gates is provided. The isolation structure, including a first isolation structure and a second isolation structure, is disposed in the substrate. The second isolation structure is disposed in the substrate above the first isolation structure and the bottom surface of the second isolation structure is lower than the top surface of the substrate. The periphery of the second isolation structure is beyond that of the first isolation structure. The transistors are disposed on the substrate respectively at two sides of the isolation structure. The trench capacitors are respectively disposed between the transistors and the isolation structures. A portion of the second isolation structure is disposed in the trench capacitor. The passing gates are completely disposed on the second isolation structure.
摘要翻译：提供了包括衬底，隔离结构，两个晶体管，两个沟槽电容器和两个通过栅极的动态随机存取存储器。包括第一隔离结构和第二隔离结构的隔离结构设置在基板中。第二隔离结构设置在第一隔离结构上方的基板中，并且第二隔离结构的底表面低于基板的顶表面。第二隔离结构的周边超出了第一隔离结构的周边。晶体管分别设置在隔离结构的两侧的基板上。沟槽电容器分别设置在晶体管和隔离结构之间。第二隔离结构的一部分设置在沟槽电容器中。通过的门完全设置在第二隔离结构上。

4. 发明申请

US20070045772A1 FUSE STRUCTURE FOR A SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的保险丝结构
公开(公告)号：US20070045772A1
公开(公告)日：2007-03-01
申请号：US11162150
申请日：2005-08-30
申请人： Chun-Wen Cheng , Chia-Wen Liang , Ruey-Chyr Lee , Sheng-Yuan Hsueh
发明人： Chun-Wen Cheng , Chia-Wen Liang , Ruey-Chyr Lee , Sheng-Yuan Hsueh
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure for a semiconductor device is provided. The fuse structure includes a fuse layer between the upper and bottom insulating layers. The fuse layer is connected to the other metal layers through via plugs. The fuse layer includes separate blocks and at least a connecting block and is coupled to at least a heat buffer block of a different layer. Because the heat buffer block is coupled to the blocks of the fuse layer, new fusing point and a new path for effectively dissipating the heat are provided and a longer and sinuous electric current path is obtained between the blocks through the heat buffer blocks. The heat buffer block and the blocks coupled to the heat buffer block can avoid large current flowing through the fuse structure and prevent overheating.
摘要翻译：提供一种用于半导体器件的熔丝结构。熔丝结构包括在上绝缘层和下绝缘层之间的熔丝层。保险丝层通过通孔连接到其他金属层。熔丝层包括单独的块和至少一个连接块，并且至少耦合到不同层的热缓冲块。由于热缓冲块耦合到熔丝层的块，所以提供了新的熔点和用于有效散热的新路径，并且通过热缓冲块在块之间获得更长和弯曲的电流路径。加热缓冲块和耦合到热缓冲块的块可以避免大电流流过保险丝结构并防止过热。

5. 发明授权

US07344954B2 Method of manufacturing a capacitor deep trench and of etching a deep trench opening 有权
标题翻译：制造电容器深沟槽并蚀刻深沟槽开口的方法
公开(公告)号：US07344954B2
公开(公告)日：2008-03-18
申请号：US11306560
申请日：2006-01-03
申请人： Ta-Chuan Yeh , Ni-Min Chung , Kao-Su Huang , Yung-Chang Lin , Ruey-Chyr Lee , Chien-Kuo Wang
发明人： Ta-Chuan Yeh , Ni-Min Chung , Kao-Su Huang , Yung-Chang Lin , Ruey-Chyr Lee , Chien-Kuo Wang
IPC分类号： H01L21/20
CPC分类号： H01L27/1087 , H01L21/76205
摘要： A substrate is provided having an oxide layer, a first nitride-silicon, a STI, and a second nitride-silicon. A pattern poly-silicon layer on the second nitride-silicon layer is etched to form a deep trench opening. Etching the pattern poly-silicon layer also deepens the deep trench opening. Then, a conductive layer is filled in the deep trench opening.
摘要翻译：提供了具有氧化物层，第一氮化硅 - 硅，STI和第二氮化硅 - 硅的衬底。蚀刻第二氮化硅 - 硅层上的图案多晶硅层以形成深沟槽开口。蚀刻图案多晶硅层也加深了深沟槽开口。然后，在深沟槽开口中填充导电层。

6. 发明授权

US07332392B2 Trench-capacitor DRAM device and manufacture method thereof 有权
标题翻译：沟槽电容器DRAM器件及其制造方法
公开(公告)号：US07332392B2
公开(公告)日：2008-02-19
申请号：US11279254
申请日：2006-04-11
申请人： Yung-Chang Lin , Sun-Chieh Chien , Chien-Li Kuo , Ruey-Chyr Lee
发明人： Yung-Chang Lin , Sun-Chieh Chien , Chien-Li Kuo , Ruey-Chyr Lee
IPC分类号： H01L21/8242
CPC分类号： H01L29/945 , H01L27/1087 , H01L29/66181
摘要： A trench capacitor structure includes a semiconductor substrate comprising thereon a STI structure. A capacitor deep trench is etched into the semiconductor substrate. Collar oxide layer is disposed on inner surface of the capacitor deep trench. A first doped polysilicon layer is disposed on the collar oxide layer and on the exposed bottom of the capacitor deep trench. A capacitor dielectric layer is formed on the first doped polysilicon layer. A second doped polysilicon layer is formed on the capacitor dielectric layer. A deep ion well is formed in the semiconductor substrate, wherein the deep ion well is electrically connected with the first doped polysilicon layer through the bottom of the capacitor deep trench. A passing gate insulation (PGI) layer is formed on the second doped polysilicon layer and on the STI structure.
摘要翻译：沟槽电容器结构包括其上包括STI结构的半导体衬底。电容器深沟槽被蚀刻到半导体衬底中。环状氧化物层设置在电容器深沟槽的内表面上。第一掺杂多晶硅层设置在轴环氧化物层和电容器深沟槽的暴露的底部上。在第一掺杂多晶硅层上形成电容器电介质层。第二掺杂多晶硅层形成在电容器介电层上。在半导体衬底中形成深离子阱，其中深离子阱通过电容器深沟槽的底部与第一掺杂多晶硅层电连接。在第二掺杂多晶硅层和STI结构上形成通过栅极绝缘（PGI）层。

7. 发明申请

US20080038931A1 METHOD OF MANUFACTURING A CAPACITOR DEEP TRENCH AND OF ETCHING A DEEP TRENCH OPENING 有权
标题翻译：制造电容式深层电镀和蚀刻深层开关的方法
公开(公告)号：US20080038931A1
公开(公告)日：2008-02-14
申请号：US11871166
申请日：2007-10-12
申请人： Ta-Chuan Yeh , Ni-Min Chung , Kao-Su Huang , Yung-Chang Lin , Ruey-Chyr Lee , Chien-Kuo Wang
发明人： Ta-Chuan Yeh , Ni-Min Chung , Kao-Su Huang , Yung-Chang Lin , Ruey-Chyr Lee , Chien-Kuo Wang
IPC分类号： H01L21/306
CPC分类号： H01L27/1087 , H01L21/76205
摘要： A substrate is provided having an oxide layer, a first nitride-silicon, a STI, and a second nitride-silicon. A pattern poly-silicon layer on the second nitride-silicon layer is etched to form a deep trench opening. Etching the pattern poly-silicon layer also deepens the deep trench opening. Then, a conductive layer is filled in the deep trench opening.
摘要翻译：提供了具有氧化物层，第一氮化硅 - 硅，STI和第二氮化硅 - 硅的衬底。蚀刻第二氮化硅 - 硅层上的图案多晶硅层以形成深沟槽开口。蚀刻图案多晶硅层也加深了深沟槽开口。然后，在深沟槽开口中填充导电层。

8. 发明申请

US20070155089A1 METHOD OF MANUFACTURING A CAPACITOR DEEP TRENCH AND OF ETCHING A DEEP TRENCH OPENING 有权
标题翻译：制造电容式深层电镀和蚀刻深层开关的方法
公开(公告)号：US20070155089A1
公开(公告)日：2007-07-05
申请号：US11306560
申请日：2006-01-03
申请人： Ta-Chuan Yeh , Ni-Min Chung , Kao-Su Huang , Yung-Chang Lin , Ruey-Chyr Lee , Chien-Kuo Wang
发明人： Ta-Chuan Yeh , Ni-Min Chung , Kao-Su Huang , Yung-Chang Lin , Ruey-Chyr Lee , Chien-Kuo Wang
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087 , H01L21/76205
摘要： A substrate is provided having an oxide layer, a first nitride-silicon, a STI, and a second nitride-silicon. A pattern poly-silicon layer on the second nitride-silicon layer is etched to form a deep trench opening. Etching the pattern poly-silicon layer also deepens the deep trench opening. Then, a conductive layer is filled in the deep trench opening.
摘要翻译：提供了具有氧化物层，第一氮化硅 - 硅，STI和第二氮化硅 - 硅的衬底。蚀刻第二氮化硅 - 硅层上的图案多晶硅层以形成深沟槽开口。蚀刻图案多晶硅层也加深了深沟槽开口。然后，在深沟槽开口中填充导电层。

9. 发明授权

US07190044B1 Fuse structure for a semiconductor device 有权
标题翻译：一种半导体器件的保险丝结构
公开(公告)号：US07190044B1
公开(公告)日：2007-03-13
申请号：US11162150
申请日：2005-08-30
申请人： Chun-Wen Cheng , Chia-Wen Liang , Ruey-Chyr Lee , Sheng-Yuan Hsueh
发明人： Chun-Wen Cheng , Chia-Wen Liang , Ruey-Chyr Lee , Sheng-Yuan Hsueh
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure for a semiconductor device is provided. The fuse structure includes a fuse layer between the upper and bottom insulating layers. The fuse layer is connected to the other metal layers through via plugs. The fuse layer includes separate blocks and at least a connecting block and is coupled to at least a heat buffer block of a different layer. Because the heat buffer block is coupled to the blocks of the fuse layer, new fusing point and a new path for effectively dissipating the heat are provided and a longer and sinuous electric current path is obtained between the blocks through the heat buffer blocks. The heat buffer block and the blocks coupled to the heat buffer block can avoid large current flowing through the fuse structure and prevent overheating.
摘要翻译：提供一种用于半导体器件的熔丝结构。熔丝结构包括在上绝缘层和下绝缘层之间的熔丝层。保险丝层通过通孔连接到其他金属层。熔丝层包括单独的块和至少一个连接块，并且至少耦合到不同层的热缓冲块。由于热缓冲块耦合到熔丝层的块，所以提供了新的熔点和用于有效散热的新路径，并且通过热缓冲块在块之间获得更长和弯曲的电流路径。加热缓冲块和耦合到热缓冲块的块可以避免大电流流过保险丝结构并防止过热。

10. 发明申请

US20080020539A1 DYNAMIC RANDOM ACCESS MEMORY AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：动态随机存取存储器及其制造方法
公开(公告)号：US20080020539A1
公开(公告)日：2008-01-24
申请号：US11865542
申请日：2007-10-01
申请人： CHIEN-KUO WANG , JUN-CHI HUANG , RUEY-CHYR LEE , YUNG-CHANG LIN
发明人： CHIEN-KUO WANG , JUN-CHI HUANG , RUEY-CHYR LEE , YUNG-CHANG LIN
IPC分类号： H01L21/02
CPC分类号： H01L27/10861
摘要： A dynamic random access memory including a substrate, an isolation structure, two transistors, two trench capacitors and two passing gates is provided. The isolation structure, including a first isolation structure and a second isolation structure, is disposed in the substrate. The second isolation structure is disposed in the substrate above the first isolation structure and the bottom surface of the second isolation structure is lower than the top surface of the substrate. The periphery of the second isolation structure is beyond that of the first isolation structure. The transistors are disposed on the substrate respectively at two sides of the isolation structure. The trench capacitors are respectively disposed between the transistors and the isolation structures. A portion of the second isolation structure is disposed in the trench capacitor. The passing gates are completely disposed on the second isolation structure.
摘要翻译：提供了包括衬底，隔离结构，两个晶体管，两个沟槽电容器和两个通过栅极的动态随机存取存储器。包括第一隔离结构和第二隔离结构的隔离结构设置在基板中。第二隔离结构设置在第一隔离结构上方的基板中，并且第二隔离结构的底表面低于基板的顶表面。第二隔离结构的周边超出了第一隔离结构的周边。晶体管分别设置在隔离结构的两侧的基板上。沟槽电容器分别设置在晶体管和隔离结构之间。第二隔离结构的一部分设置在沟槽电容器中。通过的门完全设置在第二隔离结构上。

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