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1. 发明申请

WO2021221911A1 BALANCING DATA FOR STORAGE IN A MEMORY DEVICE 审中-公开
公开(公告)号：WO2021221911A1
公开(公告)日：2021-11-04
申请号：PCT/US2021/027313
申请日：2021-04-14
申请人： MICRON TECHNOLOGY, INC.
发明人： LAURENT, Christophe, Vincent Antoine , MARTINELLI, Andrea , SFORZIN, Marco , AMATO, Paolo
IPC分类号： G06F3/06 , H04L12/861
摘要： Methods, systems, and devices related to balancing data are described. Data may be communicated using an original set of bits that may be partitioned into segments. Each of the original set of bits may have a first value or a second value, where a weight of the original set of bits may be based on a quantity of the set of bits that have the first value. If the weight of the original set of bits is outside of a target weight range, a different, encoded set of bits may be used to represent the data, the encoded set of bits having a weight within the target weight range. The encoded set of bits may be identified based an inversion of the original set of bits in a one-at-a-time and cumulative fashion. The encoded set of bits may be stored in place of the original set of bits.

2. 发明申请

WO2021041003A1 ARCHITECTURE-BASED POWER MANAGEMENT FOR A MEMORY DEVICE 审中-公开
公开(公告)号：WO2021041003A1
公开(公告)日：2021-03-04
申请号：PCT/US2020/045412
申请日：2020-08-07
申请人： MICRON TECHNOLOGY, INC.
发明人： LAURENT, Christophe, Vincent Antoine , MARTINELLI, Andrea , MIRICHIGNI, Graziano
IPC分类号： G11C5/14 , G11C8/12 , G06F3/06 , G11C5/04
摘要： Methods, systems, and devices for architecture-based power management for a memory device are described. Aspects include operating a first memory bank within a memory device in a first mode and a second memory bank within the memory device in a second mode. The memory device may receive a power down command for the first memory bank while operating the first memory bank in the first mode and the second memory bank in the second mode and switch the first memory bank from the first mode to a first low power mode while maintaining the second memory bank in the second mode. The first low power mode corresponds to less power consumption by the first memory bank than the first mode. In some cases, switching the first memory bank from the first mode to the first low power mode includes deactivating circuitry dedicated to the first memory bank.

3. 发明申请

WO2022217188A1 FIXED WEIGHT CODEWORDS FOR TERNARY MEMORY CELLS 审中-公开
公开(公告)号：WO2022217188A1
公开(公告)日：2022-10-13
申请号：PCT/US2022/071264
申请日：2022-03-22
申请人： MICRON TECHNOLOGY, INC.
发明人： LAURENT, Christophe, Vincent Antoine , MUZZETTO, Riccardo
IPC分类号： G06F3/06 , G11C7/10 , G06F11/10
摘要： Methods, systems, and devices for fixed weight codewords for ternary memory cells are described. A memory device may generate a codeword from a set of data bits and invert a portion of the codeword so that the codeword is associated with a target distribution of programmable states. After inverting the portion of the codeword, the memory device store the codeword in a set of ternary cells according to a coding scheme. The memory device may read the codeword from the set of ternary cells and select one or more reference voltages for the set of ternary cells based on the target distribution for the codeword and the states of the ternary cells.

4. 发明申请

WO2022026184A1 GENERATING A BALANCED CODEWORD PROTECTED BY AN ERROR CORRECTION CODE 审中-公开
公开(公告)号：WO2022026184A1
公开(公告)日：2022-02-03
申请号：PCT/US2021/041562
申请日：2021-07-14
申请人： MICRON TECHNOLOGY, INC.
发明人： LAURENT, Christophe, Vincent Antoine
IPC分类号： G06F11/10 , H03M13/37 , H03M13/15
摘要： Methods, systems, and devices for generating a balanced codeword protected by an error correction code are described. A memory device may receive data bits for storage. Based on the data bits, the memory device may generate a codeword that includes the data bits, parity bits, and placeholder bits. The memory device may balance the codeword by inverting one or more packets of the codeword. After balancing the codeword, the memory device may store at least a portion of the codeword in memory so that a later operation or a decoding process reveals the packets that were inverted as part of the balancing process. Accordingly, the memory device may re-invert the appropriate packets to recover the original data bits.

5. 发明申请

WO2021040969A1 BANK CONFIGURABLE POWER MODES 审中-公开
公开(公告)号：WO2021040969A1
公开(公告)日：2021-03-04
申请号：PCT/US2020/044736
申请日：2020-08-03
申请人： MICRON TECHNOLOGY, INC.
发明人： MIRICHIGNI, Graziano , MARTINELLI, Andrea , LAURENT, Christophe, Vincent Antoine
IPC分类号： G11C5/14 , G11C8/12 , G11C7/10 , G06F3/06 , G11C11/22
摘要： Methods, systems, and devices for bank-configurable power modes are described. Aspects include operating a memory device that has multiple memory banks in a first mode. While operating in the first mode, the memory device may receive a command to enter a second mode having a lower power consumption level than the first mode. The memory device may enter the second mode by switching a first subset of the memory banks to a first low power mode that operates at a first power consumption level and a second subset of the memory banks to a second low power mode that operates at a second power consumption level that may be lower than the first power consumption level. In some cases, the memory device may switch the first subset of memory banks from the first low power mode while maintaining the second subset of memory banks in the low power mode.

6. 发明申请

WO2015038466A1 APPARATUS AND METHODS FOR LEAKAGE CURRENT REDUCTION IN INTEGRATED CIRCUITS 审中-公开
标题翻译：集成电路中漏电流减少的装置和方法
公开(公告)号：WO2015038466A1
公开(公告)日：2015-03-19
申请号：PCT/US2014/054524
申请日：2014-09-08
申请人： MICRON TECHNOLOGY, INC.
发明人： LAURENT, Christophe, Vincent Antoine
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/0016 , G06F17/5022 , G06F17/5045 , H03K19/20
摘要： This disclosure relates to leakage current reduction in integrated circuits (ICs). In one aspect, an IC can include a digital logic circuit and a polarization circuit. The digital logic circuit can have a plurality of inputs and can include a plurality of logic gates. The polarization circuit can receive a standby signal and a digital input signal comprising a plurality of bits. When the standby signal is deactivated, the polarization circuit can control the plurality of inputs of the digital logic circuit based on the digital input signal. However, when the standby signal is activated the polarization circuit can control the plurality of inputs of the digital logic circuit to a low power state associated with a smaller leakage current of the plurality of logic gates relative to at least one other state of the digital logic circuit.
摘要翻译：本公开涉及集成电路（IC）中的漏电流减少。一方面，IC可以包括数字逻辑电路和极化电路。数字逻辑电路可以具有多个输入并且可以包括多个逻辑门。偏振电路可以接收备用信号和包括多个位的数字输入信号。当待机信号被去激活时，极化电路可以基于数字输入信号来控制数字逻辑电路的多个输入。然而，当待机信号被激活时，极化电路可以将数字逻辑电路的多个输入控制到与多个逻辑门相对于数字逻辑的至少一个其他状态的较小漏电流相关联的低功率状态电路。

7. 发明申请

WO2022026234A1 GENERATING A PROTECTED AND BALANCED CODEWORD 审中-公开
公开(公告)号：WO2022026234A1
公开(公告)日：2022-02-03
申请号：PCT/US2021/042173
申请日：2021-07-19
申请人： MICRON TECHNOLOGY, INC.
发明人： LAURENT, Christophe, Vincent Antoine
IPC分类号： G06F11/10 , H03M13/15 , H03M13/37
摘要： Methods, systems, and devices for generating a balanced codeword protected by an error correction code are described. A memory device may receive data bits for storage. Based on the data bits, the memory device may generate a codeword that includes the data bits, parity bits, and placeholder bits. The memory device may balance the codeword by inverting one or more packets of the codeword. After balancing the codeword, the memory device may store at least a portion of the codeword in memory so that a later operation or a decoding process reveals the packets that were inverted as part of the balancing process. Accordingly, the memory device may re-invert the appropriate packets to recover the original data bits.

8. 发明申请

WO2021006969A1 CIRCUIT PARTITIONING FOR A MEMORY DEVICE 审中-公开
公开(公告)号：WO2021006969A1
公开(公告)日：2021-01-14
申请号：PCT/US2020/035889
申请日：2020-06-03
申请人： MICRON TECHNOLOGY, INC.
发明人： MARTINELLI, Andrea , LAURENT, Christophe, Vincent Antoine , NAVA, Claudio , DEFENDI, Marco
IPC分类号： G11C8/12 , G11C16/08
摘要： Methods, systems, and devices for circuit partitioning for a memory device are described. In one example, a memory device may include a set of memory tiles that each include a respective array of memory cells (e.g., in an array level or layer). Each of the memory tiles may include a respective circuit level or layer associated with circuitry configured to operate the respective array of memory cells. The memory device may also include circuitry for communicating data between the memory cells of the set of memory tiles and an input/output component. Aspects of the circuitry for communicating the data may be subdivided into repeatable blocks each configured to communicate one or more bits, and the repeatable blocks and other aspects of the circuitry for communicating the data is distributed across the circuit layer of two or more of the set of memory tiles.

9. 发明公开

EP4022612A1 ARCHITECTURE-BASED POWER MANAGEMENT FOR A MEMORY DEVICE 审中-实审
公开(公告)号：EP4022612A1
公开(公告)日：2022-07-06
申请号：EP20858222.1
申请日：2020-08-07
申请人： MICRON TECHNOLOGY, INC.
发明人： LAURENT, Christophe, Vincent Antoine , MARTINELLI, Andrea , MIRICHIGNI, Graziano
IPC分类号： G11C5/14 , G11C8/12 , G06F3/06 , G11C5/04

10. 发明公开

EP3997702A1 CIRCUIT PARTITIONING FOR A MEMORY DEVICE 审中-实审
公开(公告)号：EP3997702A1
公开(公告)日：2022-05-18
申请号：EP20837291.2
申请日：2020-06-03
申请人： MICRON TECHNOLOGY, INC.
发明人： MARTINELLI, Andrea , LAURENT, Christophe, Vincent Antoine , NAVA, Claudio , DEFENDI, Marco
IPC分类号： G11C8/12 , G11C16/08

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