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1. 发明申请

WO2014066845A1 APPARATUSES AND METHODS FOR MEMORY OPERATIONS HAVING VARIABLE LATENCIES 审中-公开
标题翻译：具有可变延迟的存储器操作的装置和方法
公开(公告)号：WO2014066845A1
公开(公告)日：2014-05-01
申请号：PCT/US2013/066949
申请日：2013-10-25
申请人： MIRICHIGNI, Graziano , VILLA, Corrado , PORZIO, Luca , MICRON TECHNOLOGY, INC.
发明人： MIRICHIGNI, Graziano , VILLA, Corrado , PORZIO, Luca
IPC分类号： G06F13/14 , G06F13/38 , G06F12/00
CPC分类号： G11C7/22 , G06F13/1689 , G11C7/1063
摘要： Apparatuses and methods for performing memory operations are described. In an example apparatus, a memory is configured to receive a memory instruction and perform a memory operation responsive to the memory instruction. The memory is further configured to provide an acknowledgement indicative of an end of the variable latency period wherein the acknowledgement includes information related to an acceptance of a memory instruction. Data associated with the memory instruction is exchanged with the memory following the acknowledgement. In an example method a read instruction and an address from which read data is to be read is received. A write operation is suspended responsive to the read instruction and an acknowledgement indicative of an end of the variable latency period is provided. Read data for the read instruction is provided and the write operation is continued to be suspended for a hold-off period following completion of the read operation.
摘要翻译：描述用于执行存储器操作的装置和方法。在示例性装置中，存储器被配置为接收存储器指令并且响应于存储器指令执行存储器操作。存储器还被配置为提供指示可变等待时间周期的结束的确认，其中确认包括与接受存储器指令相关的信息。与存储器指令相关联的数据与确认之后的存储器交换。在示例性方法中，接收读取指令和读取数据的地址。响应于读取指令而停止写入操作，并且提供指示可变等待时间周期结束的确认。提供读取指令的读取数据，并且在读取操作完成之后继续执行写入操作以用于停止时间。

2. 发明申请

WO2014066843A1 APPARATUSES AND METHODS FOR MEMORY OPERATIONS HAVING VARIABLE LATENCIES 审中-公开
标题翻译：具有可变延迟的存储器操作的装置和方法
公开(公告)号：WO2014066843A1
公开(公告)日：2014-05-01
申请号：PCT/US2013/066947
申请日：2013-10-25
申请人： MIRICHIGNI, Graziano , VILLA, Corrado , PORZIO, Luca , TAN, Chee Weng , LEMARIE, Sebastien , KLINDWORTH, Andre , MICRON TECHNOLOGY, INC.
发明人： MIRICHIGNI, Graziano , VILLA, Corrado , PORZIO, Luca , TAN, Chee Weng , LEMARIE, Sebastien , KLINDWORTH, Andre
IPC分类号： G06F13/14 , G06F13/38 , G06F12/00
CPC分类号： G06F9/30047 , G06F13/161 , G06F13/1689 , G11C7/1063 , G11C7/22 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2207/2272
摘要： Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.
摘要翻译：描述用于执行存储器操作的装置和方法。示例性装置包括存储器操作控制器。存储器操作控制器被配置为接收存储器指令并对其进行解码以提供用于对存储器指令执行存储器操作的内部信号。存储器操作控制器还被配置为在可变等待时间周期期间提供指示存储器指令的可变等待时间周期的时间的信息。在示例性方法中，在存储器处接收要写入数据的写指令和地址，并且提供指示用于写指令的可变等待时间周期结束的确认。在确认之后等待可变总线周转后，接收写入指令的写入数据。

3. 发明公开

EP2912558A1 APPARATUSES AND METHODS FOR MEMORY OPERATIONS HAVING VARIABLE LATENCIES 有权转让
标题翻译：器件和方法的存储操作变延迟时间
公开(公告)号：EP2912558A1
公开(公告)日：2015-09-02
申请号：EP13849956.1
申请日：2013-10-25
申请人： Mirichigni, Graziano , Villa, Corrado , Porzio, Luca , Micron Technology, Inc.
发明人： MIRICHIGNI, Graziano , VILLA, Corrado , PORZIO, Luca
IPC分类号： G06F13/14 , G06F13/38 , G06F12/00
CPC分类号： G11C7/22 , G06F13/1689 , G11C7/1063
摘要： Apparatuses and methods for performing memory operations are described. In an example apparatus, a memory is configured to receive a memory instruction and perform a memory operation responsive to the memory instruction. The memory is further configured to provide an acknowledgement indicative of an end of the variable latency period wherein the acknowledgement includes information related to an acceptance of a memory instruction. Data associated with the memory instruction is exchanged with the memory following the acknowledgement. In an example method a read instruction and an address from which read data is to be read is received. A write operation is suspended responsive to the read instruction and an acknowledgement indicative of an end of the variable latency period is provided. Read data for the read instruction is provided and the write operation is continued to be suspended for a hold-off period following completion of the read operation.

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