专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06236617B1 High performance CMOS word-line driver 有权
标题翻译：高性能CMOS字线驱动
公开(公告)号：US06236617B1
公开(公告)日：2001-05-22
申请号：US09458878
申请日：1999-12-10
申请人： Louis L. Hsu , Hans-Oliver Joachim , Matthew R. Wordeman , Hing Wong
发明人： Louis L. Hsu , Hans-Oliver Joachim , Matthew R. Wordeman , Hing Wong
IPC分类号： G11C800
CPC分类号： G11C8/08
摘要： A negative wordline DRAM array having n groups of m wordlines, in which one group is driven by a group decoder circuit (having a voltage swing between ground and a circuit high voltage (2 v)) and one driver circuit in each group is exposed to a boosted wordline high voltage (2.8 v) greater than the circuit high voltage, in which the wordline driver circuits have an output stage comprising a standard nfet in series with a high threshold voltage pfet, so that, during activation, the unselected driver circuits exposed to the boosted wordline high voltage have a very low leakage through the pfet, while the selected driver circuit has a high but tolerable leakage (2 &mgr;A) because Vqs on the nfet is nearly at the nfet threshold. The net active power from the entire array is less than that of a conventional configuration due to the reduced voltage swing, while the number of transistors exposed to high voltage stress is reduced from 9 to 1 and the number of buffer nfets required to reduce voltage drop across an active nfet is reduced from 8 to 1.
摘要翻译：具有n组m个字线的负字形DRAM阵列暴露于一组，其中一组由组解码器电路（具有地面之间的电压摆幅和电路高电压（2v））和每组中的一个驱动器电路驱动提升的字线高电压（2.8V）大于电路高电压，其中字线驱动器电路具有包括与高阈值电压pfet串联的标准nfet的输出级，使得在激活期间，未选择的驱动器电路暴露对于升压的字线高电压通过pfet具有非常低的泄漏，而所选择的驱动器电路具有高但可容许的泄漏（2μA），因为nfet上的Vqs几乎处于nfet阈值。由于降低的电压摆幅，整个阵列的净有功功率小于传统配置的功率，而暴露于高电压应力的晶体管的数量从9减少到1，并且减少电压降所需的缓冲器数量跨越一个活跃的nfet从8减少到1。

2. 发明授权

US06396324B1 Clock system for an embedded semiconductor memory unit 有权
标题翻译：嵌入式半导体存储单元的时钟系统
公开(公告)号：US06396324B1
公开(公告)日：2002-05-28
申请号：US09566311
申请日：2000-05-08
申请人： Louis L. Hsu , Rajiv V. Joshi , Richard M. Parent , Matthew R. Wordeman
发明人： Louis L. Hsu , Rajiv V. Joshi , Richard M. Parent , Matthew R. Wordeman
IPC分类号： G06F104
CPC分类号： G11C7/225 , G06F1/04 , G11C7/22 , G11C7/222
摘要： A clock system is provided capable of using an external system clock for driving at least one charge circuit of a semiconductor memory unit for restoring and refreshing a data array of the memory unit. The clock system, in one embodiment, includes a plurality of control circuits each having a clock select circuit which has as an input the external system clock, an internal clock generator circuit for generating an internal system clock, and a multiplexer. The multiplexer has as inputs an output of the clock select circuit, i.e., the external system clock, and an output of the internal clock generator circuit, i.e., the internal system clock. The multiplexer outputs either the external system clock or the internal system clock to the at least one charge circuit according to at least one control signal transmitted by a central processing unit to the clock select circuit.
摘要翻译：提供一种时钟系统，其能够使用外部系统时钟来驱动用于恢复和刷新存储器单元的数据阵列的半导体存储器单元的至少一个充电电路。在一个实施例中，时钟系统包括多个控制电路，每个控制电路具有时钟选择电路，该时钟选择电路具有作为输入的外部系统时钟，用于产生内部系统时钟的内部时钟发生器电路和多路复用器。多路复用器具有时钟选择电路的输出，即外部系统时钟和内部时钟发生器电路的输出，即内部系统时钟的输入。根据由中央处理单元发送到时钟选择电路的至少一个控制信号，多路复用器将外部系统时钟或内部系统时钟输出到至少一个充电电路。

3. 发明授权

US06349067B1 System and method for preventing noise cross contamination between embedded DRAM and system chip 失效
标题翻译：嵌入式DRAM与系统芯片之间的噪声交叉污染防止系统和方法
公开(公告)号：US06349067B1
公开(公告)日：2002-02-19
申请号：US09772461
申请日：2001-01-30
申请人： Louis L. Hsu , Richard M. Parent , Li-Kong Wang , Matthew R. Wordeman
发明人： Louis L. Hsu , Richard M. Parent , Li-Kong Wang , Matthew R. Wordeman
IPC分类号： G11C702
CPC分类号： G11C7/02 , G11C7/18 , G11C2207/104 , H01L21/761 , H01L21/823481 , H01L27/10897
摘要： A complete solution to block noise from eDRAM macro to the analog core, and vice verse, in a system-on-chip IC design. Specifically, there is provided a first isolated triple well structure formed in the IC for reducing noise component resulting from operative elements of a DC generator circuit fabricated therein; and, a second isolated triple well structure formed in the IC for reducing noise component resulting from operative elements of a noise sense amplifier bank and DRAM arrays fabricated therein. A power supply source is provided for supplying power to each DC generator circuit, noise sense amplifier bank and DRAM array; as is a power bus for providing power and a separate power bus for providing a ground to each of the DC generator circuit, and the noise sense amplifier circuit and DRAM array components. In this manner, noise contamination with noise sensitive devices in said IC is reduced and, further noise contamination of the DRAM array as sourced from the IC is reduced.
摘要翻译：一种完整的解决方案，可以将eDRAM宏的噪声阻挡到模拟核心，而在片上系统集成电路设计中也是如此。具体地，提供了一种形成在IC中的用于减少由其中制造的直流发电机电路的操作元件产生的噪声分量的第一隔离三重阱结构; 以及形成在IC中的用于降低噪声检测放大器组的操作元件和其中制造的DRAM阵列产生的噪声分量的第二隔离三重阱结构。提供电源，用于向每个DC发生器电路，噪声检测放大器组和DRAM阵列供电; 用于提供电力的电源总线和用于向每个DC发电机电路以及噪声检测放大器电路和DRAM阵列组件提供接地的单独的电源总线。以这种方式，减少了所述IC中噪声敏感器件的噪声污染，并且降低了来自IC的DRAM阵列的进一步的噪声污染。

4. 发明申请

US20120188002A1 MODULARIZED THREE-DIMENSIONAL CAPACITOR ARRAY 有权
标题翻译：模块化三维电容阵列
公开(公告)号：US20120188002A1
公开(公告)日：2012-07-26
申请号：US13438230
申请日：2012-04-03
申请人： Louis L. Hsu , Xu Ouyang , Chih-Chao Yang
发明人： Louis L. Hsu , Xu Ouyang , Chih-Chao Yang
IPC分类号： H03K17/687 , H01L21/02
CPC分类号： H01L28/40 , H01L22/14 , H01L22/22 , H01L22/34 , H01L23/5223 , H01L27/0688 , H01L27/0805 , H01L28/60 , H01L2924/0002 , Y10T307/865 , H01L2924/00
摘要： A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.
摘要翻译：模块化电容器阵列包括多个电容器模块。每个电容器模块包括电容器和被配置为电气断开电容器的开关装置。开关装置包括：感测单元，被配置为检测电容器的泄漏电平，使得如果泄漏电流超过预定电平，则开关装置电连接电容器。每个电容器模块可以包括单个电容器板，两个电容器板或多于两个的电容器板。泄漏传感器和开关装置用于电气断开任何电容器阵列的电容器模块，从而保护电容器阵列免于漏电。

5. 发明授权

US08198174B2 Air channel interconnects for 3-D integration 有权
标题翻译：空气通道互连用于3-D集成
公开(公告)号：US08198174B2
公开(公告)日：2012-06-12
申请号：US12536176
申请日：2009-08-05
申请人： Louis L. Hsu , Brian L. Ji , Fei Liu , Conal E. Murray
发明人： Louis L. Hsu , Brian L. Ji , Fei Liu , Conal E. Murray
IPC分类号： H01L21/44
CPC分类号： H01L23/467 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional (3D) chip stack structure and method of fabricating the structure thereof are provided. The 3D chip stack structure includes a plurality of vertically stacked chips which are interconnected and bonded together, wherein each of the vertically stacked chips include one or more IC device strata. The 3D chip stack structure further includes an air channel interconnect network embedded within the chip stack structure, and wherein the air channel interconnect network is formed in between at least two wafers bonded to each other of the vertically stacked wafers and in between at least two bonded wafers of the vertically stacked wafers at a bonding interface thereof. In addition, the 3D chip stack structure further includes one or more openings in a peripheral region of the chip stack structure that lead into and out of the air channel interconnect network, so that air can flow into and out of the air channel interconnect network through the one or more openings to remove heat from the chip stack structure.
摘要翻译：提供三维（3D）芯片堆叠结构及其结构的制造方法。 3D芯片堆叠结构包括互连并结合在一起的多个垂直堆叠的芯片，其中每个垂直堆叠的芯片包括一个或多个IC器件层。 3D芯片堆叠结构还包括嵌入在芯片堆叠结构内的空气通道互连网络，并且其中空气通道互连网络形成在至少两个晶片之间，所述至少两个晶片彼此接合在垂直堆叠的晶片之间，并且在至少两个结合在其接合界面处的垂直堆叠的晶片的晶片。此外，3D芯片堆叠结构还包括在芯片堆叠结构的外围区域中的一个或多个开口，其引入和流出空气通道互连网络，使得空气可以流入和流出空气通道互连网络，通过一个或多个开口以从芯片堆叠结构移除热量。

6. 发明申请

US20110254121A1 PROGRAMMABLE ANTI-FUSE STRUCTURES WITH CONDUCTIVE MATERIAL ISLANDS 失效
标题翻译：具有导电材料岛的可编程防结构
公开(公告)号：US20110254121A1
公开(公告)日：2011-10-20
申请号：US12761780
申请日：2010-04-16
申请人： Kangguo Cheng , Louis L. Hsu , William R. Tonti , Chih-Chao Yang
发明人： Kangguo Cheng , Louis L. Hsu , William R. Tonti , Chih-Chao Yang
IPC分类号： H01L23/525 , H01L21/768 , G06F17/50
CPC分类号： H01L23/5252 , G06F17/505 , H01L2924/0002 , H01L2924/00
摘要： Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features.
摘要翻译：提供了电压可编程的抗熔丝结构和方法，其包括位于介于两个相邻导电特征之间的电介质表面上的至少一个导电材料岛。在一个实施例中，反熔丝结构包括具有嵌入其中的至少两个相邻导电特征的电介质材料。至少一个导电材料岛位于介电材料的位于至少两个相邻导电特征之间的上表面上。电介质覆盖层位于电介质材料的暴露表面上，至少一个导电材料岛和至少两个相邻的导电特征。当反熔丝结构处于编程状态时，介电击穿路径存在于介电材料中，介电材料位于至少一个导电材料岛之下，该导电材料岛传导电流以电耦合两个相邻导电特征。

7. 发明授权

US07994042B2 Techniques for impeding reverse engineering 有权
标题翻译：阻止逆向工程的技术
公开(公告)号：US07994042B2
公开(公告)日：2011-08-09
申请号：US11924735
申请日：2007-10-26
申请人： Louis L. Hsu , Rajiv V. Joshi , David W. Kruger
发明人： Louis L. Hsu , Rajiv V. Joshi , David W. Kruger
IPC分类号： H01L21/00
CPC分类号： H01L21/76816 , H01L21/76825 , H01L21/76831 , H01L21/76834 , H01L23/573 , H01L27/02 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer.
摘要翻译：提供了反逆向工程技术。一方面，提供了一种在绝缘层中形成至少一个特征的方法。该方法包括以下步骤。离子选择性地植入绝缘层中，以在绝缘层内形成至少一个注入区域，所述注入离子被配置为改变通过植入区域内的绝缘层的蚀刻速率。蚀刻绝缘层，同时在植入区域内和植入区域外部形成至少一个空隙，其中通过绝缘层在植入区域内的蚀刻速率与通过绝缘体的蚀刻速率不同在植入区域外侧。空隙填充有至少一种导体材料以在绝缘层中形成特征。

8. 发明申请

US20110069425A1 MODULARIZED THREE-DIMENSIONAL CAPACITOR ARRAY 有权
标题翻译：模块化三维电容阵列
公开(公告)号：US20110069425A1
公开(公告)日：2011-03-24
申请号：US12565802
申请日：2009-09-24
申请人： Louis L. Hsu , Xu Ouyang , Chih-Chao Yang
发明人： Louis L. Hsu , Xu Ouyang , Chih-Chao Yang
IPC分类号： H01G4/38 , H01L21/02 , H03K17/687
CPC分类号： H01L28/40 , H01L22/14 , H01L22/22 , H01L22/34 , H01L23/5223 , H01L27/0688 , H01L27/0805 , H01L28/60 , H01L2924/0002 , Y10T307/865 , H01L2924/00
摘要： A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.
摘要翻译：模块化电容器阵列包括多个电容器模块。每个电容器模块包括电容器和被配置为电气断开电容器的开关装置。开关装置包括：感测单元，被配置为检测电容器的泄漏电平，使得如果泄漏电流超过预定电平，则开关装置电连接电容器。每个电容器模块可以包括单个电容器板，两个电容器板或多于两个的电容器板。泄漏传感器和开关装置用于电气断开任何电容器阵列的电容器模块，从而保护电容器阵列免于漏电。

9. 发明授权

US07855563B2 Robust cable connectivity test receiver for high-speed data receiver 有权
标题翻译：用于高速数据接收器的强大的电缆连接测试接收器
公开(公告)号：US07855563B2
公开(公告)日：2010-12-21
申请号：US11766268
申请日：2007-06-21
申请人： Huihao Xu , Louis L. Hsu , Kevin G. Kramer , James D. Rockrohr , Michael A. Sorna
发明人： Huihao Xu , Louis L. Hsu , Kevin G. Kramer , James D. Rockrohr , Michael A. Sorna
IPC分类号： G01R31/00 , H04B3/46
CPC分类号： G01R31/041 , G01R31/026
摘要： A system is provided for detecting a fault in a signal transmission path. In one embodiment, the system can include a variable amplitude signal attenuator which is operable to modify an input signal by variably attenuating a signal voltage swing of the input signal. Desirably, the input signal is attenuated only when transitioning from a high signal voltage level towards a low signal voltage level d variably, such that a larger high-to-low signal voltage swing is attenuated more than a smaller high-to-low signal voltage swing. Desirably, a comparator, which may apply hysteresis to the output signals, may detect a crossing of a reference voltage level by the modified input signal. In this way, when the comparator does not detect an expected crossing of the reference voltage level by the modified input signal, a determination can be made that a fault exists in the signal transmission path.
摘要翻译：提供了一种用于检测信号传输路径中的故障的系统。在一个实施例中，系统可以包括可变幅度信号衰减器，其可操作以通过可变地衰减输入信号的信号电压摆幅来修改输入信号。期望地，只有当从高信号电压电平转换到低信号电压电平d时，输入信号才被衰减，使得较高的高电平到低的信号电压摆幅比较小的高到低信号电压衰减摇摆。期望地，可能对输出信号施加迟滞的比较器可以检测参考电压电平与修改的输入信号的交叉。以这种方式，当比较器没有检测到通过修改的输入信号的参考电压电平的预期交叉时，可以确定在信号传输路径中存在故障。

10. 发明授权

US07804148B2 Opto-thermal mask including aligned thermal dissipative layer, reflective layer and transparent capping layer 失效
标题翻译：光热掩模包括对准的热耗散层，反射层和透明覆盖层
公开(公告)号：US07804148B2
公开(公告)日：2010-09-28
申请号：US11355799
申请日：2006-02-16
申请人： Louis L. Hsu , Jack A. Mandelman , Chandrasekhar Narayan , Chun-Yung Sung
发明人： Louis L. Hsu , Jack A. Mandelman , Chandrasekhar Narayan , Chun-Yung Sung
IPC分类号： H01L23/58 , H01L31/058 , H01L31/02 , H01L31/0232 , H01L31/024 , H01L21/033 , H01L21/00
CPC分类号： H01L21/268 , H01L21/84 , H01L27/1203 , H01L29/78603 , H01L2924/0002 , H01L2924/00
摘要： An opto-thermal annealing mask stack layer includes a thermal dissipative layer located over a substrate. A reflective layer is located upon the thermal dissipative layer. A transparent capping layer, that may have a thickness from about 10 to about 100 angstroms, is located upon the reflective layer. The opto-thermal annealing mask layer may be used as a gate electrode within a field effect device.
摘要翻译：光热退火掩模层叠层包括位于衬底上的散热层。反射层位于热耗散层上。可以具有约10至约100埃厚度的透明覆盖层位于反射层上。光热退火掩模层可以用作场效应器件中的栅电极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式