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1. 发明授权

US07041525B2 Three-dimensional island pixel photo-sensor 有权
公开(公告)号：US07041525B2
公开(公告)日：2006-05-09
申请号：US10751205
申请日：2004-01-02
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
IPC分类号： H01L21/66 , H01L21/00
CPC分类号： H01L27/14634 , H01L27/1463 , H01L27/14643
摘要： A method and structure for a photodiode array comprising a plurality of photodiode cores, light sensing sidewalls along an exterior of the cores, logic circuitry above the cores, trenches separating the cores, and a transparent material in the trenches is disclosed. With the invention, the sidewalls are perpendicular to the surface of the photodiode that receives incident light. The light sensing sidewalls comprise a junction region that causes electron transfer when struck with light. The sidewalls comprise four vertical sidewalls around each island core. The logic circuitry blocks light from the core so light is primarily only sensed by the sidewalls.

2. 发明授权

US07088074B2 System level device for battery and integrated circuit integration 有权
标题翻译：用于电池和集成电路集成的系统级装置
公开(公告)号：US07088074B2
公开(公告)日：2006-08-08
申请号：US10039541
申请日：2002-01-02
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
IPC分类号： H02J7/00
CPC分类号： H01M10/425 , H01L23/58 , H01L2224/16227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/15153 , H01L2924/19041 , H01L2924/19104 , H01L2924/30107 , H01M2/1066 , H01M2/204 , H01L2924/00014 , H01L2924/00
摘要： A system level device for battery and integrated circuit chip integration comprises at least one battery; at least one integrated circuit chip powered by the at least one battery; and a package connected to any of the at least one battery and the at least one integrated circuit chip, wherein the at least one battery connects to a pair of opposed upright ends of the package, wherein the at least one integrated circuit chip is disposed between the at least one battery and the package, and wherein the at least one integrated circuit chip lays on top of a portion of the package.
摘要翻译：用于电池和集成电路芯片集成的系统级装置包括至少一个电池; 由所述至少一个电池供电的至少一个集成电路芯片; 以及连接到所述至少一个电池和所述至少一个集成电路芯片中的任一个的封装，其中所述至少一个电池连接到所述封装的一对相对的直立端，其中所述至少一个集成电路芯片设置在所述至少一个电池和所述封装，并且其中所述至少一个集成电路芯片放置在所述封装的一部分的顶部上。

3. 发明授权

US06768063B2 Structure and method for shadow mask electrode 有权
标题翻译：荫罩电极的结构和方法
公开(公告)号：US06768063B2
公开(公告)日：2004-07-27
申请号：US09943827
申请日：2001-08-31
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
IPC分类号： H05K111
CPC分类号： H05K3/24 , G01N27/226 , H01L23/4824 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for an electrode device, whereby a second electrode is deposited on a first electrode such that there is an increase in the capacitive coupling between the pair of conductive electrodes. The electrodes are self-aligning such that the patterning manufacturing process is insensitive to variations in the positional placement of the pattern on the substrate. Moreover, a single lithographic masking layer is used for forming the pair of electrodes, which are electrically isolated. Finally, the first electrode is offset from the second electrode by a chemical surface modification of the first electrode, and an anisotropic deposition of the second electrode which is shadowed by the first electrode.
摘要翻译：一种电极装置的方法和结构，由此第二电极沉积在第一电极上，使得一对导电电极之间的电容耦合增加。电极是自对准的，使得图案化制造工艺对图案在衬底上的位置放置的变化不敏感。此外，单个光刻掩模层用于形成电隔离的一对电极。最后，第一电极通过第一电极的化学表面改性和由第一电极遮蔽的第二电极的各向异性沉积而偏离第二电极。

4. 发明授权

US07112502B2 Method to fabricate passive components using conductive polymer 有权
公开(公告)号：US07112502B2
公开(公告)日：2006-09-26
申请号：US10828374
申请日：2004-04-20
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
IPC分类号： H01L21/20
CPC分类号： H01C7/005 , H01C7/006 , H01C17/075 , H01G4/18 , H01G4/33 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L23/5328 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for an integrated circuit chip has a logic core which includes a plurality of insulating and conducting levels, an exterior conductor level and passive devices having a conductive polymer directly connected to the exterior conductor level. The passive devices contain RF devices which also includes resistor, capacitor, and/or inductor. The resistors can be serpentine resistors and the capacitors can be interdigitated capacitors.

5. 发明授权

US06958522B2 Method to fabricate passive components using conductive polymer 有权
标题翻译：使用导电聚合物制造无源元件的方法
公开(公告)号：US06958522B2
公开(公告)日：2005-10-25
申请号：US09897891
申请日：2001-07-05
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
IPC分类号： H01L27/06 , H01L29/00 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01C7/005 , H01C7/006 , H01C17/075 , H01G4/18 , H01G4/33 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L23/5328 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for an integrated circuit chip has a logic core which includes a plurality of insulating and conducting levels, an exterior conductor level and passive devices having a conductive polymer directly connected to the exterior conductor level. The passive devices contain RF devices which also includes resistor, capacitor, and/or inductor. The resistors can be serpentine resistors and the capacitors can be interdigitated capacitors.
摘要翻译：集成电路芯片的方法和结构具有包括多个绝缘和导电水平的逻辑芯，外部导体水平和具有直接连接到外部导体水平的导电聚合物的无源器件。无源器件包含还包括电阻器，电容器和/或电感器的RF器件。电阻器可以是蛇形电阻器，电容器可以是交错电容器。

6. 发明授权

US06720595B2 Three-dimensional island pixel photo-sensor 有权
标题翻译：三维岛像素光电传感器
公开(公告)号：US06720595B2
公开(公告)日：2004-04-13
申请号：US09922077
申请日：2001-08-06
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
IPC分类号： H01L31062
CPC分类号： H01L27/14634 , H01L27/1463 , H01L27/14643
摘要： A method and structure for a photodiode array comprising a plurality of photodiode cores, light sensing sidewalls along an exterior of the cores, logic circuitry above the cores, trenches separating the cores, and a transparent material in the trenches is disclosed. With the invention, the sidewalls are perpendicular to the surface of the photodiode that receives incident light. The light sensing sidewalls comprise a junction region that causes electron transfer when struck with light. The sidewalls comprise four vertical sidewalls around each island core. The logic circuitry blocks light from the core so light is primarily only sensed by the sidewalls.
摘要翻译：公开了一种用于光电二极管阵列的方法和结构，该阵列包括多个光电二极管芯，沿芯的外部的感光侧壁，芯之上的逻辑电路，分离芯的沟槽和沟槽中的透明材料。利用本发明，侧壁垂直于接收入射光的光电二极管的表面。感光侧壁包括当用光照射时引起电子转移的结区域。侧壁包围围绕每个岛芯的四个垂直侧壁。逻辑电路阻挡来自芯的光，因此光仅主要由侧壁感测。

7. 发明授权

US07023528B2 Hybrid electronic mask 有权
标题翻译：混合电子面具
公开(公告)号：US07023528B2
公开(公告)日：2006-04-04
申请号：US10167327
申请日：2002-06-10
申请人： Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
发明人： Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
IPC分类号： G03B27/72 , G03B27/54 , G03B27/42
CPC分类号： G03F1/26 , G03F7/2014 , G03F7/70291
摘要： An electronically programmable mask for lithography has an array of individually controllable light sources aligned with an array of individually controllable liquid crystals, so that individual pixels may be turned on or off and phase-shifted to provide a desired light intensity distribution on a wafer. The mask may be used in a contact printing mode or in a reduction projection mode.
摘要翻译：用于光刻的电子可编程掩模具有与独立可控液晶阵列对准的独立可控光源的阵列，使得各个像素可以被导通或截止并相移以在晶片上提供期望的光强分布。掩模可以以接触印刷模式或缩小投影模式使用。

8. 发明授权

US06452110B1 Patterning microelectronic features without using photoresists 失效
标题翻译：图案化微电子特征，而不使用光致抗蚀剂
公开(公告)号：US06452110B1
公开(公告)日：2002-09-17
申请号：US09897889
申请日：2001-07-05
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Keith Kwong Hon Wong
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Keith Kwong Hon Wong
IPC分类号： H05K109
CPC分类号： H05K3/02 , H01L21/288 , H01L21/32134 , H01L21/76885 , Y10T29/49155 , Y10T29/49156
摘要： A method and structure for producing metallic polymer conductor lines comprising of an alternative methodology to a traditional damascene approach, called a cloisonne or inverse damascene approach. The cloisonne approach comprises the steps of coating a photosensitive polymer such as pyrrole or aniline with a silver salt on a semiconductor substrate. Using standard photolithography and resist developing techniques, the conducting polymer is exposed to a wet chemical developer, removing a portion of the exposed conducting polymer region, leaving only conducting polymer lines on top of the substrate. Next, an insulating dielectric layer is deposited over the entire structure and a chemical mechanical polish planarization of the insulator is performed creating the conducting polymer lines. Included in another aspect of the invention is a method and structure for a self-planarizing interconnect material comprising a conductive polymer thereby reducing the number of processing steps relative to the prior art.
摘要翻译：一种用于生产金属聚合物导体线的方法和结构，其包括传统大马士革方法的替代方法，称为景泰蓝或逆大马士革方法。景泰蓝方法包括在半导体衬底上用银盐将光敏聚合物如吡咯或苯胺涂覆的步骤。使用标准光刻和抗蚀显影技术，将导电聚合物暴露于湿化学显影剂，除去暴露的导电聚合物区域的一部分，仅在基底顶部留下导电聚合物线。接下来，在整个结构上沉积绝缘电介质层，并进行绝缘体的化学机械抛光平面化，产生导电聚合物线。包括在本发明的另一方面中的是一种用于自平坦化互连材料的方法和结构，其包括导电聚合物，从而减少相对于现有技术的加工步骤的数量。

9. 发明授权

US06355531B1 Method for fabricating semiconductor devices with different properties using maskless process 失效
标题翻译：使用无掩模工艺制造具有不同特性的半导体器件的方法
公开(公告)号：US06355531B1
公开(公告)日：2002-03-12
申请号：US09634225
申请日：2000-08-09
申请人： Jack A. Mandelman , Louis L. Hsu , Carl J. Radens , William R. Tonti , Li-Kong Wang
发明人： Jack A. Mandelman , Louis L. Hsu , Carl J. Radens , William R. Tonti , Li-Kong Wang
IPC分类号： H01L218236
CPC分类号： H01L21/823892 , H01L21/823807 , H01L21/82385 , Y10S438/981
摘要： A method is provided for fabricating semiconductor devices having different properties on a common semiconductor substrate. The method includes the steps of (a) forming N openings on the semiconductor substrate, wherein each opening is corresponding to a channel region of each semiconductor device, (b) forming oxide layers of an ith type on surfaces of the N openings, (c) depositing gate conductor material of an ith type over structure of the semiconductor devices, the gate conductor material of the ith type having a gate conductor work-function of an ith type, (d) removing the gate conductor material of the ith type such that a predetermined amount of the gate conductor material of the ith type remains in an ith opening to form a gate conductor material layer of the ith type on top surface in the ith opening and the gate conductor material of the ith type deposited in the structure other than the ith opening is removed, (e) removing the oxide layers of the ith type from openings other than the ith opening, (f) repeating the steps of (a) through (e) from “i=1” to “i=N”, and (g) forming at least one layer on surface of each of N gate conductor material layers in the N openings to form a gate conductor, whereby the N semiconductor devices have N gate conductors, respectively, wherein the N gate conductors have N types of gate conductor work-functions. The semiconductor devices also have channel regions of which doping levels are different from each other by implanting the channel regions with different types of implants.
摘要翻译：提供了一种在公共半导体衬底上制造具有不同特性的半导体器件的方法。该方法包括以下步骤：（a）在半导体衬底上形成N个开口，其中每个开口对应于每个半导体器件的沟道区，（b）在N个开口的表面上形成第i个类型的氧化物层，（c ）沉积所述半导体器件的第i型结构的栅极导体材料，所述第i型栅极导体材料具有第i类型的栅极导体功函数，（d）去除所述第i种类型的栅极导体材料，使得第i个类型的栅极导体材料的预定量保持在第i个开口中，以在第i个开口的顶表面上形成第i型的栅极导体材料层，并且沉积在除第除去第i个开口，（e）从第i个开口以外的开口除去第i个类型的氧化物层，（f）重复步骤（a）至（e）从“i = 1”到“i = N “，（g）在其上形成至少一层在N个开口中的N个栅极导体材料层中的每一个的表面形成栅极导体，由此N个半导体器件分别具有N个栅极导体，其中N个栅极导体具有N种类型的栅极导体功函数。半导体器件还具有通过用不同类型的植入物植入沟道区域而使掺杂水平彼此不同的沟道区域。

10. 发明授权

US06670234B2 Method of integrating volatile and non-volatile memory cells on the same substrate and a semiconductor memory device thereof 失效
标题翻译：将易失性和非易失性存储单元集成在同一衬底上的方法及其半导体存储器件
公开(公告)号：US06670234B2
公开(公告)日：2003-12-30
申请号：US09887403
申请日：2001-06-22
申请人： Louis L. Hsu , Carl J. Radens , Li-Kong Wang
发明人： Louis L. Hsu , Carl J. Radens , Li-Kong Wang
IPC分类号： H01L2100
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/1052 , H01L27/10861 , H01L27/10894 , H01L27/11546
摘要： A method for fabricating DRAM and flash memory cells on a single chip includes providing a silicon substrate, forming a trench capacitor for each of the DRAM cells in the silicon substrate, forming isolation regions in the silicon substrate which are electrically isolated from each other, forming first type wells for DRAM and flash memory cells at first predetermined regions of the silicon substrate by implanting a first type impurity in the first predetermined regions, forming second type wells for DRAM and flash memory cells at second predetermined regions in the first type wells by implanting a second type impurity in the second predetermined regions, forming oxide layers for DRAM and flash memory cells on the second type wells, forming gate electrodes for DRAM and flash memory cells on the oxide layers for DRAM and flash memory cells, and forming source and drain regions for DRAM and flash memory cells in the respective second type wells for DRAM and flash memory cells, in which the source and drain regions are associated with each of the gate electrodes for DRAM and flash memory cells.
摘要翻译：在单个芯片上制造DRAM和闪存单元的方法包括提供硅衬底，为硅衬底中的每个DRAM单元形成沟槽电容器，形成硅衬底中彼此电隔离的隔离区域，形成通过在第一预定区域中注入第一种类型的杂质，在第一种类型的阱中的第二预定区域形成用于DRAM和闪速存储单元的第二类型阱，通过植入在第二预定区域中形成第二类型杂质，在第二类型阱上形成用于DRAM和闪存单元的氧化物层，在DRAM和闪存单元的氧化物层上形成用于DRAM的闪存存储单元的栅电极，以及形成源极和漏极用于DRAM和闪速存储器单元的相应的第二类型阱中的用于DRAM和闪存单元的区域 e源极和漏极区域与用于DRAM和闪存单元的每个栅电极相关联。

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