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1. 发明授权

US07983069B2 Write operations for phase-change-material memory 有权
标题翻译：相变材料存储器的写操作
公开(公告)号：US07983069B2
公开(公告)日：2011-07-19
申请号：US12146128
申请日：2008-06-25
申请人： Louis L. C. Hsu , Brian L. Ji , Chung Hon Lam
发明人： Louis L. C. Hsu , Brian L. Ji , Chung Hon Lam
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0076 , G11C2013/0078 , G11C2213/79
摘要： Improved write operation techniques for use in phase-change-material (PCM) memory devices are disclosed. By way of one example, a method of performing a write operation in a phase-change-material memory cell, the memory cell having a set phase and a reset phase associated therewith, comprises the following steps. A word-line associated with the memory cell is monitored. Performance of a write operation to the memory cell for the set phase is initiated when the word-line is activated. The write operation to the memory cell for the set phase may then be continued when valid data for the set phase is available. A write operation to the memory cell for the reset phase may be performed when valid data for the reset phase is available. Other improved PCM write operation techniques are disclosed.
摘要翻译：公开了用于相变材料（PCM）存储器件的改进的写操作技术。作为一个示例，在相变材料存储器单元中执行写入操作的方法，具有设置相位和与其相关联的复位阶段的存储器单元包括以下步骤。监视与存储器单元相关联的字线。当字线被激活时，启动对设置阶段的存储单元的写操作的执行。然后可以在设定阶段的有效数据可用时继续对设定阶段的存储单元的写入操作。当复位阶段的有效数据可用时，可以执行对复位阶段的存储单元的写操作。公开了其它改进的PCM写操作技术。

2. 发明授权

US07319608B2 Non-volatile content addressable memory using phase-change-material memory elements 有权
标题翻译：使用相变材料存储元件的非易失性内容可寻址存储器
公开(公告)号：US07319608B2
公开(公告)日：2008-01-15
申请号：US11172473
申请日：2005-06-30
申请人： Louis L. C. Hsu , Brian L. Ji , Chung Hon Lam , Hon-Sum Philip Wong
发明人： Louis L. C. Hsu , Brian L. Ji , Chung Hon Lam , Hon-Sum Philip Wong
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C15/046
摘要： A non-volatile content addressable memory cell comprises: a first phase change material element, the first phase change material element having one end connected to a match-line; a first transistor, the first transistor having a gate connected to a word-line, a source connected to a true bit-read-write-search-line, and a drain connected to another end of the first phase change material element; a second phase change material element, the second phase change material element having one end connected to the match-line; and a second transistor, the second transistor having a gate connected to the word-line, a source connected to a complementary bit-read-write-search-line, and a drain connected to another end of the second phase change material element.
摘要翻译：非易失性内容可寻址存储单元包括：第一相变材料元件，所述第一相变材料元件具有连接到匹配线的一端; 第一晶体管，第一晶体管具有连接到字线的栅极，连接到真位读 - 写搜索线的源极和连接到第一相变材料元件的另一端的漏极; 第二相变材料元件，所述第二相变材料元件具有连接到所述匹配线的一端; 以及第二晶体管，所述第二晶体管具有连接到所述字线的栅极，连接到互补位读写搜索线的源极和连接到所述第二相变材料元件的另一端的漏极。

3. 发明授权

US07460389B2 Write operations for phase-change-material memory 有权
标题翻译：相变材料存储器的写操作
公开(公告)号：US07460389B2
公开(公告)日：2008-12-02
申请号：US11193878
申请日：2005-07-29
申请人： Louis L. C. Hsu , Brian L. Ji , Chung Hon Lam
发明人： Louis L. C. Hsu , Brian L. Ji , Chung Hon Lam
IPC分类号： G11C13/00 , G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0076 , G11C2013/0078 , G11C2213/79
摘要： Improved write operation techniques for use in phase-change-material (PCM) memory devices are disclosed. By way of one example, a method of performing a write operation in a phase-change-material memory cell, the memory cell having a set phase and a reset phase associated therewith, comprises the following steps. A word-line associated with the memory cell is monitored. Performance of a write operation to the memory cell for the set phase is initiated when the word-line is activated. The write operation to the memory cell for the set phase may then be continued when valid data for the set phase is available. A write operation to the memory cell for the reset phase may be performed when valid data for the reset phase is available. Other improved PCM write operation techniques are disclosed.
摘要翻译：公开了用于相变材料（PCM）存储器件的改进的写操作技术。作为一个示例，在相变材料存储器单元中执行写入操作的方法，具有设置相位和与其相关联的复位阶段的存储器单元包括以下步骤。监视与存储器单元相关联的字线。当字线被激活时，启动对设置阶段的存储单元的写操作的执行。然后可以在设定阶段的有效数据可用时继续对设定阶段的存储单元的写入操作。当复位阶段的有效数据可用时，可以执行对复位阶段的存储单元的写操作。公开了其它改进的PCM写操作技术。

4. 发明申请

US20080253177A1 Write Operations for Phase-Change-Material Memory 有权
标题翻译：相变材料存储器的写操作
公开(公告)号：US20080253177A1
公开(公告)日：2008-10-16
申请号：US12146128
申请日：2008-06-25
申请人： Louis L.C. Hsu , Brian L. Ji , Chung Hon Lam
发明人： Louis L.C. Hsu , Brian L. Ji , Chung Hon Lam
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0076 , G11C2013/0078 , G11C2213/79
摘要： Improved write operation techniques for use in phase-change-material (PCM) memory devices are disclosed. By way of one example, a method of performing a write operation in a phase-change-material memory cell, the memory cell having a set phase and a reset phase associated therewith, comprises the following steps. A word-line associated with the memory cell is monitored. Performance of a write operation to the memory cell for the set phase is initiated when the word-line is activated. The write operation to the memory cell for the set phase may then be continued when valid data for the set phase is available. A write operation to the memory cell for the reset phase may be performed when valid data for the reset phase is available. Other improved PCM write operation techniques are disclosed.
摘要翻译：公开了用于相变材料（PCM）存储器件的改进的写操作技术。作为一个示例，在相变材料存储器单元中执行写入操作的方法，具有设置相位和与其相关联的复位阶段的存储器单元包括以下步骤。监视与存储器单元相关联的字线。当字线被激活时，启动对设置阶段的存储单元的写操作的执行。然后可以在设定阶段的有效数据可用时继续对设定阶段的存储单元的写入操作。当复位阶段的有效数据可用时，可以执行对复位阶段的存储单元的写操作。公开了其它改进的PCM写操作技术。

5. 发明授权

US07233177B2 Precision tuning of a phase-change resistive element 有权
标题翻译：相变电阻元件的精密调谐
公开(公告)号：US07233177B2
公开(公告)日：2007-06-19
申请号：US11098078
申请日：2005-04-04
申请人： Louis C. Hsu , Brian L. Ji , Chung Hon Lam
发明人： Louis C. Hsu , Brian L. Ji , Chung Hon Lam
IPC分类号： H03K5/22 , G06G7/28
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0064 , G11C2013/0054
摘要： The present invention comprises a method and structure for programming an on-chip phase-change resistor to a target resistance. Using an off-chip precision resistor as a reference, a state-machine determines a difference between the resistance of an on-chip resistor and the target resistance. Based upon this difference, the state machine directs a pulse generator to apply set or reset pulses to the on-chip resistor in order to decrease or increase, respectively, the resistance of the resistor, as necessary. In order to program the resistance of the phase-change resistor to a tight tolerance, it is successively reset and set by applying progressively decreasing numbers of reset pulses and set pulses, respectively, until the number of set pulses is equal to one and the target resistance of the on-chip resistor is reached.
摘要翻译：本发明包括用于将片上相变电阻器编程为目标电阻的方法和结构。使用片外精密电阻器作为参考，状态机确定片上电阻器的电阻与目标电阻之间的差。基于这种差异，状态机引导脉冲发生器将片上电阻器设置或复位脉冲施加到片上电阻器，以便根据需要分别降低或增加电阻器的电阻。为了将相变电阻器的电阻编程为严格的公差，通过分别逐渐递减的复位脉冲数和设定脉冲数来连续复位和设置，直到设定脉冲数等于1，目标值达到片上电阻的电阻。

6. 发明授权

US08766410B2 Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors 有权
标题翻译：嵌入式DRAM集成电路，具有极薄的绝缘体上硅传导晶体管
公开(公告)号：US08766410B2
公开(公告)日：2014-07-01
申请号：US13153806
申请日：2011-06-06
申请人： Jin Cai , Josephine Chang , Leland Chang , Brian L. Ji , Steven John Koester , Amlan Majumdar
发明人： Jin Cai , Josephine Chang , Leland Chang , Brian L. Ji , Steven John Koester , Amlan Majumdar
IPC分类号： H01L23/58
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10894
摘要： Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.
摘要翻译：提供具有组合的存储器和逻辑功能的集成电路。一方面，提供集成电路。集成电路包括：衬底，其包括在BOX层上的硅层，其中硅层的选择区域具有在约3纳米和约20纳米之间的厚度; 至少一个eDRAM单元包括：至少一个传输晶体管，其具有形成在所述硅层的所述选择区域中的传输晶体管源极区域，传输晶体管漏极区域和传输晶体管沟道区域; 以及电连接到传输晶体管的电容器。

7. 发明授权

US08212537B2 Integratable efficient switching down converter 有权
标题翻译：可集成的高效切换转换器
公开(公告)号：US08212537B2
公开(公告)日：2012-07-03
申请号：US12508235
申请日：2009-07-23
申请人： Gary D. Carpenter , Wonyoung Kim , Brian L. Ji
发明人： Gary D. Carpenter , Wonyoung Kim , Brian L. Ji
IPC分类号： G05F1/10 , G05F1/40
CPC分类号： H02M3/158
摘要： A converter circuit and methods for operating the same. The converter circuit includes a supply voltage, a capacitor, an inductor, and four stacked switching elements. Each switching element is adjustable from a low resistance state to a high resistance state by a control signal. The inductor outputs current to a circuit load. The circuit may be operated in a first mode such that the output is adjustable between the supply voltage and half the supply voltage. Alternatively, in a second mode of operation, the output is adjustable from half the supply voltage to a ground voltage.
摘要翻译： A转换器电路及其操作方法。转换器电路包括电源电压，电容器，电感器和四个堆叠的开关元件。每个开关元件可通过控制信号从低电阻状态调节到高电阻状态。电感将电流输出到电路负载。电路可以在第一模式下操作，使得输出在电源电压和电源电压的一半之间是可调节的。或者，在第二操作模式中，输出可从电源电压的一半调整到接地电压。

8. 发明授权

US08198174B2 Air channel interconnects for 3-D integration 有权
标题翻译：空气通道互连用于3-D集成
公开(公告)号：US08198174B2
公开(公告)日：2012-06-12
申请号：US12536176
申请日：2009-08-05
申请人： Louis L. Hsu , Brian L. Ji , Fei Liu , Conal E. Murray
发明人： Louis L. Hsu , Brian L. Ji , Fei Liu , Conal E. Murray
IPC分类号： H01L21/44
CPC分类号： H01L23/467 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional (3D) chip stack structure and method of fabricating the structure thereof are provided. The 3D chip stack structure includes a plurality of vertically stacked chips which are interconnected and bonded together, wherein each of the vertically stacked chips include one or more IC device strata. The 3D chip stack structure further includes an air channel interconnect network embedded within the chip stack structure, and wherein the air channel interconnect network is formed in between at least two wafers bonded to each other of the vertically stacked wafers and in between at least two bonded wafers of the vertically stacked wafers at a bonding interface thereof. In addition, the 3D chip stack structure further includes one or more openings in a peripheral region of the chip stack structure that lead into and out of the air channel interconnect network, so that air can flow into and out of the air channel interconnect network through the one or more openings to remove heat from the chip stack structure.
摘要翻译：提供三维（3D）芯片堆叠结构及其结构的制造方法。 3D芯片堆叠结构包括互连并结合在一起的多个垂直堆叠的芯片，其中每个垂直堆叠的芯片包括一个或多个IC器件层。 3D芯片堆叠结构还包括嵌入在芯片堆叠结构内的空气通道互连网络，并且其中空气通道互连网络形成在至少两个晶片之间，所述至少两个晶片彼此接合在垂直堆叠的晶片之间，并且在至少两个结合在其接合界面处的垂直堆叠的晶片的晶片。此外，3D芯片堆叠结构还包括在芯片堆叠结构的外围区域中的一个或多个开口，其引入和流出空气通道互连网络，使得空气可以流入和流出空气通道互连网络，通过一个或多个开口以从芯片堆叠结构移除热量。

9. 发明授权

US07985633B2 Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors 有权
标题翻译：嵌入式DRAM集成电路，具有极薄的绝缘体上硅传导晶体管
公开(公告)号：US07985633B2
公开(公告)日：2011-07-26
申请号：US11929943
申请日：2007-10-30
申请人： Jin Cai , Josephine Chang , Leland Chang , Brian L. Ji , Steven John Koester , Amlan Majumdar
发明人： Jin Cai , Josephine Chang , Leland Chang , Brian L. Ji , Steven John Koester , Amlan Majumdar
IPC分类号： H01L21/84
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10894
摘要： Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.
摘要翻译：提供具有组合的存储器和逻辑功能的集成电路。一方面，提供集成电路。集成电路包括：衬底，其包括在BOX层上的硅层，其中硅层的选择区域具有在约3纳米和约20纳米之间的厚度; 至少一个eDRAM单元包括：至少一个传输晶体管，其具有形成在所述硅层的所述选择区域中的传输晶体管源极区域，传输晶体管漏极区域和传输晶体管沟道区域; 以及电连接到传输晶体管的电容器。

10. 发明申请

US20110108900A1 BI-DIRECTIONAL SELF-ALIGNED FET CAPACITOR 有权
标题翻译：双向自对准FET电容器
公开(公告)号：US20110108900A1
公开(公告)日：2011-05-12
申请号：US12616861
申请日：2009-11-12
申请人： Leland Chang , Chung-Hsun Lin , Brian L. Ji , Jeffrey W. Sleight
发明人： Leland Chang , Chung-Hsun Lin , Brian L. Ji , Jeffrey W. Sleight
IPC分类号： H01L29/94 , H01L21/334
CPC分类号： H01L27/0811 , H01L21/26586 , H01L21/823418 , H01L21/84 , H01L27/1203 , H01L29/66181 , H01L29/94
摘要： A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack.
摘要翻译：形成场效应晶体管（FET）电容器的方法包括：形成沟道区; 在沟道区上形成栅叠层; 在所述栅极堆叠的第一侧上形成第一延伸区域，所述第一延伸区域通过以第一角度注入第一掺杂材料形成，使得阴极区域存在于所述栅极叠层的第二侧上; 以及在所述栅极堆叠的第二侧上形成第二延伸区域，所述第二延伸区域通过以第二角度注入第二掺杂材料形成，使得阴极区域存在于所述栅极叠层的第一侧上。

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