专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07319608B2 Non-volatile content addressable memory using phase-change-material memory elements 有权
标题翻译：使用相变材料存储元件的非易失性内容可寻址存储器
公开(公告)号：US07319608B2
公开(公告)日：2008-01-15
申请号：US11172473
申请日：2005-06-30
申请人： Louis L. C. Hsu , Brian L. Ji , Chung Hon Lam , Hon-Sum Philip Wong
发明人： Louis L. C. Hsu , Brian L. Ji , Chung Hon Lam , Hon-Sum Philip Wong
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C15/046
摘要： A non-volatile content addressable memory cell comprises: a first phase change material element, the first phase change material element having one end connected to a match-line; a first transistor, the first transistor having a gate connected to a word-line, a source connected to a true bit-read-write-search-line, and a drain connected to another end of the first phase change material element; a second phase change material element, the second phase change material element having one end connected to the match-line; and a second transistor, the second transistor having a gate connected to the word-line, a source connected to a complementary bit-read-write-search-line, and a drain connected to another end of the second phase change material element.
摘要翻译：非易失性内容可寻址存储单元包括：第一相变材料元件，所述第一相变材料元件具有连接到匹配线的一端; 第一晶体管，第一晶体管具有连接到字线的栅极，连接到真位读 - 写搜索线的源极和连接到第一相变材料元件的另一端的漏极; 第二相变材料元件，所述第二相变材料元件具有连接到所述匹配线的一端; 以及第二晶体管，所述第二晶体管具有连接到所述字线的栅极，连接到互补位读写搜索线的源极和连接到所述第二相变材料元件的另一端的漏极。

2. 发明授权

US07460389B2 Write operations for phase-change-material memory 有权
标题翻译：相变材料存储器的写操作
公开(公告)号：US07460389B2
公开(公告)日：2008-12-02
申请号：US11193878
申请日：2005-07-29
申请人： Louis L. C. Hsu , Brian L. Ji , Chung Hon Lam
发明人： Louis L. C. Hsu , Brian L. Ji , Chung Hon Lam
IPC分类号： G11C13/00 , G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0076 , G11C2013/0078 , G11C2213/79
摘要： Improved write operation techniques for use in phase-change-material (PCM) memory devices are disclosed. By way of one example, a method of performing a write operation in a phase-change-material memory cell, the memory cell having a set phase and a reset phase associated therewith, comprises the following steps. A word-line associated with the memory cell is monitored. Performance of a write operation to the memory cell for the set phase is initiated when the word-line is activated. The write operation to the memory cell for the set phase may then be continued when valid data for the set phase is available. A write operation to the memory cell for the reset phase may be performed when valid data for the reset phase is available. Other improved PCM write operation techniques are disclosed.
摘要翻译：公开了用于相变材料（PCM）存储器件的改进的写操作技术。作为一个示例，在相变材料存储器单元中执行写入操作的方法，具有设置相位和与其相关联的复位阶段的存储器单元包括以下步骤。监视与存储器单元相关联的字线。当字线被激活时，启动对设置阶段的存储单元的写操作的执行。然后可以在设定阶段的有效数据可用时继续对设定阶段的存储单元的写入操作。当复位阶段的有效数据可用时，可以执行对复位阶段的存储单元的写操作。公开了其它改进的PCM写操作技术。

3. 发明授权

US07983069B2 Write operations for phase-change-material memory 有权
标题翻译：相变材料存储器的写操作
公开(公告)号：US07983069B2
公开(公告)日：2011-07-19
申请号：US12146128
申请日：2008-06-25
申请人： Louis L. C. Hsu , Brian L. Ji , Chung Hon Lam
发明人： Louis L. C. Hsu , Brian L. Ji , Chung Hon Lam
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0076 , G11C2013/0078 , G11C2213/79
摘要： Improved write operation techniques for use in phase-change-material (PCM) memory devices are disclosed. By way of one example, a method of performing a write operation in a phase-change-material memory cell, the memory cell having a set phase and a reset phase associated therewith, comprises the following steps. A word-line associated with the memory cell is monitored. Performance of a write operation to the memory cell for the set phase is initiated when the word-line is activated. The write operation to the memory cell for the set phase may then be continued when valid data for the set phase is available. A write operation to the memory cell for the reset phase may be performed when valid data for the reset phase is available. Other improved PCM write operation techniques are disclosed.
摘要翻译：公开了用于相变材料（PCM）存储器件的改进的写操作技术。作为一个示例，在相变材料存储器单元中执行写入操作的方法，具有设置相位和与其相关联的复位阶段的存储器单元包括以下步骤。监视与存储器单元相关联的字线。当字线被激活时，启动对设置阶段的存储单元的写操作的执行。然后可以在设定阶段的有效数据可用时继续对设定阶段的存储单元的写入操作。当复位阶段的有效数据可用时，可以执行对复位阶段的存储单元的写操作。公开了其它改进的PCM写操作技术。

4. 发明授权

US07485891B2 Multi-bit phase change memory cell and multi-bit phase change memory including the same, method of forming a multi-bit phase change memory, and method of programming a multi-bit phase change memory 失效
标题翻译：包括相同的多位相变存储单元和多位相变存储器，形成多位相变存储器的方法，以及编程多位相变存储器的方法
公开(公告)号：US07485891B2
公开(公告)日：2009-02-03
申请号：US10718070
申请日：2003-11-20
申请人： Hendrik F. Hamann , Chung Hon Lam , Michelle Leigh Steen , Hon-Sum Philip Wong
发明人： Hendrik F. Hamann , Chung Hon Lam , Michelle Leigh Steen , Hon-Sum Philip Wong
IPC分类号： H01L21/302
CPC分类号： H01L45/06 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C2213/71 , H01L27/2463 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： A multi-bit phase change memory cell including a stack of a plurality of conductive layers and a plurality of phase change material layers, each of the phase change material layers disposed between a corresponding pair of conductive layers and having electrical resistances that are different from one another.
摘要翻译：一种多位相变存储单元，包括多个导电层和多个相变材料层的堆叠，每个相变材料层设置在相应的一对导电层之间并且具有不同于一个导电层的电阻另一个。

5. 发明申请

US20080253177A1 Write Operations for Phase-Change-Material Memory 有权
标题翻译：相变材料存储器的写操作
公开(公告)号：US20080253177A1
公开(公告)日：2008-10-16
申请号：US12146128
申请日：2008-06-25
申请人： Louis L.C. Hsu , Brian L. Ji , Chung Hon Lam
发明人： Louis L.C. Hsu , Brian L. Ji , Chung Hon Lam
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0076 , G11C2013/0078 , G11C2213/79
摘要： Improved write operation techniques for use in phase-change-material (PCM) memory devices are disclosed. By way of one example, a method of performing a write operation in a phase-change-material memory cell, the memory cell having a set phase and a reset phase associated therewith, comprises the following steps. A word-line associated with the memory cell is monitored. Performance of a write operation to the memory cell for the set phase is initiated when the word-line is activated. The write operation to the memory cell for the set phase may then be continued when valid data for the set phase is available. A write operation to the memory cell for the reset phase may be performed when valid data for the reset phase is available. Other improved PCM write operation techniques are disclosed.
摘要翻译：公开了用于相变材料（PCM）存储器件的改进的写操作技术。作为一个示例，在相变材料存储器单元中执行写入操作的方法，具有设置相位和与其相关联的复位阶段的存储器单元包括以下步骤。监视与存储器单元相关联的字线。当字线被激活时，启动对设置阶段的存储单元的写操作的执行。然后可以在设定阶段的有效数据可用时继续对设定阶段的存储单元的写入操作。当复位阶段的有效数据可用时，可以执行对复位阶段的存储单元的写操作。公开了其它改进的PCM写操作技术。

6. 发明授权

US07233177B2 Precision tuning of a phase-change resistive element 有权
标题翻译：相变电阻元件的精密调谐
公开(公告)号：US07233177B2
公开(公告)日：2007-06-19
申请号：US11098078
申请日：2005-04-04
申请人： Louis C. Hsu , Brian L. Ji , Chung Hon Lam
发明人： Louis C. Hsu , Brian L. Ji , Chung Hon Lam
IPC分类号： H03K5/22 , G06G7/28
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0064 , G11C2013/0054
摘要： The present invention comprises a method and structure for programming an on-chip phase-change resistor to a target resistance. Using an off-chip precision resistor as a reference, a state-machine determines a difference between the resistance of an on-chip resistor and the target resistance. Based upon this difference, the state machine directs a pulse generator to apply set or reset pulses to the on-chip resistor in order to decrease or increase, respectively, the resistance of the resistor, as necessary. In order to program the resistance of the phase-change resistor to a tight tolerance, it is successively reset and set by applying progressively decreasing numbers of reset pulses and set pulses, respectively, until the number of set pulses is equal to one and the target resistance of the on-chip resistor is reached.
摘要翻译：本发明包括用于将片上相变电阻器编程为目标电阻的方法和结构。使用片外精密电阻器作为参考，状态机确定片上电阻器的电阻与目标电阻之间的差。基于这种差异，状态机引导脉冲发生器将片上电阻器设置或复位脉冲施加到片上电阻器，以便根据需要分别降低或增加电阻器的电阻。为了将相变电阻器的电阻编程为严格的公差，通过分别逐渐递减的复位脉冲数和设定脉冲数来连续复位和设置，直到设定脉冲数等于1，目标值达到片上电阻的电阻。

7. 发明授权

US08445313B2 Method for forming a self-aligned bit line for PCRAM and self-aligned etch back process 失效
标题翻译：用于形成PCRAM和自对准回蚀工艺的自对准位线的方法
公开(公告)号：US08445313B2
公开(公告)日：2013-05-21
申请号：US13546684
申请日：2012-07-11
申请人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
发明人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
IPC分类号： H01L21/00
CPC分类号： H01L45/06 , H01L45/144 , H01L45/1608 , H01L45/1683
摘要： A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.
摘要翻译：一种形成与相变材料对准的位线的方法，包括在下电极的一部分上形成牺牲材料的基座并且形成与所述牺牲材料相邻的至少一个电介质材料，其中所述至少一种电介质材料具有上表面与牺牲材料的基座的上表面基本共面。牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。还提供了自对准的回蚀工艺。

8. 发明申请

US20120202333A1 METHOD FOR FORMING A SELF-ALIGNED BIT LINE FOR PCRAM AND SELF-ALIGNED ETCH BACK PROCESS 有权
标题翻译：用于形成用于PCRAM和自对准回退过程的自对准位线的方法
公开(公告)号：US20120202333A1
公开(公告)日：2012-08-09
申请号：US13020051
申请日：2011-02-03
申请人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
发明人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
IPC分类号： H01L21/02
CPC分类号： H01L45/06 , H01L45/144 , H01L45/1608 , H01L45/1683
摘要： A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and fowling at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.
摘要翻译：一种形成与相变材料对准的位线的方法，其包括在下电极的一部分上形成牺牲材料的基座并且与邻近所述牺牲材料的至少一个电介质材料相连，其中所述至少一种电介质材料具有上表面与牺牲材料的基座的上表面基本共面。牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。还提供了自对准的回蚀工艺。

9. 发明授权

US08238149B2 Methods and apparatus for reducing defect bits in phase change memory 有权
标题翻译：用于减少相变存储器中缺陷位的方法和装置
公开(公告)号：US08238149B2
公开(公告)日：2012-08-07
申请号：US12715802
申请日：2010-03-02
申请人： Yen-Hao Shih , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
发明人： Yen-Hao Shih , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C29/70 , G11C2213/79
摘要： Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics.
摘要翻译：相位变化存储器件和这里描述的操作方法基于以下发现：在施加到相变存储器单元以建立高电阻复位状态的初始高电流操作之后，存储器单元的电流 - 电压（IV）行为可以使用不同的偏置电压来检测存储器单元是否具有差的数据保留特性的缺陷单元。

10. 发明申请

US20120193599A1 PHASE CHANGE MEMORY CELL ARRAY WITH SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING 有权
标题翻译：相变式存储单元阵列与自适应底层电极及其制造方法
公开(公告)号：US20120193599A1
公开(公告)日：2012-08-02
申请号：US13445194
申请日：2012-04-12
申请人： Hsiang-Lan Lung , Chung Hon Lam , Matthew J. Breitwisch
发明人： Hsiang-Lan Lung , Chung Hon Lam , Matthew J. Breitwisch
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： An array of phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming a patterning layer on the separation layer and forming an array of mask openings in the patterning layer using lithographic process. Etch masks are formed within the mask openings by a process that compensates for variation in the size of the mask openings that result from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings exposing the underlying contacts. Electrode material is deposited within the electrode openings; and memory elements are formed over the bottom electrodes. Finally, bit lines are formed over the memory elements to complete the memory cells. In the resulting memory array, the critical dimension of the top surface of bottom electrode varies less than the width of the memory elements in the mask openings.
摘要翻译：通过在触点阵列上形成分离层，在分离层上形成图形层并使用光刻工艺在图案形成层中形成掩模开口阵列来制造相变存储器单元的阵列。通过补偿由平版印刷工艺产生的掩模开口的尺寸变化的过程，在掩模开口内形成蚀刻掩模。蚀刻掩模用于蚀刻通过分离层以限定暴露下面的触点的电极开口的阵列。电极材料沉积在电极开口内; 并且存储元件形成在底部电极上。最后，在存储器元件上形成位线以完成存储器单元。在所得到的存储器阵列中，底部电极的顶表面的临界尺寸小于掩模开口中存储元件的宽度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式