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1. 发明申请

US20130154583A1 DYNAMIC VOLTAGE SCALING SYSTEM BASED ON ON-CHIP MONITORING AND VOLTAGE PREDICTION 有权
标题翻译：基于片上监控和电压预测的动态电压调节系统
公开(公告)号：US20130154583A1
公开(公告)日：2013-06-20
申请号：US13700426
申请日：2011-10-17
申请人： Longxing Shi , Weiwei Shan , Jun Yang , Haolin Gu , Xinning Liu , Yang Zhang
发明人： Longxing Shi , Weiwei Shan , Jun Yang , Haolin Gu , Xinning Liu , Yang Zhang
IPC分类号： G05F1/10
CPC分类号： G05F1/10 , G06F1/26 , G06F11/008 , G06F11/3058
摘要： The present invention discloses a dynamic voltage scaling system based on on-chip monitoring and voltage prediction, comprising a main circuit that has integrated on-chip monitoring circuits, a supply voltage scaling module, and voltage converters, wherein, the supply voltage scaling module comprises a sampling and statistics module designed to calculate the error rate of the main circuit in the current time slice, a state recording module designed to record the error rate and the corresponding supply voltage, an error prediction module, and a state transition probability generation module; the error prediction module predicts the error trend of the main circuit in a future time slice according to the state recording module and the state transition probability generation module, and generates regulation signals and sends to the corresponding voltage converters, so as to generate the voltage required for operation of the entire main circuit. The present invention utilizes the Markov theory to predict the “future” timing violation level of the circuit according to the “past” working condition and “current” working condition of the main circuit, and reserves some time for voltage scaling in the voltage converters; as a result, the dynamic voltage scaling has high directivity and purposiveness.
摘要翻译：本发明公开了一种基于片上监控和电压预测的动态电压缩放系统，包括具有集成片上监控电路的主电路，电源电压缩放模块和电压转换器，其中电源电压缩放模块包括用于计算当前时间片中主电路的误码率的采样和统计模块，设计用于记录错误率和相应电源电压的状态记录模块，误差预测模块和状态转移概率生成模块; 误差预测模块根据状态记录模块和状态转移概率生成模块预测未来时间片中主电路的误差趋势，并产生调节信号并发送到相应的电压转换器，以产生所需的电压用于整个主电路的操作。本发明利用马尔可夫理论根据主电路的“过去”工作条件和“当前”工作状态预测电路的“未来”时序违规等级，并为电压转换器中的电压调整预留一些时间; 因此，动态电压调整具有很高的方向性和目的性。

2. 发明授权

US08909999B2 Dynamic voltage scaling system based on on-chip monitoring and voltage prediction 有权
标题翻译：基于片上监控和电压预测的动态电压缩放系统
公开(公告)号：US08909999B2
公开(公告)日：2014-12-09
申请号：US13700426
申请日：2011-10-17
申请人： Longxing Shi , Weiwei Shan , Jun Yang , Haolin Gu , Xinning Liu , Yang Zhang
发明人： Longxing Shi , Weiwei Shan , Jun Yang , Haolin Gu , Xinning Liu , Yang Zhang
IPC分类号： G06F11/00 , G05F1/10 , G06F1/26 , G06F11/30
CPC分类号： G05F1/10 , G06F1/26 , G06F11/008 , G06F11/3058
摘要： A dynamic voltage scaling system based on on-chip monitoring and voltage prediction is disclosed, comprising a main circuit that has integrated on-chip monitoring circuits, a supply voltage scaling module, and voltage converters, wherein, the supply voltage scaling module comprises a sampling and statistics module designed to calculate the error rate of the main circuit in the current time slice, a state recording module designed to record the error rate and the corresponding supply voltage, an error prediction module, and a state transition probability generation module; the error prediction module predicts the error trend of the main circuit in a future time slice according to the state recording module and the state transition probability generation module, and generates regulation signals and sends to the corresponding voltage converters, so as to generate the voltage required for operation of the entire main circuit.
摘要翻译：公开了一种基于片上监控和电压预测的动态电压缩放系统，其包括具有集成片上监控电路的主电路，电源电压缩放模块和电压转换器，其中，电源电压缩放模块包括采样统计模块设计用于计算当前时间片中主电路的误码率，设计为记录错误率和相应电源电压的状态记录模块，误差预测模块和状态转移概率生成模块; 误差预测模块根据状态记录模块和状态转移概率生成模块预测未来时间片中主电路的误差趋势，并产生调节信号并发送到相应的电压转换器，以产生所需的电压用于整个主电路的操作。

3. 发明授权

US08803580B2 Power-on-reset (POR) circuit with zero steady-state current consumption and stable pull-up voltage 有权
标题翻译：上电复位（POR）电路具有零稳态电流消耗和稳定的上拉电压
公开(公告)号：US08803580B2
公开(公告)日：2014-08-12
申请号：US13704184
申请日：2011-10-17
申请人： Longxing Shi , Weiwei Shan , Peng Cao , Na Bai , Xuexiang Wang , Tao Zhao
发明人： Longxing Shi , Weiwei Shan , Peng Cao , Na Bai , Xuexiang Wang , Tao Zhao
IPC分类号： H03L7/00 , H03K3/02
CPC分类号： H03K17/20 , H03K17/223
摘要： The present invention discloses a Power-On-Reset (POR) circuit with zero steady-state current consumption and stable pull-up voltage. The POR circuit achieves zero steady-state current consumption during steady operation after the POR process by cutting off a power supply to a band-gap comparator circuit and a current comparator circuit after the POR process. The present invention has high reliability and stable pull-up voltage, is less susceptible to the impact of power-on rate of power supply, temperature, and process variation, has very low steady-state power consumption, and can be integrated in a SOC chip in low-power consumption applications.
摘要翻译：本发明公开了一种具有零稳态电流消耗和稳定上拉电压的上电复位（POR）电路。在POR处理之后，通过在POR处理之后切断对带隙比较器电路和电流比较器电路的电源，POR电路在稳定运行期间实现零稳态电流消耗。本发明具有高可靠性和稳定的上拉电压，较不容易受到电源上电速率，温度和工艺变化的影响，具有非常低的稳态功耗，并且可以集成在SOC 芯片在低功耗应用中。

4. 发明申请

US20120069650A1 SUB-THRESHOLD MEMORY CELL CIRCUIT WITH HIGH DENSITY AND HIGH ROBUSTNESS 有权
标题翻译：具有高密度和高可靠性的子阈值存储单元电路
公开(公告)号：US20120069650A1
公开(公告)日：2012-03-22
申请号：US13322859
申请日：2009-08-13
申请人： Jun Yang , Na Bai , Jie Li , Chen Hu , Longxing Shi
发明人： Jun Yang , Na Bai , Jie Li , Chen Hu , Longxing Shi
IPC分类号： G11C11/34
CPC分类号： G11C11/412
摘要： A high-density and high-robustness sub-threshold memory cell circuit, having two PMOS transistors P1 and P2 and five NMOS transistors N1˜N5, wherein, the each base electrode of the two PMOS transistors and NMOS transistors N3, N4, and N5 is connected with the local grid electrode respectively; the base electrode of the NMOS transistors N1 and N2, are grounded respectively; the NMOS transistor N1 form an phase inverter with the PMOS transistor P1, and the NMOS transistor N2 form another phase inverter with the PMOS transistor P2; the two phase inverters are connected with each other in a cross coupling manner via the cut-off NMOS transistor N5, the output end of the phase inverter N1 and P1 directly connected to the input end of the phase inverter N2 and P2, and the output end of the phase inverter N2 and P2 connected to the input end of the phase inverter N1 and P1 via the cut-off NMOS transistor N5; the NMOS transistor N3 is connected with the write bit line (WBL) of the phase inverter N1 and P1, and the NMOS transistor N4 is connected with the NOT WBL and read word line (RWL) of the phase inverter N2 and P2.
摘要翻译：具有两个PMOS晶体管P1和P2以及五个NMOS晶体管N1〜N5的高密度和高鲁棒性子阈值存储单元电路，其中，两个PMOS晶体管和NMOS晶体管N3，N4和N5的每个基极分别与局部栅电极连接; NMOS晶体管N1和N2的基极分别接地; NMOS晶体管N1与PMOS晶体管P1形成相位逆变器，NMOS晶体管N2与PMOS晶体管P2形成另一个反相器; 两相逆变器通过截止NMOS晶体管N5，直流连接到相位逆变器N2和P2的输入端的相位反相器N1和P1的输出端以交叉耦合方式彼此连接，并且输出通过截止NMOS晶体管N5连接到相位反相器N1和P1的输入端的相位逆变器N2和P2的端部; NMOS晶体管N3与相位反相器N1和P1的写入位线（WBL）连接，NMOS晶体管N4与相位逆变器N2和P2的NOT WBL和读出字线（RWL）连接。

5. 发明授权

US08559213B2 Sub-threshold memory cell circuit with high density and high robustness 有权
标题翻译：子阈值存储单元电路具有高密度和高鲁棒性
公开(公告)号：US08559213B2
公开(公告)日：2013-10-15
申请号：US13322859
申请日：2009-08-13
申请人： Jun Yang , Na Bai , Jie Li , Chen Hu , Longxing Shi
发明人： Jun Yang , Na Bai , Jie Li , Chen Hu , Longxing Shi
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A high-density and high-robustness sub-threshold memory cell circuit, having two PMOS transistors P1 and P2 and five NMOS transistors N1˜N5, wherein, the each base electrode of the two PMOS transistors and NMOS transistors N3, N4, and N5 is connected with the local grid electrode respectively; the base electrode of the NMOS transistors N1 and N2, are grounded respectively; the NMOS transistor N1 form an phase inverter with the PMOS transistor P1, and the NMOS transistor N2 form another phase inverter with the PMOS transistor P2; the two phase inverters are connected with each other in a cross coupling manner via the cut-off NMOS transistor N5, the output end of the phase inverter N1 and P1 directly connected to the input end of the phase inverter N2 and P2, and the output end of the phase inverter N2 and P2 connected to the input end of the phase inverter N1 and P1 via the cut-off NMOS transistor N5; the NMOS transistor N3 is connected with the write bit line (WBL) of the phase inverter N1 and P1, and the NMOS transistor N4 is connected with the NOT WBL and read word line (RWL) of the phase inverter N2 and P2.
摘要翻译：具有两个PMOS晶体管P1和P2以及五个NMOS晶体管N1〜N5的高密度和高鲁棒性子阈值存储单元电路，其中，两个PMOS晶体管和NMOS晶体管N3，N4和N5的每个基极分别与局部栅电极连接; NMOS晶体管N1和N2的基极分别接地; NMOS晶体管N1与PMOS晶体管P1形成相位逆变器，NMOS晶体管N2与PMOS晶体管P2形成另一个反相器; 两相逆变器通过截止NMOS晶体管N5，直流连接到相位逆变器N2和P2的输入端的相位反相器N1和P1的输出端以交叉耦合方式彼此连接，并且输出通过截止NMOS晶体管N5连接到相位反相器N1和P1的输入端的相位逆变器N2和P2的端部; NMOS晶体管N3与相位反相器N1和P1的写入位线（WBL）连接，NMOS晶体管N4与相位逆变器N2和P2的NOT WBL和读出字线（RWL）连接。

6. 发明申请

US20130153956A1 SILICON ON INSULATOR INTEGRATED HIGH-CURRENT N TYPE COMBINED SEMICONDUCTOR DEVICE 有权
标题翻译：绝缘子集成高电流N型组合半导体器件的硅
公开(公告)号：US20130153956A1
公开(公告)日：2013-06-20
申请号：US13819286
申请日：2011-07-11
申请人： Longxing Shi , Qinsong Qian , Changlong Huo , Weifeng Sun , Shengli Lu
发明人： Longxing Shi , Qinsong Qian , Changlong Huo , Weifeng Sun , Shengli Lu
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/743 , H01L27/0705 , H01L29/66325 , H01L29/7394
摘要： A silicon on insulator integrated high-current N type combined semiconductor device, which can improve the current density, comprises a P type substrate and a buried oxide layer arranged thereon. A P type epitaxial layer divided into a region I and a region II is arranged on the buried oxide layer. The region I comprises an N type drift region, a P type deep well, an N type buffer well, a P type drain region, an N type source region and a P type body contact region; a field oxide layer and agate oxide layer are arranged on a silicon surface, and a polysilicon lattice is arranged on the gate oxide layer. The region II comprises an N type triode drift region, a P type deep well, an N type triode buffer well, a P type emitting region, an N type base region, an N type source region and a P type body contact region; a field oxide layer and a gate oxide layer are arranged on a silicon surface, and a polysilicon lattice is arranged on the gate oxide layer. It is characterized in that the N type base region is wrapped in the N type buffer region, and the drain electrode metal on the P type drain region is connected with the base electrode metal on the N type base region by a metal layer. In this invention, the current density of the device has been obviously improved without increasing the device area and reducing other performances of the device.
摘要翻译：一种绝缘体上集成的大电流N型组合半导体器件，其可以提高电流密度，包括P型衬底和其上布置的掩埋氧化物层。分为区域I和区域II的P型外延层布置在掩埋氧化物层上。区域I包括N型漂移区，P型深阱，N型缓冲阱，P型漏极区，N型源区和P型体接触区; 在硅表面上设置场氧化物层和玛瑙氧化物层，并且在栅极氧化物层上设置多晶硅晶格。区域II包括N型三极管漂移区，P型深阱，N型三极管缓冲阱，P型发射区，N型基极区，N型源区和P型体接触区; 在硅表面上设置场氧化物层和栅极氧化物层，并且在栅极氧化物层上设置多晶硅晶格。其特征在于，N型基极区域被包裹在N型缓冲区域中，P型漏极区域上的漏极金属通过金属层与N型基极区域上的基极金属连接。在本发明中，器件的电流密度明显提高，而不增加器件面积并降低器件的其他性能。

7. 发明申请

US20120326688A1 SWITCHING POWER SUPPLY WITH QUICK TRANSIENT RESPONSE 有权
标题翻译：快速切换电源切换
公开(公告)号：US20120326688A1
公开(公告)日：2012-12-27
申请号：US13582971
申请日：2010-10-25
申请人： Weifeng Sun , Miao Yang , Youshan Jin , Sichao Liu , Shen Xu , Shengli Lu , Longxing Shi
发明人： Weifeng Sun , Miao Yang , Youshan Jin , Sichao Liu , Shen Xu , Shengli Lu , Longxing Shi
IPC分类号： G05F1/618
CPC分类号： H02M3/1588 , H02M2001/0025 , H02M2003/1566 , Y02B70/1466
摘要： A switching power supply with a quick transient response is provided. A hysteretic control loop which comprises a hysteretic controller (117) and a control signal gate (116) is added to the original PWM control loop of the switching power supply. The hysteretic controller (117) is used to detect an output voltage (Vout) of the switching power supply and compare the output voltage (Vout) of the switching power supply with a reference voltage (Vref). When a load current (Iout) of the switching power supply is suddenly changed, the output voltage (Vout) of the switching power supply fluctuates. If the output voltage (Vout) of the switching power supply is in a setting range of the hysteretic voltage, output terminals (SELp, SELn) of the hysteretic controller (117) are in a low potential, and the control signal gate (116) selects output signals (Qp1, Qn1) from a PWM controller (101) as input signals of a gate signal drive circuit (106). If the fluctuation of the output voltage (Vout) of the switching power supply exceeds the setting range of the hysteretic voltage, an output terminal (SELp, SELn) of the hysteretic controller (117) outputs a high potential, and the control signal gate (116) selects output signals (Qp2, Qn2) of the hysteretic controller (117) as input signals of the gate signal drive circuit (106), so the operation of switching tubes (111, 112) at the power lever (102) of the switching power supply is controlled to stabilize the output voltage (Vout).
摘要翻译：提供了具有快速瞬态响应的开关电源。包括迟滞控制器（117）和控制信号门（116）的迟滞控制回路被添加到开关电源的原始PWM控制环路中。迟滞控制器（117）用于检测开关电源的输出电压（Vout），并将开关电源的输出电压（Vout）与参考电压（Vref）进行比较。当开关电源的负载电流（Iout）突然改变时，开关电源的输出电压（Vout）波动。如果开关电源的输出电压（Vout）处于滞后电压的设定范围，则迟滞控制器（117）的输出端子（SELp，SELn）为低电位，控制信号门（116）选择来自PWM控制器（101）的输出信号（Qp1，Qn1）作为门信号驱动电路（106）的输入信号。如果开关电源的输出电压（Vout）的波动超过迟滞电压的设定范围，则迟滞控制器（117）的输出端子（SELp，SELn）输出高电位，控制信号门极 116）选择滞后控制器（117）的输出信号（Qp2，Qn2）作为门信号驱动电路（106）的输入信号，从而切换管（111,112）在动力杆（102）控制开关电源以稳定输出电压（Vout）。

8. 发明授权

US08766698B2 Return-type current-reuse mixer 有权
标题翻译：返回型电流再利用混频器
公开(公告)号：US08766698B2
公开(公告)日：2014-07-01
申请号：US13978864
申请日：2011-08-18
申请人： Jianhui Wu , Chao Chen , Hong Li , Longxing Shi , Zixuan Wang , Jie Sun , Zhiyi Ye , Meng Zhang
发明人： Jianhui Wu , Chao Chen , Hong Li , Longxing Shi , Zixuan Wang , Jie Sun , Zhiyi Ye , Meng Zhang
IPC分类号： G06G7/12 , G06F7/44
CPC分类号： H03D7/1425
摘要： A return-type current-reuse mixer having a transconductance/amplification stage, a mixing stage, and a high-pass and a low-pass filter network. The transconductance/amplification stage has a current-reuse CMOS topology wherein an input frequency signal is converted into a frequency current, low-frequency components are removed from the frequency current by the high-pass filter network, the frequency current is fed into the mixing stage, modulation occurs in the mixing stage, and then an intermediate-frequency signal is generated and output. Once high-frequency components are removed from the intermediate-frequency signal by the low-pass filter network, the intermediate-frequency signal is sent again for input into the transconductance/amplification stage, then amplified in the transconductance/amplification stage and output. The mixer transconductance/amplification stage employs a current-reuse technique. The input frequency and the output intermediate-frequency signal share a common transconductance/amplification stage. The mixer reduces power consumption, simplifies the circuit topology, and provides high conversion gain.
摘要翻译：具有跨导/放大级，混频级以及高通和低通滤波器网络的返回型电流再利用混频器。跨导/放大级具有电流再利用CMOS拓扑，其中输入频率信号被转换成频率电流，低频分量由高通滤波器网络从频率电流中去除，频率电流被馈送到混频在混合阶段发生调制，然后产生并输出中频信号。一旦通过低通滤波器网络从中频信号中去除了高频分量，则再次发送中频信号以输入到跨导/放大级，然后在跨导/放大级中放大并输出。混频器跨导/放大级采用电流复用技术。输入频率和输出中频信号共用一个跨导/放大级。混频器降低了功耗，简化了电路拓扑结构，并提供了高转换增益。

9. 发明申请

US20120256671A1 SWITCH LEVEL CIRCUIT WITH DEAD TIME SELF-ADAPTING CONTROL 失效
标题翻译：切换电平电路与死时间自适应控制
公开(公告)号：US20120256671A1
公开(公告)日：2012-10-11
申请号：US13515801
申请日：2010-10-26
申请人： Shen Xu , Weifeng Sun , Miao Yang , Sichao Liu , Youshan Jin , Shengli Lu , Longxing Shi
发明人： Shen Xu , Weifeng Sun , Miao Yang , Sichao Liu , Youshan Jin , Shengli Lu , Longxing Shi
IPC分类号： H03K3/017
CPC分类号： H02M3/1588 , H02M2001/0048 , H02M2001/385 , Y02B70/1466 , Y02B70/1491
摘要： A switch level circuit (110) with dead time self-adapting control, which minimizes the switching loss in a switching power supply converter with synchronous rectification by changing a dead time between a high-side control transistor (10) and a low-side synchronous rectifying transistor (11). The switch level circuit (110) includes the high-side control transistor (10) and the low-side synchronous rectifying transistor (11) which are controlled to be on and off by external control signals, and a waveform with a given duty cycle is outputted at a node (LX) between the two transistors. The switch level circuit (110) also includes a control module for adjusting the dead time. The control module comprises a sampling circuit (16) for detecting the current dead time at the node (LX), an adjusting circuit (17) for buffering and converting the sampling voltage sampled by the sampling circuit (16), and a controlled delay unit (15) equipped with an external control input terminal, wherein the controlled delay unit (15) delays an external control signal and outputs the delayed signal to a controlled terminal of the low-side synchronous rectifying transistor (11) as a control signal. The switch level circuit (110) has simple structure, better performance and wide application range.
摘要翻译：一种具有死区时间自适应控制的开关电平电路（110），其通过改变高侧控制晶体管（10）和低侧同步（10）之间的死区时间而使得具有同步整流的开关电源转换器的开关损耗最小化整流晶体管（11）。开关电平电路（110）包括通过外部控制信号控制为接通和断开的高侧控制晶体管（10）和低侧同步整流晶体管（11），具有给定占空比的波形为在两个晶体管之间的节点（LX）处输出。开关电平电路（110）还包括用于调节死区时间的控制模块。控制模块包括用于检测节点（LX）上的当前死区时间的采样电路（16），用于缓冲和转换由采样电路（16）采样的采样电压的调节电路（17），以及受控延迟单元（15），其中所述受控延迟单元（15）延迟外部控制信号，并将延迟的信号作为控制信号输出到低侧同步整流晶体管（11）的受控端子。开关电平电路（110）结构简单，性能好，应用范围广。

10. 发明授权

US09048820B2 High-speed fully-differential clock duty cycle calibration circuit 有权
标题翻译：高速全差分时钟占空比校准电路
公开(公告)号：US09048820B2
公开(公告)日：2015-06-02
申请号：US13978710
申请日：2011-08-18
申请人： Longxing Shi , Danhong Gu , Junhui Gu , Jianhui Wu , Wei Zhao , Zhiyi Ye , Dahai Hu , Meng Zhang , Hong Li
发明人： Longxing Shi , Danhong Gu , Junhui Gu , Jianhui Wu , Wei Zhao , Zhiyi Ye , Dahai Hu , Meng Zhang , Hong Li
IPC分类号： H03K3/017 , H03K5/04 , H03K7/08 , H03K5/156
CPC分类号： H03K3/017 , H03K5/1565
摘要： A high-speed fully differential clock duty cycle calibration circuit applied to calibrating the clock duty cycle in a high-speed system. The circuit detects the duty cycle with a continuous time integrator, and directly adjusts the duty cycle on a clock transmission link so as to increase the working speed. Being of a fully differential circuit structure, the circuit can calibrate the duty cycle under a designated process within a higher and wider frequency range, and has relatively good constraining force for process mismatch and common mode noise. The circuit comprises adjustment level ADJ1 and ADJ2, a first buffer level BUF1, a second buffer level BUF2 and a duty cycle detection level DCD.
摘要翻译：高速全差分时钟占空比校准电路用于校准高速系统中的时钟占空比。该电路利用连续时间积分器检测占空比，并直接调整时钟传输链路上的占空比，以提高工作速度。作为全差分电路结构，该电路可以在更高和更宽的频率范围内的指定过程下校准占空比，并且对于过程失配和共模噪声具有相对较好的约束力。电路包括调整电平ADJ1和ADJ2，第一缓冲电平BUF1，第二缓冲电平BUF2和占空比检测电平DCD。

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