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1. 发明授权

US08766698B2 Return-type current-reuse mixer 有权
标题翻译：返回型电流再利用混频器
公开(公告)号：US08766698B2
公开(公告)日：2014-07-01
申请号：US13978864
申请日：2011-08-18
申请人： Jianhui Wu , Chao Chen , Hong Li , Longxing Shi , Zixuan Wang , Jie Sun , Zhiyi Ye , Meng Zhang
发明人： Jianhui Wu , Chao Chen , Hong Li , Longxing Shi , Zixuan Wang , Jie Sun , Zhiyi Ye , Meng Zhang
IPC分类号： G06G7/12 , G06F7/44
CPC分类号： H03D7/1425
摘要： A return-type current-reuse mixer having a transconductance/amplification stage, a mixing stage, and a high-pass and a low-pass filter network. The transconductance/amplification stage has a current-reuse CMOS topology wherein an input frequency signal is converted into a frequency current, low-frequency components are removed from the frequency current by the high-pass filter network, the frequency current is fed into the mixing stage, modulation occurs in the mixing stage, and then an intermediate-frequency signal is generated and output. Once high-frequency components are removed from the intermediate-frequency signal by the low-pass filter network, the intermediate-frequency signal is sent again for input into the transconductance/amplification stage, then amplified in the transconductance/amplification stage and output. The mixer transconductance/amplification stage employs a current-reuse technique. The input frequency and the output intermediate-frequency signal share a common transconductance/amplification stage. The mixer reduces power consumption, simplifies the circuit topology, and provides high conversion gain.
摘要翻译：具有跨导/放大级，混频级以及高通和低通滤波器网络的返回型电流再利用混频器。跨导/放大级具有电流再利用CMOS拓扑，其中输入频率信号被转换成频率电流，低频分量由高通滤波器网络从频率电流中去除，频率电流被馈送到混频在混合阶段发生调制，然后产生并输出中频信号。一旦通过低通滤波器网络从中频信号中去除了高频分量，则再次发送中频信号以输入到跨导/放大级，然后在跨导/放大级中放大并输出。混频器跨导/放大级采用电流复用技术。输入频率和输出中频信号共用一个跨导/放大级。混频器降低了功耗，简化了电路拓扑结构，并提供了高转换增益。

2. 发明申请

US20130300490A1 RETURN-TYPE CURRENT-REUSE MIXER 有权
标题翻译：返回型电流 - 再利用混合器
公开(公告)号：US20130300490A1
公开(公告)日：2013-11-14
申请号：US13978864
申请日：2011-08-18
申请人： Jianhui Wu , Chao Chen , Hong Li , Longxing Shi , Zixuan Wang , Jie Sun , Zhiyi Ye , Meng Zhang
发明人： Jianhui Wu , Chao Chen , Hong Li , Longxing Shi , Zixuan Wang , Jie Sun , Zhiyi Ye , Meng Zhang
IPC分类号： H03D7/14
CPC分类号： H03D7/1425
摘要： A return-type current-reuse mixer having a transconductance/amplification stage, a mixing stage, and a high-pass and a low-pass filter network. The transconductance/amplification stage has a current-reuse CMOS topology wherein an input frequency signal is converted into a frequency current, low-frequency components are removed from the frequency current by the high-pass filter network, the frequency current is fed into the mixing stage, modulation occurs in the mixing stage, and then an intermediate-frequency signal is generated and output. Once high-frequency components are removed from the intermediate-frequency signal by the low-pass filter network, the intermediate-frequency signal is sent again for input into the transconductance/amplification stage, then amplified in the transconductance/amplification stage and output. The mixer transconductance/amplification stage employs a current-reuse technique. The input frequency and the output intermediate-frequency signal share a common transconductance/amplification stage. The mixer reduces power consumption, simplifies the circuit topology, and provides high conversion gain.
摘要翻译：具有跨导/放大级，混频级以及高通和低通滤波器网络的返回型电流再利用混频器。跨导/放大级具有电流再利用CMOS拓扑，其中输入频率信号被转换成频率电流，低频分量由高通滤波器网络从频率电流中去除，频率电流被馈送到混频在混合阶段发生调制，然后产生并输出中频信号。一旦通过低通滤波器网络从中频信号中去除了高频分量，则再次发送中频信号以输入到跨导/放大级，然后在跨导/放大级中放大并输出。混频器跨导/放大级采用电流复用技术。输入频率和输出中频信号共用一个跨导/放大级。混频器降低了功耗，简化了电路拓扑结构，并提供了高转换增益。

3. 发明授权

US09048820B2 High-speed fully-differential clock duty cycle calibration circuit 有权
标题翻译：高速全差分时钟占空比校准电路
公开(公告)号：US09048820B2
公开(公告)日：2015-06-02
申请号：US13978710
申请日：2011-08-18
申请人： Longxing Shi , Danhong Gu , Junhui Gu , Jianhui Wu , Wei Zhao , Zhiyi Ye , Dahai Hu , Meng Zhang , Hong Li
发明人： Longxing Shi , Danhong Gu , Junhui Gu , Jianhui Wu , Wei Zhao , Zhiyi Ye , Dahai Hu , Meng Zhang , Hong Li
IPC分类号： H03K3/017 , H03K5/04 , H03K7/08 , H03K5/156
CPC分类号： H03K3/017 , H03K5/1565
摘要： A high-speed fully differential clock duty cycle calibration circuit applied to calibrating the clock duty cycle in a high-speed system. The circuit detects the duty cycle with a continuous time integrator, and directly adjusts the duty cycle on a clock transmission link so as to increase the working speed. Being of a fully differential circuit structure, the circuit can calibrate the duty cycle under a designated process within a higher and wider frequency range, and has relatively good constraining force for process mismatch and common mode noise. The circuit comprises adjustment level ADJ1 and ADJ2, a first buffer level BUF1, a second buffer level BUF2 and a duty cycle detection level DCD.
摘要翻译：高速全差分时钟占空比校准电路用于校准高速系统中的时钟占空比。该电路利用连续时间积分器检测占空比，并直接调整时钟传输链路上的占空比，以提高工作速度。作为全差分电路结构，该电路可以在更高和更宽的频率范围内的指定过程下校准占空比，并且对于过程失配和共模噪声具有相对较好的约束力。电路包括调整电平ADJ1和ADJ2，第一缓冲电平BUF1，第二缓冲电平BUF2和占空比检测电平DCD。

4. 发明申请

US20140002158A1 HIGH-SPEED FULLY-DIFFERENTIAL CLOCK DUTY CYCLE CALIBRATION CIRCUIT 有权
标题翻译：高速全差分时钟周期校准电路
公开(公告)号：US20140002158A1
公开(公告)日：2014-01-02
申请号：US13978710
申请日：2011-08-18
申请人： Longxing Shi , Danhong Gu , Junhui Gu , Jianhui Wu , Wei Zhao , Zhiyi Ye , Dahai Hu , Meng Zhang , Hong Li
发明人： Longxing Shi , Danhong Gu , Junhui Gu , Jianhui Wu , Wei Zhao , Zhiyi Ye , Dahai Hu , Meng Zhang , Hong Li
IPC分类号： H03K3/017
CPC分类号： H03K3/017 , H03K5/1565
摘要： A high-speed fully differential clock duty cycle calibration circuit applied to calibrating the clock duty cycle in a high-speed system. The circuit detects the duty cycle with a continuous time integrator, and directly adjusts the duty cycle on a clock transmission link so as to increase the working speed. Being of a fully differential circuit structure, the circuit can calibrate the duty cycle under a designated process within a higher and wider frequency range, and has relatively good constraining force for process mismatch and common mode noise. The circuit comprises adjustment level ADJ1 and ADJ2, a first buffer level BUF1, a second buffer level BUF2 and a duty cycle detection level DCD.
摘要翻译：高速全差分时钟占空比校准电路用于校准高速系统中的时钟占空比。该电路利用连续时间积分器检测占空比，并直接调整时钟传输链路上的占空比，以提高工作速度。作为全差分电路结构，该电路可以在更高和更宽的频率范围内的指定过程下校准占空比，并且对于过程失配和共模噪声具有相对较好的约束力。电路包括调整电平ADJ1和ADJ2，第一缓冲电平BUF1，第二缓冲电平BUF2和占空比检测电平DCD。

5. 发明申请

US20130307711A1 STOCHASTIC TIME-DIGITAL CONVERTER 有权
标题翻译： STOCHASTIC时代数字转换器
公开(公告)号：US20130307711A1
公开(公告)日：2013-11-21
申请号：US13983297
申请日：2012-05-29
申请人： Jianhui Wu , Zixuan Wang , Xiao Shi , Meng Zhang , Cheng Huang , Chao Chen , Fuqing Huang , Xincun Ji , Ping Jiang
发明人： Jianhui Wu , Zixuan Wang , Xiao Shi , Meng Zhang , Cheng Huang , Chao Chen , Fuqing Huang , Xincun Ji , Ping Jiang
IPC分类号： H03M1/04
CPC分类号： H03M1/04 , G04F10/005
摘要： A stochastic time-digital converter (STDC) including an input switching circuit, an STDC array, and an encoder. A clock circuit inputs two clock signals into two input terminals of the input switching circuit; the input switching circuit transmits the two clock signals in a cyclic cross-transposition form to two input terminals of the STDC array, and simultaneously outputs a trigger control signal to the encoder; each comparator in the STDC array independently judges the speeds of the two clock signals and sends the judgement results to the encoder for collection and processing; and the encoder outputs the size and positivity or negativity of the phase difference of the two clock signals. The technical solution utilizes the stochastic characteristic of the STDC to double the number of the equivalent comparators in the STDC array, eliminating the effects on the circuitry of device mismatching and processes, power supply voltage, and temperature.
摘要翻译：包括输入切换电路，STDC阵列和编码器的随机时间数字转换器（STDC）。时钟电路将两个时钟信号输入到输入开关电路的两个输入端; 输入切换电路以循环交叉形式将两个时钟信号发送到STDC阵列的两个输入端，同时向编码器输出触发控制信号; STDC阵列中的每个比较器独立地判断两个时钟信号的速度，并将判断结果发送到编码器进行采集和处理; 并且编码器输出两个时钟信号的相位差的大小和积极性或消极性。该技术解决方案利用STDC的随机特性将STDC阵列中的等效比较器的数量加倍，从而消除了器件不匹配和处理电路，电源电压和温度的影响。

6. 发明授权

US08810440B2 Stochastic Time-Digital Converter 有权
标题翻译：随机时间数字转换器
公开(公告)号：US08810440B2
公开(公告)日：2014-08-19
申请号：US13983297
申请日：2012-05-29
申请人： Jianhui Wu , Zixuan Wang , Xiao Shi , Meng Zhang , Cheng Huang , Chao Chen , Fuqing Huang , Xincun Ji , Ping Jiang
发明人： Jianhui Wu , Zixuan Wang , Xiao Shi , Meng Zhang , Cheng Huang , Chao Chen , Fuqing Huang , Xincun Ji , Ping Jiang
IPC分类号： H03M1/04 , G04F10/00
CPC分类号： H03M1/04 , G04F10/005
摘要： A stochastic time-digital converter (STDC) including an input switching circuit, an STDC array, and an encoder. A clock circuit inputs two clock signals into two input terminals of the input switching circuit; the input switching circuit transmits the two clock signals in a cyclic cross-transposition form to two input terminals of the STDC array, and simultaneously outputs a trigger control signal to the encoder; each comparator in the STDC array independently judges the speeds of the two clock signals and sends the judgement results to the encoder for collection and processing; and the encoder outputs the size and positivity or negativity of the phase difference of the two clock signals. The technical solution utilizes the stochastic characteristic of the STDC to double the number of the equivalent comparators in the STDC array, eliminating the effects on the circuitry of device mismatching and processes, power supply voltage, and temperature.
摘要翻译：包括输入切换电路，STDC阵列和编码器的随机时间数字转换器（STDC）。时钟电路将两个时钟信号输入到输入开关电路的两个输入端; 输入切换电路以循环交叉形式将两个时钟信号发送到STDC阵列的两个输入端，同时向编码器输出触发控制信号; STDC阵列中的每个比较器独立地判断两个时钟信号的速度，并将判断结果发送到编码器进行采集和处理; 并且编码器输出两个时钟信号的相位差的大小和积极性或消极性。该技术解决方案利用STDC的随机特性将STDC阵列中的等效比较器的数量加倍，从而消除了器件不匹配和处理电路，电源电压和温度的影响。

7. 发明公开

US20240292354A1 UPLINK TIMING ADJUSTMENT IN HIGH SPEED DEPLOYMENTS 审中-公开
公开(公告)号：US20240292354A1
公开(公告)日：2024-08-29
申请号：US18570722
申请日：2022-10-21
申请人： Ilya Bolotin , Meng Zhang , Andrey Chervyakov , Hua Li , Rui Huang
发明人： Ilya Bolotin , Meng Zhang , Andrey Chervyakov , Hua Li , Rui Huang
IPC分类号： H04W56/00 , H04L27/26 , H04W76/20 , H04W88/08
CPC分类号： H04W56/0015 , H04L27/26025 , H04W76/20 , H04W88/085
摘要： An apparatus and system of uplink timing adjustment for frequency range 2 (FR2) communication with remote radio heads (RRHs) in a unidirectional high speed train (HST) deployment are described. A one-shot uplink timing adjustment is applied when a first value is greater than a second value. The first value is a difference between an end of a first transmission from a neighboring RRH and an end of reception of the first transmission at the UE less a difference between an end of a second transmission from a serving RRH and an end of reception of the second transmission at the UE. The second value is a predetermined gradual timing adjustment set by a 3GPP specification, the predetermined adjustment plus a timing error limit, the predetermined adjustment plus twice a downlink error, or a multiple of the predetermined adjustment. The one-shot uplink timing adjustment is twice the first value.

8. 发明授权

US12004610B1 Watch band 有权
公开(公告)号：US12004610B1
公开(公告)日：2024-06-11
申请号：US18512053
申请日：2023-11-17
申请人： Meng Zhang
发明人： Meng Zhang
IPC分类号： A44C5/20 , A44C5/00
CPC分类号： A44C5/2042 , A44C5/0069
摘要： A watch band includes a connector including a first hole and a second hole arranged at opposite ends thereof; a first band connected to the first hole, and a second band connected to the second hole. The first band includes a first connection member connected to an end of a wearable electronic device, a free end section and an extension section connected between the first connection member and the free end section. The second band includes a second connection member connected to another end of the wearable electronic device. The free end section is extendable through the first hole to be fastened to the extension section by VELCRO-type hook-and-loop fasteners. The free end section is provided with loops, the fixing layer is provided with hooks engageable with the loops. The length of the watch band is adjustable via adjusting engaging position of the free end section and the fixing layer.

9. 发明公开

US20230224845A1 RECEIVE TIMING DIFFERENCE DEFINITION FOR HIGH SUBCARRIER SPACING 审中-公开
公开(公告)号：US20230224845A1
公开(公告)日：2023-07-13
申请号：US18091496
申请日：2022-12-30
申请人： Ilya Bolotin , Meng Zhang , Andrey Chervyakov , Hua Li , Rui Huang
发明人： Ilya Bolotin , Meng Zhang , Andrey Chervyakov , Hua Li , Rui Huang
IPC分类号： H04W56/00 , H04L5/00
CPC分类号： H04W56/0065 , H04L5/0092
摘要： An apparatus and system of establishing receive timing difference (RTD) for high subcarrier spacing (SCS) are described. The RTD is dependent on whether carrier aggregation (CA) or dual connectivity (DC) is used. For CA, RTD reflects the entire time difference between carriers caused by a Timing Alignment Error (TAE) and propagation delay difference between slots aligned at transmission. For DC, RTD is between the closest slot boundaries and reflects only slot boundary misalignment without considering the slot index.

10. 外观设计

USD794479S1 Digital caliper with large display 有权
公开(公告)号：USD794479S1
公开(公告)日：2017-08-15
申请号：US29556750
申请日：2016-03-03
申请人： Yanchen Zhang , Meng Zhang
设计人： Yanchen Zhang , Meng Zhang

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