专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140002158A1 HIGH-SPEED FULLY-DIFFERENTIAL CLOCK DUTY CYCLE CALIBRATION CIRCUIT 有权
标题翻译：高速全差分时钟周期校准电路
公开(公告)号：US20140002158A1
公开(公告)日：2014-01-02
申请号：US13978710
申请日：2011-08-18
申请人： Longxing Shi , Danhong Gu , Junhui Gu , Jianhui Wu , Wei Zhao , Zhiyi Ye , Dahai Hu , Meng Zhang , Hong Li
发明人： Longxing Shi , Danhong Gu , Junhui Gu , Jianhui Wu , Wei Zhao , Zhiyi Ye , Dahai Hu , Meng Zhang , Hong Li
IPC分类号： H03K3/017
CPC分类号： H03K3/017 , H03K5/1565
摘要： A high-speed fully differential clock duty cycle calibration circuit applied to calibrating the clock duty cycle in a high-speed system. The circuit detects the duty cycle with a continuous time integrator, and directly adjusts the duty cycle on a clock transmission link so as to increase the working speed. Being of a fully differential circuit structure, the circuit can calibrate the duty cycle under a designated process within a higher and wider frequency range, and has relatively good constraining force for process mismatch and common mode noise. The circuit comprises adjustment level ADJ1 and ADJ2, a first buffer level BUF1, a second buffer level BUF2 and a duty cycle detection level DCD.
摘要翻译：高速全差分时钟占空比校准电路用于校准高速系统中的时钟占空比。该电路利用连续时间积分器检测占空比，并直接调整时钟传输链路上的占空比，以提高工作速度。作为全差分电路结构，该电路可以在更高和更宽的频率范围内的指定过程下校准占空比，并且对于过程失配和共模噪声具有相对较好的约束力。电路包括调整电平ADJ1和ADJ2，第一缓冲电平BUF1，第二缓冲电平BUF2和占空比检测电平DCD。

2. 发明申请

US20130300490A1 RETURN-TYPE CURRENT-REUSE MIXER 有权
标题翻译：返回型电流 - 再利用混合器
公开(公告)号：US20130300490A1
公开(公告)日：2013-11-14
申请号：US13978864
申请日：2011-08-18
申请人： Jianhui Wu , Chao Chen , Hong Li , Longxing Shi , Zixuan Wang , Jie Sun , Zhiyi Ye , Meng Zhang
发明人： Jianhui Wu , Chao Chen , Hong Li , Longxing Shi , Zixuan Wang , Jie Sun , Zhiyi Ye , Meng Zhang
IPC分类号： H03D7/14
CPC分类号： H03D7/1425
摘要： A return-type current-reuse mixer having a transconductance/amplification stage, a mixing stage, and a high-pass and a low-pass filter network. The transconductance/amplification stage has a current-reuse CMOS topology wherein an input frequency signal is converted into a frequency current, low-frequency components are removed from the frequency current by the high-pass filter network, the frequency current is fed into the mixing stage, modulation occurs in the mixing stage, and then an intermediate-frequency signal is generated and output. Once high-frequency components are removed from the intermediate-frequency signal by the low-pass filter network, the intermediate-frequency signal is sent again for input into the transconductance/amplification stage, then amplified in the transconductance/amplification stage and output. The mixer transconductance/amplification stage employs a current-reuse technique. The input frequency and the output intermediate-frequency signal share a common transconductance/amplification stage. The mixer reduces power consumption, simplifies the circuit topology, and provides high conversion gain.
摘要翻译：具有跨导/放大级，混频级以及高通和低通滤波器网络的返回型电流再利用混频器。跨导/放大级具有电流再利用CMOS拓扑，其中输入频率信号被转换成频率电流，低频分量由高通滤波器网络从频率电流中去除，频率电流被馈送到混频在混合阶段发生调制，然后产生并输出中频信号。一旦通过低通滤波器网络从中频信号中去除了高频分量，则再次发送中频信号以输入到跨导/放大级，然后在跨导/放大级中放大并输出。混频器跨导/放大级采用电流复用技术。输入频率和输出中频信号共用一个跨导/放大级。混频器降低了功耗，简化了电路拓扑结构，并提供了高转换增益。

3. 发明授权

US08766698B2 Return-type current-reuse mixer 有权
标题翻译：返回型电流再利用混频器
公开(公告)号：US08766698B2
公开(公告)日：2014-07-01
申请号：US13978864
申请日：2011-08-18
申请人： Jianhui Wu , Chao Chen , Hong Li , Longxing Shi , Zixuan Wang , Jie Sun , Zhiyi Ye , Meng Zhang
发明人： Jianhui Wu , Chao Chen , Hong Li , Longxing Shi , Zixuan Wang , Jie Sun , Zhiyi Ye , Meng Zhang
IPC分类号： G06G7/12 , G06F7/44
CPC分类号： H03D7/1425
摘要： A return-type current-reuse mixer having a transconductance/amplification stage, a mixing stage, and a high-pass and a low-pass filter network. The transconductance/amplification stage has a current-reuse CMOS topology wherein an input frequency signal is converted into a frequency current, low-frequency components are removed from the frequency current by the high-pass filter network, the frequency current is fed into the mixing stage, modulation occurs in the mixing stage, and then an intermediate-frequency signal is generated and output. Once high-frequency components are removed from the intermediate-frequency signal by the low-pass filter network, the intermediate-frequency signal is sent again for input into the transconductance/amplification stage, then amplified in the transconductance/amplification stage and output. The mixer transconductance/amplification stage employs a current-reuse technique. The input frequency and the output intermediate-frequency signal share a common transconductance/amplification stage. The mixer reduces power consumption, simplifies the circuit topology, and provides high conversion gain.
摘要翻译：具有跨导/放大级，混频级以及高通和低通滤波器网络的返回型电流再利用混频器。跨导/放大级具有电流再利用CMOS拓扑，其中输入频率信号被转换成频率电流，低频分量由高通滤波器网络从频率电流中去除，频率电流被馈送到混频在混合阶段发生调制，然后产生并输出中频信号。一旦通过低通滤波器网络从中频信号中去除了高频分量，则再次发送中频信号以输入到跨导/放大级，然后在跨导/放大级中放大并输出。混频器跨导/放大级采用电流复用技术。输入频率和输出中频信号共用一个跨导/放大级。混频器降低了功耗，简化了电路拓扑结构，并提供了高转换增益。

4. 发明授权

US09048820B2 High-speed fully-differential clock duty cycle calibration circuit 有权
标题翻译：高速全差分时钟占空比校准电路
公开(公告)号：US09048820B2
公开(公告)日：2015-06-02
申请号：US13978710
申请日：2011-08-18
申请人： Longxing Shi , Danhong Gu , Junhui Gu , Jianhui Wu , Wei Zhao , Zhiyi Ye , Dahai Hu , Meng Zhang , Hong Li
发明人： Longxing Shi , Danhong Gu , Junhui Gu , Jianhui Wu , Wei Zhao , Zhiyi Ye , Dahai Hu , Meng Zhang , Hong Li
IPC分类号： H03K3/017 , H03K5/04 , H03K7/08 , H03K5/156
CPC分类号： H03K3/017 , H03K5/1565
摘要： A high-speed fully differential clock duty cycle calibration circuit applied to calibrating the clock duty cycle in a high-speed system. The circuit detects the duty cycle with a continuous time integrator, and directly adjusts the duty cycle on a clock transmission link so as to increase the working speed. Being of a fully differential circuit structure, the circuit can calibrate the duty cycle under a designated process within a higher and wider frequency range, and has relatively good constraining force for process mismatch and common mode noise. The circuit comprises adjustment level ADJ1 and ADJ2, a first buffer level BUF1, a second buffer level BUF2 and a duty cycle detection level DCD.
摘要翻译：高速全差分时钟占空比校准电路用于校准高速系统中的时钟占空比。该电路利用连续时间积分器检测占空比，并直接调整时钟传输链路上的占空比，以提高工作速度。作为全差分电路结构，该电路可以在更高和更宽的频率范围内的指定过程下校准占空比，并且对于过程失配和共模噪声具有相对较好的约束力。电路包括调整电平ADJ1和ADJ2，第一缓冲电平BUF1，第二缓冲电平BUF2和占空比检测电平DCD。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式