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1. 发明授权

US09048820B2 High-speed fully-differential clock duty cycle calibration circuit 有权
标题翻译：高速全差分时钟占空比校准电路
公开(公告)号：US09048820B2
公开(公告)日：2015-06-02
申请号：US13978710
申请日：2011-08-18
申请人： Longxing Shi , Danhong Gu , Junhui Gu , Jianhui Wu , Wei Zhao , Zhiyi Ye , Dahai Hu , Meng Zhang , Hong Li
发明人： Longxing Shi , Danhong Gu , Junhui Gu , Jianhui Wu , Wei Zhao , Zhiyi Ye , Dahai Hu , Meng Zhang , Hong Li
IPC分类号： H03K3/017 , H03K5/04 , H03K7/08 , H03K5/156
CPC分类号： H03K3/017 , H03K5/1565
摘要： A high-speed fully differential clock duty cycle calibration circuit applied to calibrating the clock duty cycle in a high-speed system. The circuit detects the duty cycle with a continuous time integrator, and directly adjusts the duty cycle on a clock transmission link so as to increase the working speed. Being of a fully differential circuit structure, the circuit can calibrate the duty cycle under a designated process within a higher and wider frequency range, and has relatively good constraining force for process mismatch and common mode noise. The circuit comprises adjustment level ADJ1 and ADJ2, a first buffer level BUF1, a second buffer level BUF2 and a duty cycle detection level DCD.
摘要翻译：高速全差分时钟占空比校准电路用于校准高速系统中的时钟占空比。该电路利用连续时间积分器检测占空比，并直接调整时钟传输链路上的占空比，以提高工作速度。作为全差分电路结构，该电路可以在更高和更宽的频率范围内的指定过程下校准占空比，并且对于过程失配和共模噪声具有相对较好的约束力。电路包括调整电平ADJ1和ADJ2，第一缓冲电平BUF1，第二缓冲电平BUF2和占空比检测电平DCD。

2. 发明申请

US20140002158A1 HIGH-SPEED FULLY-DIFFERENTIAL CLOCK DUTY CYCLE CALIBRATION CIRCUIT 有权
标题翻译：高速全差分时钟周期校准电路
公开(公告)号：US20140002158A1
公开(公告)日：2014-01-02
申请号：US13978710
申请日：2011-08-18
申请人： Longxing Shi , Danhong Gu , Junhui Gu , Jianhui Wu , Wei Zhao , Zhiyi Ye , Dahai Hu , Meng Zhang , Hong Li
发明人： Longxing Shi , Danhong Gu , Junhui Gu , Jianhui Wu , Wei Zhao , Zhiyi Ye , Dahai Hu , Meng Zhang , Hong Li
IPC分类号： H03K3/017
CPC分类号： H03K3/017 , H03K5/1565
摘要： A high-speed fully differential clock duty cycle calibration circuit applied to calibrating the clock duty cycle in a high-speed system. The circuit detects the duty cycle with a continuous time integrator, and directly adjusts the duty cycle on a clock transmission link so as to increase the working speed. Being of a fully differential circuit structure, the circuit can calibrate the duty cycle under a designated process within a higher and wider frequency range, and has relatively good constraining force for process mismatch and common mode noise. The circuit comprises adjustment level ADJ1 and ADJ2, a first buffer level BUF1, a second buffer level BUF2 and a duty cycle detection level DCD.
摘要翻译：高速全差分时钟占空比校准电路用于校准高速系统中的时钟占空比。该电路利用连续时间积分器检测占空比，并直接调整时钟传输链路上的占空比，以提高工作速度。作为全差分电路结构，该电路可以在更高和更宽的频率范围内的指定过程下校准占空比，并且对于过程失配和共模噪声具有相对较好的约束力。电路包括调整电平ADJ1和ADJ2，第一缓冲电平BUF1，第二缓冲电平BUF2和占空比检测电平DCD。

3. 发明授权

US08766698B2 Return-type current-reuse mixer 有权
标题翻译：返回型电流再利用混频器
公开(公告)号：US08766698B2
公开(公告)日：2014-07-01
申请号：US13978864
申请日：2011-08-18
申请人： Jianhui Wu , Chao Chen , Hong Li , Longxing Shi , Zixuan Wang , Jie Sun , Zhiyi Ye , Meng Zhang
发明人： Jianhui Wu , Chao Chen , Hong Li , Longxing Shi , Zixuan Wang , Jie Sun , Zhiyi Ye , Meng Zhang
IPC分类号： G06G7/12 , G06F7/44
CPC分类号： H03D7/1425
摘要： A return-type current-reuse mixer having a transconductance/amplification stage, a mixing stage, and a high-pass and a low-pass filter network. The transconductance/amplification stage has a current-reuse CMOS topology wherein an input frequency signal is converted into a frequency current, low-frequency components are removed from the frequency current by the high-pass filter network, the frequency current is fed into the mixing stage, modulation occurs in the mixing stage, and then an intermediate-frequency signal is generated and output. Once high-frequency components are removed from the intermediate-frequency signal by the low-pass filter network, the intermediate-frequency signal is sent again for input into the transconductance/amplification stage, then amplified in the transconductance/amplification stage and output. The mixer transconductance/amplification stage employs a current-reuse technique. The input frequency and the output intermediate-frequency signal share a common transconductance/amplification stage. The mixer reduces power consumption, simplifies the circuit topology, and provides high conversion gain.
摘要翻译：具有跨导/放大级，混频级以及高通和低通滤波器网络的返回型电流再利用混频器。跨导/放大级具有电流再利用CMOS拓扑，其中输入频率信号被转换成频率电流，低频分量由高通滤波器网络从频率电流中去除，频率电流被馈送到混频在混合阶段发生调制，然后产生并输出中频信号。一旦通过低通滤波器网络从中频信号中去除了高频分量，则再次发送中频信号以输入到跨导/放大级，然后在跨导/放大级中放大并输出。混频器跨导/放大级采用电流复用技术。输入频率和输出中频信号共用一个跨导/放大级。混频器降低了功耗，简化了电路拓扑结构，并提供了高转换增益。

4. 发明申请

US20130300490A1 RETURN-TYPE CURRENT-REUSE MIXER 有权
标题翻译：返回型电流 - 再利用混合器
公开(公告)号：US20130300490A1
公开(公告)日：2013-11-14
申请号：US13978864
申请日：2011-08-18
申请人： Jianhui Wu , Chao Chen , Hong Li , Longxing Shi , Zixuan Wang , Jie Sun , Zhiyi Ye , Meng Zhang
发明人： Jianhui Wu , Chao Chen , Hong Li , Longxing Shi , Zixuan Wang , Jie Sun , Zhiyi Ye , Meng Zhang
IPC分类号： H03D7/14
CPC分类号： H03D7/1425
摘要： A return-type current-reuse mixer having a transconductance/amplification stage, a mixing stage, and a high-pass and a low-pass filter network. The transconductance/amplification stage has a current-reuse CMOS topology wherein an input frequency signal is converted into a frequency current, low-frequency components are removed from the frequency current by the high-pass filter network, the frequency current is fed into the mixing stage, modulation occurs in the mixing stage, and then an intermediate-frequency signal is generated and output. Once high-frequency components are removed from the intermediate-frequency signal by the low-pass filter network, the intermediate-frequency signal is sent again for input into the transconductance/amplification stage, then amplified in the transconductance/amplification stage and output. The mixer transconductance/amplification stage employs a current-reuse technique. The input frequency and the output intermediate-frequency signal share a common transconductance/amplification stage. The mixer reduces power consumption, simplifies the circuit topology, and provides high conversion gain.
摘要翻译：具有跨导/放大级，混频级以及高通和低通滤波器网络的返回型电流再利用混频器。跨导/放大级具有电流再利用CMOS拓扑，其中输入频率信号被转换成频率电流，低频分量由高通滤波器网络从频率电流中去除，频率电流被馈送到混频在混合阶段发生调制，然后产生并输出中频信号。一旦通过低通滤波器网络从中频信号中去除了高频分量，则再次发送中频信号以输入到跨导/放大级，然后在跨导/放大级中放大并输出。混频器跨导/放大级采用电流复用技术。输入频率和输出中频信号共用一个跨导/放大级。混频器降低了功耗，简化了电路拓扑结构，并提供了高转换增益。

5. 发明申请

US20130307711A1 STOCHASTIC TIME-DIGITAL CONVERTER 有权
标题翻译： STOCHASTIC时代数字转换器
公开(公告)号：US20130307711A1
公开(公告)日：2013-11-21
申请号：US13983297
申请日：2012-05-29
申请人： Jianhui Wu , Zixuan Wang , Xiao Shi , Meng Zhang , Cheng Huang , Chao Chen , Fuqing Huang , Xincun Ji , Ping Jiang
发明人： Jianhui Wu , Zixuan Wang , Xiao Shi , Meng Zhang , Cheng Huang , Chao Chen , Fuqing Huang , Xincun Ji , Ping Jiang
IPC分类号： H03M1/04
CPC分类号： H03M1/04 , G04F10/005
摘要： A stochastic time-digital converter (STDC) including an input switching circuit, an STDC array, and an encoder. A clock circuit inputs two clock signals into two input terminals of the input switching circuit; the input switching circuit transmits the two clock signals in a cyclic cross-transposition form to two input terminals of the STDC array, and simultaneously outputs a trigger control signal to the encoder; each comparator in the STDC array independently judges the speeds of the two clock signals and sends the judgement results to the encoder for collection and processing; and the encoder outputs the size and positivity or negativity of the phase difference of the two clock signals. The technical solution utilizes the stochastic characteristic of the STDC to double the number of the equivalent comparators in the STDC array, eliminating the effects on the circuitry of device mismatching and processes, power supply voltage, and temperature.
摘要翻译：包括输入切换电路，STDC阵列和编码器的随机时间数字转换器（STDC）。时钟电路将两个时钟信号输入到输入开关电路的两个输入端; 输入切换电路以循环交叉形式将两个时钟信号发送到STDC阵列的两个输入端，同时向编码器输出触发控制信号; STDC阵列中的每个比较器独立地判断两个时钟信号的速度，并将判断结果发送到编码器进行采集和处理; 并且编码器输出两个时钟信号的相位差的大小和积极性或消极性。该技术解决方案利用STDC的随机特性将STDC阵列中的等效比较器的数量加倍，从而消除了器件不匹配和处理电路，电源电压和温度的影响。

6. 发明授权

US08810440B2 Stochastic Time-Digital Converter 有权
标题翻译：随机时间数字转换器
公开(公告)号：US08810440B2
公开(公告)日：2014-08-19
申请号：US13983297
申请日：2012-05-29
申请人： Jianhui Wu , Zixuan Wang , Xiao Shi , Meng Zhang , Cheng Huang , Chao Chen , Fuqing Huang , Xincun Ji , Ping Jiang
发明人： Jianhui Wu , Zixuan Wang , Xiao Shi , Meng Zhang , Cheng Huang , Chao Chen , Fuqing Huang , Xincun Ji , Ping Jiang
IPC分类号： H03M1/04 , G04F10/00
CPC分类号： H03M1/04 , G04F10/005
摘要： A stochastic time-digital converter (STDC) including an input switching circuit, an STDC array, and an encoder. A clock circuit inputs two clock signals into two input terminals of the input switching circuit; the input switching circuit transmits the two clock signals in a cyclic cross-transposition form to two input terminals of the STDC array, and simultaneously outputs a trigger control signal to the encoder; each comparator in the STDC array independently judges the speeds of the two clock signals and sends the judgement results to the encoder for collection and processing; and the encoder outputs the size and positivity or negativity of the phase difference of the two clock signals. The technical solution utilizes the stochastic characteristic of the STDC to double the number of the equivalent comparators in the STDC array, eliminating the effects on the circuitry of device mismatching and processes, power supply voltage, and temperature.
摘要翻译：包括输入切换电路，STDC阵列和编码器的随机时间数字转换器（STDC）。时钟电路将两个时钟信号输入到输入开关电路的两个输入端; 输入切换电路以循环交叉形式将两个时钟信号发送到STDC阵列的两个输入端，同时向编码器输出触发控制信号; STDC阵列中的每个比较器独立地判断两个时钟信号的速度，并将判断结果发送到编码器进行采集和处理; 并且编码器输出两个时钟信号的相位差的大小和积极性或消极性。该技术解决方案利用STDC的随机特性将STDC阵列中的等效比较器的数量加倍，从而消除了器件不匹配和处理电路，电源电压和温度的影响。

7. 发明授权

US08838618B1 System and method for identifying feature phrases in item description information 有权
标题翻译：用于在项目描述信息中识别特征短语的系统和方法
公开(公告)号：US08838618B1
公开(公告)日：2014-09-16
申请号：US13175124
申请日：2011-07-01
申请人： Jianhui Wu , Nicholas R. Boyd , Srikanth Thirumalai
发明人： Jianhui Wu , Nicholas R. Boyd , Srikanth Thirumalai
IPC分类号： G06F17/30
CPC分类号： G06F17/30625
摘要： Embodiments may include, for each item in a subset of items from a larger group of items, evaluating item description information about that item to identify a respective set of candidate phrases to be evaluated. Embodiments may also include, for each phrase in the sets of candidate phrases, generating multiple component scores based on one or more of the frequency with which that phrase occurs in the item description information for the subset of items and/or the frequency with which that phrase occurs in a corpus of item description information for the overall group of items. Embodiments may also include, for each phrase in the sets of candidate phrases, generating a respective phrase score based on the component scores generated for that phrase. Embodiments may include, based on phrase scores, selecting a subset of phrases from the sets of candidate phrases as being feature phrases for the subset of items.
摘要翻译：实施例可以包括对于来自较大组项目的项目的子集中的每个项目，评估关于该项目的项目描述信息以标识要评估的各个候选短语集合。实施例还可以包括对于候选短语集合中的每个短语，基于在该项目的子集的项目描述信息中出现该短语的频率中的一个或多个频率和/或该频率的频率，生成多个分量分数短语发生在整个项目组的项目描述信息的语料库中。对于候选短语集合中的每个短语，实施例还可以包括基于为该短语生成的分数分数来生成相应的短语分数。实施例可以包括基于短语分数，从候选短语集合中选择短语的子集作为项目子集的特征短语。

8. 发明授权

US08577814B1 System and method for genetic creation of a rule set for duplicate detection 有权
标题翻译：遗传创建用于重复检测的规则集的系统和方法
公开(公告)号：US08577814B1
公开(公告)日：2013-11-05
申请号：US13193285
申请日：2011-07-28
申请人： Jianhui Wu , Srikanth Thirumalai
发明人： Jianhui Wu , Srikanth Thirumalai
IPC分类号： G06F15/18
CPC分类号： G06N3/126
摘要： Embodiments may generate a population of candidate rules including multiple rule conditions for detecting duplicates, each duplicate representing different sets of item description information that describe a common item. For each candidate rule of the population, embodiments may apply that rule to a reference data set including known duplicates and non-duplicates. Embodiments may assign each candidate rule a fitness score generated with a fitness function based on the performance of that candidate rule. Embodiments may, based on the fitness scores, select a subset of the population of candidate rules as parents for the new generation of candidate rules. Embodiments may perform crossover and/or mutation operations on the parent candidate rules to generate the new generation of candidate rules. Embodiments may select from the new generation of candidate rules (or from subsequent generations of candidate rules), rules for inclusion within a rule set for detecting duplicates within item description information.
摘要翻译：实施例可以生成包括用于检测重复的多个规则条件的候选规则的总体，每个复制代表描述公共项目的不同的项目描述信息集合。对于群体的每个候选规则，实施例可以将该规则应用于包括已知重复项和非重复项的参考数据集。实施例可以基于该候选规则的执行来为每个候选规则分配用适应度函数生成的适合度分数。实施例可以基于适应度分数来选择候选规则的群体的子集作为新一代候选规则的父母。实施例可以对父候选规则执行交叉和/或变异操作以生成候选规则的新一代。实施例可以从新一代的候选规则（或从后续的候选规则）中选择用于包含在用于检测项目描述信息内的重复项的规则集中的规则。

9. 发明申请

US20130285715A1 Transconductance-Enhancing Passive Frequency Mixer 有权
标题翻译：跨导增强无源混频器
公开(公告)号：US20130285715A1
公开(公告)日：2013-10-31
申请号：US13980355
申请日：2012-05-29
申请人： Jianhui Wu , Xiao Shi , Chao Chen , Zhilin Liu , Qiang Zhao , Junfeng Wen , Xudong Wang , Chunfeng Bai , Qian Tian
发明人： Jianhui Wu , Xiao Shi , Chao Chen , Zhilin Liu , Qiang Zhao , Junfeng Wen , Xudong Wang , Chunfeng Bai , Qian Tian
IPC分类号： H03H11/04
CPC分类号： H03H11/0466 , H03D7/1441 , H03D7/1466
摘要： A transconductance-enhancing passive frequency mixer comprises a transconductance amplification stage, a frequency mixing stage, and an output transresistance amplifier. The transconductance amplification stage has a pre-amplification transconductance-enhancing structure, so that the transconductance is greatly enhanced, thereby obtaining the same transconductance value at a lower bias current. A radio-frequency current is modulated by the frequency mixing stage to generate an output mid-frequency current signal. The mid-frequency current signal passes through the transresistance amplifier, to form voltage output, and finally obtain a mid-frequency voltage signal. The transresistance amplifier has a transconductance-enhancing structure, thereby further reducing input impedance, and improving current utilization efficiency and port isolation. The frequency mixer has the characteristics of low power consumption, high conversion gain, good port isolation, and the like.
摘要翻译：跨导增强型无源混频器包括跨导放大级，频率混频级和输出跨阻放大器。跨导放大级具有预放大跨导增强结构，使得跨导大大增强，从而在较低偏置电流下获得相同的跨导值。射频电流由混频级调制以产生输出中频电流信号。中频电流信号通过跨阻放大器，形成电压输出，最后得到中频电压信号。跨阻放大器具有跨导增强结构，从而进一步降低输入阻抗，提高电流利用效率和端口隔离。该混频器具有低功耗，高转换增益，良好的端口隔离等特点。

10. 发明授权

US09022840B2 Abrasive tool for use as a chemical mechanical planarization pad conditioner 有权
标题翻译：用作化学机械平面化垫垫调节剂的研磨工具
公开(公告)号：US09022840B2
公开(公告)日：2015-05-05
申请号：US13682524
申请日：2012-11-20
申请人： Charles Dinh-Ngoc , Srinivasan Ramanath , Eric M. Schulz , Jianhui Wu , Thomas Puthanangady , Ramanujam Vedantham , Taewook Hwang
发明人： Charles Dinh-Ngoc , Srinivasan Ramanath , Eric M. Schulz , Jianhui Wu , Thomas Puthanangady , Ramanujam Vedantham , Taewook Hwang
IPC分类号： B24B53/12 , B24B53/017 , B24B37/04
CPC分类号： B24B53/017 , B24B37/04 , B24B53/12
摘要： An abrasive tool including a CMP pad conditioner having a substrate including a first major surface, a second major surface opposite the first major surface, and a side surface extending between the first major surface and the second major, wherein a first layer of abrasive grains is attached to the first major surface and a second layer of abrasive grains is attached to the second major surface. The conditioner further includes a first sealing member extending in a peripheral direction along a portion of the side surface of the substrate.
摘要翻译：一种研磨工具，包括具有基材的CMP垫调节剂，所述基材包括第一主表面，与第一主表面相对的第二主表面和在第一主表面和第二主表面之间延伸的侧表面，其中第一磨料颗粒层为附着在第一主表面上，第二层磨料颗粒附着在第二主表面上。调节器还包括沿着基板的侧表面的一部分沿周向方向延伸的第一密封构件。

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