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1. 发明授权

US06649489B1 Poly etching solution to improve silicon trench for low STI profile 有权
标题翻译： Poly蚀刻解决方案，以改善硅沟槽的低STI特性
公开(公告)号：US06649489B1
公开(公告)日：2003-11-18
申请号：US10366207
申请日：2003-02-13
申请人： Li-Wen Chang , Hung-Cheng Sung , Der-Shin Shyu , Han-Ping Chen , Chen-Ming Huang , Ya-Chen Kao
发明人： Li-Wen Chang , Hung-Cheng Sung , Der-Shin Shyu , Han-Ping Chen , Chen-Ming Huang , Ya-Chen Kao
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： A method of etch polysilicon adjacent to a recessed STI structure feature is described. A substrate is provided with a dielectric layer thereon and a polysilicon layer on the dielectric layer. A shallow trench is formed that extends through the polysilicon and dielectric layers into the substrate. An insulating material is used to fill the trench and is then recessed in the trench below the surface of the substrate by polishing and etching steps. A conformal buffer layer is deposited which covers the polysilicon and sidewalls of the trench above the recessed insulating layer. The buffer layer is etched back to expose the insulating layer and the polysilicon is removed by a plasma etch. A spacer comprised of a portion of the buffer layer protects the substrate during the polysilicon etch to prevent unwanted trenches from being formed adjacent to the STI structure, thereby increasing the etch process window.
摘要翻译：描述了与凹陷STI结构特征相邻的蚀刻多晶硅的方法。衬底上设置介电层，并在电介质层上设置多晶硅层。形成浅沟槽，其延伸穿过多晶硅和电介质层进入衬底。绝缘材料用于填充沟槽，然后通过抛光和蚀刻步骤将其凹入到衬底表面下方的沟槽中。沉积保形缓冲层，其覆盖凹陷绝缘层上方的沟槽的多晶硅和侧壁。将缓冲层回蚀刻以暴露绝缘层，并且通过等离子体蚀刻去除多晶硅。由缓冲层的一部分构成的间隔件在多晶硅蚀刻期间保护衬底以防止在STI结构附近形成不必要的沟槽，从而增加蚀刻工艺窗口。

2. 发明授权

US06819593B2 Architecture to suppress bit-line leakage 有权
标题翻译：抑制位线泄漏的体系结构
公开(公告)号：US06819593B2
公开(公告)日：2004-11-16
申请号：US10318458
申请日：2002-12-13
申请人： Der-Shin Shyu , Hung-Cheng Sung , Li-Wen Chang , Han-Ping Chen , Chen-Ming Huang , Ya-Chen Kao
发明人： Der-Shin Shyu , Hung-Cheng Sung , Li-Wen Chang , Han-Ping Chen , Chen-Ming Huang , Ya-Chen Kao
IPC分类号： G11C1600
CPC分类号： G11C16/3418 , G11C16/0425
摘要： A method to suppress bit-line leakage in a nonvolatile memory cell is achieved. The method comprises providing an array of nonvolatile memory cells comprising source and bulk terminals. The array comprises a plurality of subarrays. The sources of all the nonvolatile cells in each subarray are coupled together to form a common subarray source. Bulks of all the nonvolatile cells in the array are coupled together to form a common array bulk. A first, non-zero voltage is forced between the common subarray source and the common array bulk for a first subarray that is selected for an access operation. A second, non-zero voltage is forced between the common subarray source and the common array bulk for a second subarray that is not selected for an access operation. The second, non-zero voltage inhibits bit line leakage in the second subarray.
摘要翻译：实现了在非易失性存储单元中抑制位线泄漏的方法。该方法包括提供包括源极和体积端子的非易失性存储器单元的阵列。阵列包括多个子阵列。每个子阵列中的所有非易失性单元的源耦合在一起以形成公共的子阵列源。阵列中所有非易失性单元的容量被耦合在一起以形成共同的阵列体。对于为访问操作选择的第一子阵列，第一个非零电压被强制在公共子阵列源和公共阵列块之间。第二个非零电压被强制在公共子阵列源和公共阵列块之间，用于未被选择用于访问操作的第二子阵列。第二个非零电压禁止第二个子阵列中的位线泄漏。

3. 发明授权

US06569736B1 Method for fabricating square polysilicon spacers for a split gate flash memory device by multi-step polysilicon etch 有权
标题翻译：通过多步多晶硅蚀刻制造用于分离栅极闪存器件的方形多晶硅间隔物的方法
公开(公告)号：US06569736B1
公开(公告)日：2003-05-27
申请号：US10076668
申请日：2002-02-14
申请人： Cheng-Yuan Hsu , Hung-Cheng Sung , Su-Chang Chen , Han-Ping Chen , Chia-Ta Hsieh , Der-Shin Shyu
发明人： Cheng-Yuan Hsu , Hung-Cheng Sung , Su-Chang Chen , Han-Ping Chen , Chia-Ta Hsieh , Der-Shin Shyu
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/6656 , H01L29/66825
摘要： A method for forming square polysilicon spacers on a split gate flash memory device by a multi-step polysilicon etch process is described. The method can be carried out by depositing a polysilicon layer on the flash memory device structure and then depositing a sacrificial layer, such as silicon oxide, on top of the polysilicon layer. The sacrificial layer has a slower etch rate than the polysilicon layer during a main etch step. The sacrificial layer overlies the flash memory device is then removed, while the sacrificial layer on the sidewall is kept intact. The polysilicon layer that overlies the flash memory device is then etched away followed by a step of removing all residual sacrificial layers. The exposed polysilicon layer is then etched to define the square polysilicon spacers on the split gate flash memory device.
摘要翻译：描述了通过多步多晶硅蚀刻工艺在分裂栅极闪存器件上形成方形多晶硅间隔物的方法。该方法可以通过在闪存器件结构上沉积多晶硅层，然后在多晶硅层的顶部上沉积牺牲层，例如氧化硅来进行。在主蚀刻步骤期间，牺牲层具有比多晶硅层更慢的蚀刻速率。覆盖闪存器件的牺牲层然后被去除，同时侧壁上的牺牲层保持完整。然后将覆盖在闪速存储器件上的多晶硅层蚀刻掉，随后除去所有残余牺牲层的步骤。然后蚀刻暴露的多晶硅层以在分裂栅极闪存器件上限定方形多晶硅间隔物。

4. 发明授权

US06849499B2 Process for flash memory cell 失效
标题翻译：闪存单元的处理
公开(公告)号：US06849499B2
公开(公告)日：2005-02-01
申请号：US10331370
申请日：2002-12-30
申请人： Hung-Cheng Sung , Han-Ping Chen , Cheng-Yuan Hsu
发明人： Hung-Cheng Sung , Han-Ping Chen , Cheng-Yuan Hsu
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/336 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method is provided for forming a flash memory cell having an amorphous silicon floating gate capped by a CVD oxide, and a control gate formed over an intergate oxide layer formed over the oxide cap. Amorphous silicon is first formed over a gate oxide layer over a substrate, followed by the forming of a silicon nitride layer over the amorphous silicon layer. Silicon nitride is patterned to have a tapered opening so that the process window for aligning the floating gate with the active region of the cell is achieved with a relatively wide margin. Next, an oxide cap is formed over the floating gate. Using an oxide deposition method in place of the conventional polyoxidation method provides a less bulbous oxide formation over the floating gate, thus, yielding improved erase speed for the cell. The invention is also directed to a flash memory cell fabricated by the disclosed method.
摘要翻译：提供了一种用于形成具有由CVD氧化物覆盖的非晶硅浮动栅极的闪存单元的方法，以及形成在氧化物盖上形成的栅间氧化物层上的控制栅极。首先在衬底上的栅极氧化物层上形成无定形硅，随后在非晶硅层上形成氮化硅层。将氮化硅图案化成具有锥形开口，使得用浮动栅极与电池的有源区对准的工艺窗口以相对较大的余量实现。接下来，在浮动栅极上形成氧化物盖。使用氧化物沉积方法代替常规的多氧化方法提供了在浮栅上的较少的氧化锆形成，从而产生改善的电池的擦除速度。本发明还涉及通过所公开的方法制造的闪存单元。

5. 发明授权

US06828183B1 Process for high voltage oxide and select gate poly for split-gate flash memory 有权
标题翻译：用于高压氧化物的工艺和用于分流栅闪存的选择栅极聚合物
公开(公告)号：US06828183B1
公开(公告)日：2004-12-07
申请号：US10120834
申请日：2002-04-11
申请人： Hung Cheng Sung , Han-Ping Chen , Cheng Yuan Hsu
发明人： Hung Cheng Sung , Han-Ping Chen , Cheng Yuan Hsu
IPC分类号： H01L218238
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11534
摘要： A process for forming a high voltage oxide (HV) and a select gate poly for a split-gate flash memory is disclosed. The general difficulty of forming oxides of two different thicknesses for two different areas on the same substrate is alleviated by forming an HV oxide layer over the entire substrate just prior to the forming of the control gate of a cell area after the forming of a gate oxide layer over the peripheral area of the substrate. At an immediate subsequent step, a peripheral gate is formed over the HV oxide over the peripheral area, and, as a final step, the forming of the control gate, or the select gate of the cell area follows next.
摘要翻译：公开了一种用于形成用于分闸式闪存的高电压氧化物（HV）和选择栅多晶硅的工艺。在形成栅极氧化物之后，在形成电池区域的控制栅极之前，通过在整个衬底上形成HV氧化物层来减轻在相同衬底上形成两个不同厚度的两种不同厚度的氧化物的一般困难层在衬底的周边区域上。在紧随其后的步骤中，外围栅极形成在外围区域上的HV氧化物上，并且作为最后的步骤，接下来将形成控制栅极或单元区域的选择栅极。

6. 发明授权

US06482700B2 Split gate field effect transistor (FET) device with enhanced electrode registration and method for fabrication thereof 有权
标题翻译：具有增强的电极配准的分离栅场效应晶体管（FET）器件及其制造方法
公开(公告)号：US06482700B2
公开(公告)日：2002-11-19
申请号：US09725984
申请日：2000-11-29
申请人： Han-Ping Chen , Hung-Cheng Sung
发明人： Han-Ping Chen , Hung-Cheng Sung
IPC分类号： H01L218232
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/66553
摘要： Within a method for fabricating a split gate field effect transistor (FET) within a semiconductor integrated circuit microelectronic fabrication there is employed a patterned mask layer as an etch mask layer for forming from a blanket floating gate electrode material layer a floating gate electrode. At least a portion of the patterned mask layer is then laterally etched to completely expose an edge of the floating gate electrode prior to forming over the floating gate electrode and the edge of the floating gate electrode an inter-gate electrode dielectric layer having formed thereupon a control gate electrode. The method contemplates a split gate field effect transistor (FET) device fabricated in accord with the method. The resulting split gate field effect transistor (FET) device has an enhanced control gate electrode to floating gate electrode registration.
摘要翻译：在用于在半导体集成电路微电子制造中制造分裂栅极场效应晶体管（FET）的方法中，采用图案化掩模层作为用于从橡皮布浮栅电极材料层形成浮栅电极的蚀刻掩模层。然后在图案化掩模层的至少一部分被横向蚀刻之前，以在形成浮栅和浮栅之间的栅极电极介质层之前形成的栅间电极介电层控制栅电极。该方法考虑了根据该方法制造的分裂栅极场效应晶体管（FET）器件。所产生的分离栅场效应晶体管（FET）器件具有增强的控制栅电极到浮栅电极配准。

7. 发明申请

US20060007196A1 Panel display control and adjustment 审中-公开
标题翻译：面板显示控制和调整
公开(公告)号：US20060007196A1
公开(公告)日：2006-01-12
申请号：US10860096
申请日：2004-06-04
申请人： Han-Ping Chen
发明人： Han-Ping Chen
IPC分类号： G09G5/00
CPC分类号： G09G3/20 , G09G2320/0285 , G09G2330/10
摘要： A method and apparatus performs position-oriented adjustments of panel control signals for a flat panel display device in order to correct or compensate for pixel, line, or area defects or distortions such that the display quality meets or approaches a specification level. Also, the present invention provides a method to reduce the adjustment parameter storage by using simplified parametric descriptions.
摘要翻译：一种方法和装置对平板显示装置执行面板控制信号的面向位置的调整，以便校正或补偿像素，线或面积缺陷或失真，使得显示质量达到或接近规格水平。此外，本发明提供了一种通过简化参数描述来减少调整参数存储的方法。

8. 发明授权

US5731625A Bipolar variable resistance device 失效
标题翻译：双极可变电阻器件
公开(公告)号：US5731625A
公开(公告)日：1998-03-24
申请号：US766771
申请日：1996-12-13
申请人： Han-Ping Chen
发明人： Han-Ping Chen
IPC分类号： H01L27/11 , H01L27/04
CPC分类号： H01L27/1112 , Y10S257/904
摘要： A bipolar variable resistance device suitable for integrated circuit applications includes a silicon substrate, and a resistive layer covering the silicon substrate, the resistive layer being doped with impurities of a first polarity and of a second polarity. A dielectric layer covers the resistive layer. A conductive layer covers the dielectric layer. The device is used to change the resistance of the resistive layer by varying a control voltage applied to the conductive layer.
摘要翻译：适用于集成电路应用的双极可变电阻器件包括硅衬底和覆盖硅衬底的电阻层，电阻层掺杂有第一极性和第二极性的杂质。电介质层覆盖电阻层。导电层覆盖电介质层。该器件用于通过改变施加到导电层的控制电压来改变电阻层的电阻。

9. 发明申请

US20050127435A1 Method of forming self-aligned poly for embedded flash 有权
标题翻译：用于嵌入式闪光灯的自对准聚酰亚胺的方法
公开(公告)号：US20050127435A1
公开(公告)日：2005-06-16
申请号：US10822505
申请日：2004-04-12
申请人： Han-Ping Chen , Chung-Yi Yu
发明人： Han-Ping Chen , Chung-Yi Yu
IPC分类号： H01L21/8247 , H01L27/115 , H01L27/12 , H01L29/423 , H01L29/76 , H01L29/788
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11521 , H01L27/11534 , H01L27/1203 , H01L29/42324 , H01L29/7885
摘要： A method of manufacturing a microelectronic device including, in one embodiment, providing a substrate having a plurality of partially completed microelectronic devices including at least one partially completed memory device and at least one partially completed transistor. At least a portion of the partially completed transistor is protected by forming a first layer over the portion of the partially completed transistor to be protected during a subsequent material removal step. A second layer is formed substantially covering the partially completed memory device and the partially completed transistor. Portions of the second layer are removed leaving a portion of the second layer over the partially completed memory device. At least a substantial portion of the first layer is removed from the partially completed transistor after the portions of the second layer are removed.
摘要翻译：一种制造微电子器件的方法，在一个实施例中包括提供具有多个部分完成的微电子器件的衬底，所述微电子器件包括至少一个部分完成的存储器件和至少一个部分完成的晶体管。通过在随后的材料去除步骤期间在待保护的部分完成的晶体管的部分上形成第一层来保护部分完成的晶体管的至少一部分。形成基本覆盖部分完成的存储器件和部分完成的晶体管的第二层。去除第二层的部分，留下部分完成的存储器件上的第二层的一部分。在去除第二层的部分之后，第一层的至少大部分被从部分完成的晶体管中去除。

10. 发明授权

US06222211B1 Memory package method and apparatus 失效
标题翻译：存储器封装方法和装置
公开(公告)号：US06222211B1
公开(公告)日：2001-04-24
申请号：US09443330
申请日：1999-11-19
申请人： Han-Ping Chen
发明人： Han-Ping Chen
IPC分类号： H01L2710
CPC分类号： G11C29/88 , G11C29/883 , G11C29/886 , H01L27/105
摘要： A method and apparatus configures the data bits of partially defective memory devices in order to construct usable memory chip or module packages that meet the specification of a fully or partially functional package.
摘要翻译：方法和装置配置部分有缺陷的存储器件的数据位，以便构建满足完全或部分功能封装的规范的可用存储器芯片或模块封装。

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