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1. 发明申请

US20060007196A1 Panel display control and adjustment 审中-公开
标题翻译：面板显示控制和调整
公开(公告)号：US20060007196A1
公开(公告)日：2006-01-12
申请号：US10860096
申请日：2004-06-04
申请人： Han-Ping Chen
发明人： Han-Ping Chen
IPC分类号： G09G5/00
CPC分类号： G09G3/20 , G09G2320/0285 , G09G2330/10
摘要： A method and apparatus performs position-oriented adjustments of panel control signals for a flat panel display device in order to correct or compensate for pixel, line, or area defects or distortions such that the display quality meets or approaches a specification level. Also, the present invention provides a method to reduce the adjustment parameter storage by using simplified parametric descriptions.
摘要翻译：一种方法和装置对平板显示装置执行面板控制信号的面向位置的调整，以便校正或补偿像素，线或面积缺陷或失真，使得显示质量达到或接近规格水平。此外，本发明提供了一种通过简化参数描述来减少调整参数存储的方法。

2. 发明授权

US06649489B1 Poly etching solution to improve silicon trench for low STI profile 有权
标题翻译： Poly蚀刻解决方案，以改善硅沟槽的低STI特性
公开(公告)号：US06649489B1
公开(公告)日：2003-11-18
申请号：US10366207
申请日：2003-02-13
申请人： Li-Wen Chang , Hung-Cheng Sung , Der-Shin Shyu , Han-Ping Chen , Chen-Ming Huang , Ya-Chen Kao
发明人： Li-Wen Chang , Hung-Cheng Sung , Der-Shin Shyu , Han-Ping Chen , Chen-Ming Huang , Ya-Chen Kao
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： A method of etch polysilicon adjacent to a recessed STI structure feature is described. A substrate is provided with a dielectric layer thereon and a polysilicon layer on the dielectric layer. A shallow trench is formed that extends through the polysilicon and dielectric layers into the substrate. An insulating material is used to fill the trench and is then recessed in the trench below the surface of the substrate by polishing and etching steps. A conformal buffer layer is deposited which covers the polysilicon and sidewalls of the trench above the recessed insulating layer. The buffer layer is etched back to expose the insulating layer and the polysilicon is removed by a plasma etch. A spacer comprised of a portion of the buffer layer protects the substrate during the polysilicon etch to prevent unwanted trenches from being formed adjacent to the STI structure, thereby increasing the etch process window.
摘要翻译：描述了与凹陷STI结构特征相邻的蚀刻多晶硅的方法。衬底上设置介电层，并在电介质层上设置多晶硅层。形成浅沟槽，其延伸穿过多晶硅和电介质层进入衬底。绝缘材料用于填充沟槽，然后通过抛光和蚀刻步骤将其凹入到衬底表面下方的沟槽中。沉积保形缓冲层，其覆盖凹陷绝缘层上方的沟槽的多晶硅和侧壁。将缓冲层回蚀刻以暴露绝缘层，并且通过等离子体蚀刻去除多晶硅。由缓冲层的一部分构成的间隔件在多晶硅蚀刻期间保护衬底以防止在STI结构附近形成不必要的沟槽，从而增加蚀刻工艺窗口。

3. 发明授权

US5731625A Bipolar variable resistance device 失效
标题翻译：双极可变电阻器件
公开(公告)号：US5731625A
公开(公告)日：1998-03-24
申请号：US766771
申请日：1996-12-13
申请人： Han-Ping Chen
发明人： Han-Ping Chen
IPC分类号： H01L27/11 , H01L27/04
CPC分类号： H01L27/1112 , Y10S257/904
摘要： A bipolar variable resistance device suitable for integrated circuit applications includes a silicon substrate, and a resistive layer covering the silicon substrate, the resistive layer being doped with impurities of a first polarity and of a second polarity. A dielectric layer covers the resistive layer. A conductive layer covers the dielectric layer. The device is used to change the resistance of the resistive layer by varying a control voltage applied to the conductive layer.
摘要翻译：适用于集成电路应用的双极可变电阻器件包括硅衬底和覆盖硅衬底的电阻层，电阻层掺杂有第一极性和第二极性的杂质。电介质层覆盖电阻层。导电层覆盖电介质层。该器件用于通过改变施加到导电层的控制电压来改变电阻层的电阻。

4. 发明申请

US20050127435A1 Method of forming self-aligned poly for embedded flash 有权
标题翻译：用于嵌入式闪光灯的自对准聚酰亚胺的方法
公开(公告)号：US20050127435A1
公开(公告)日：2005-06-16
申请号：US10822505
申请日：2004-04-12
申请人： Han-Ping Chen , Chung-Yi Yu
发明人： Han-Ping Chen , Chung-Yi Yu
IPC分类号： H01L21/8247 , H01L27/115 , H01L27/12 , H01L29/423 , H01L29/76 , H01L29/788
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11521 , H01L27/11534 , H01L27/1203 , H01L29/42324 , H01L29/7885
摘要： A method of manufacturing a microelectronic device including, in one embodiment, providing a substrate having a plurality of partially completed microelectronic devices including at least one partially completed memory device and at least one partially completed transistor. At least a portion of the partially completed transistor is protected by forming a first layer over the portion of the partially completed transistor to be protected during a subsequent material removal step. A second layer is formed substantially covering the partially completed memory device and the partially completed transistor. Portions of the second layer are removed leaving a portion of the second layer over the partially completed memory device. At least a substantial portion of the first layer is removed from the partially completed transistor after the portions of the second layer are removed.
摘要翻译：一种制造微电子器件的方法，在一个实施例中包括提供具有多个部分完成的微电子器件的衬底，所述微电子器件包括至少一个部分完成的存储器件和至少一个部分完成的晶体管。通过在随后的材料去除步骤期间在待保护的部分完成的晶体管的部分上形成第一层来保护部分完成的晶体管的至少一部分。形成基本覆盖部分完成的存储器件和部分完成的晶体管的第二层。去除第二层的部分，留下部分完成的存储器件上的第二层的一部分。在去除第二层的部分之后，第一层的至少大部分被从部分完成的晶体管中去除。

5. 发明授权

US06849499B2 Process for flash memory cell 失效
标题翻译：闪存单元的处理
公开(公告)号：US06849499B2
公开(公告)日：2005-02-01
申请号：US10331370
申请日：2002-12-30
申请人： Hung-Cheng Sung , Han-Ping Chen , Cheng-Yuan Hsu
发明人： Hung-Cheng Sung , Han-Ping Chen , Cheng-Yuan Hsu
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/336 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method is provided for forming a flash memory cell having an amorphous silicon floating gate capped by a CVD oxide, and a control gate formed over an intergate oxide layer formed over the oxide cap. Amorphous silicon is first formed over a gate oxide layer over a substrate, followed by the forming of a silicon nitride layer over the amorphous silicon layer. Silicon nitride is patterned to have a tapered opening so that the process window for aligning the floating gate with the active region of the cell is achieved with a relatively wide margin. Next, an oxide cap is formed over the floating gate. Using an oxide deposition method in place of the conventional polyoxidation method provides a less bulbous oxide formation over the floating gate, thus, yielding improved erase speed for the cell. The invention is also directed to a flash memory cell fabricated by the disclosed method.
摘要翻译：提供了一种用于形成具有由CVD氧化物覆盖的非晶硅浮动栅极的闪存单元的方法，以及形成在氧化物盖上形成的栅间氧化物层上的控制栅极。首先在衬底上的栅极氧化物层上形成无定形硅，随后在非晶硅层上形成氮化硅层。将氮化硅图案化成具有锥形开口，使得用浮动栅极与电池的有源区对准的工艺窗口以相对较大的余量实现。接下来，在浮动栅极上形成氧化物盖。使用氧化物沉积方法代替常规的多氧化方法提供了在浮栅上的较少的氧化锆形成，从而产生改善的电池的擦除速度。本发明还涉及通过所公开的方法制造的闪存单元。

6. 发明授权

US06819593B2 Architecture to suppress bit-line leakage 有权
标题翻译：抑制位线泄漏的体系结构
公开(公告)号：US06819593B2
公开(公告)日：2004-11-16
申请号：US10318458
申请日：2002-12-13
申请人： Der-Shin Shyu , Hung-Cheng Sung , Li-Wen Chang , Han-Ping Chen , Chen-Ming Huang , Ya-Chen Kao
发明人： Der-Shin Shyu , Hung-Cheng Sung , Li-Wen Chang , Han-Ping Chen , Chen-Ming Huang , Ya-Chen Kao
IPC分类号： G11C1600
CPC分类号： G11C16/3418 , G11C16/0425
摘要： A method to suppress bit-line leakage in a nonvolatile memory cell is achieved. The method comprises providing an array of nonvolatile memory cells comprising source and bulk terminals. The array comprises a plurality of subarrays. The sources of all the nonvolatile cells in each subarray are coupled together to form a common subarray source. Bulks of all the nonvolatile cells in the array are coupled together to form a common array bulk. A first, non-zero voltage is forced between the common subarray source and the common array bulk for a first subarray that is selected for an access operation. A second, non-zero voltage is forced between the common subarray source and the common array bulk for a second subarray that is not selected for an access operation. The second, non-zero voltage inhibits bit line leakage in the second subarray.
摘要翻译：实现了在非易失性存储单元中抑制位线泄漏的方法。该方法包括提供包括源极和体积端子的非易失性存储器单元的阵列。阵列包括多个子阵列。每个子阵列中的所有非易失性单元的源耦合在一起以形成公共的子阵列源。阵列中所有非易失性单元的容量被耦合在一起以形成共同的阵列体。对于为访问操作选择的第一子阵列，第一个非零电压被强制在公共子阵列源和公共阵列块之间。第二个非零电压被强制在公共子阵列源和公共阵列块之间，用于未被选择用于访问操作的第二子阵列。第二个非零电压禁止第二个子阵列中的位线泄漏。

7. 发明授权

US06222211B1 Memory package method and apparatus 失效
标题翻译：存储器封装方法和装置
公开(公告)号：US06222211B1
公开(公告)日：2001-04-24
申请号：US09443330
申请日：1999-11-19
申请人： Han-Ping Chen
发明人： Han-Ping Chen
IPC分类号： H01L2710
CPC分类号： G11C29/88 , G11C29/883 , G11C29/886 , H01L27/105
摘要： A method and apparatus configures the data bits of partially defective memory devices in order to construct usable memory chip or module packages that meet the specification of a fully or partially functional package.
摘要翻译：方法和装置配置部分有缺陷的存储器件的数据位，以便构建满足完全或部分功能封装的规范的可用存储器芯片或模块封装。

8. 发明授权

US6125068A Memory access control 失效
标题翻译：内存访问控制
公开(公告)号：US6125068A
公开(公告)日：2000-09-26
申请号：US450017
申请日：1999-11-29
申请人： Han-Ping Chen
发明人： Han-Ping Chen
IPC分类号： G11C29/00 , G11C13/00
CPC分类号： G11C29/88 , G11C29/886
摘要： A method and apparatus controls the memory access of memory devices in order to utilize partially defective memory devices to construct usable memory chip or module packages that meet the specification of a fully or partially functional package.
摘要翻译：方法和装置控制存储器设备的存储器访问，以便利用部分有缺陷的存储器件来构建满足完全或部分功能封装的规范的可用存储器芯片或模块封装。

9. 发明授权

US07153744B2 Method of forming self-aligned poly for embedded flash 有权
标题翻译：用于嵌入式闪光灯的自对准聚酰亚胺的方法
公开(公告)号：US07153744B2
公开(公告)日：2006-12-26
申请号：US10822505
申请日：2004-04-12
申请人： Han-Ping Chen , Chung-Yi Yu
发明人： Han-Ping Chen , Chung-Yi Yu
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11521 , H01L27/11534 , H01L27/1203 , H01L29/42324 , H01L29/7885
摘要： A method of manufacturing a microelectronic device including, in one embodiment, providing a substrate having a plurality of partially completed microelectronic devices including at least one partially completed memory device and at least one partially completed transistor. At least a portion of the partially completed transistor is protected by forming a first layer over the portion of the partially completed transistor to be protected during a subsequent material removal step. A second layer is formed substantially covering the partially completed memory device and the partially completed transistor. Portions of the second layer are removed leaving a portion of the second layer over the partially completed memory device. At least a substantial portion of the first layer is removed from the partially completed transistor after the portions of the second layer are removed.
摘要翻译：一种制造微电子器件的方法，在一个实施例中包括提供具有多个部分完成的微电子器件的衬底，所述微电子器件包括至少一个部分完成的存储器件和至少一个部分完成的晶体管。通过在随后的材料去除步骤期间在待保护的部分完成的晶体管的部分上形成第一层来保护部分完成的晶体管的至少一部分。形成基本覆盖部分完成的存储器件和部分完成的晶体管的第二层。去除第二层的部分，留下部分完成的存储器件上的第二层的一部分。在去除第二层的部分之后，第一层的至少大部分被从部分完成的晶体管中去除。

10. 发明授权

US06358827B1 Method of forming a squared-off, vertically oriented polysilicon spacer gate 有权
标题翻译：形成平方的垂直取向的多晶硅间隔栅的方法
公开(公告)号：US06358827B1
公开(公告)日：2002-03-19
申请号：US09764232
申请日：2001-01-19
申请人： Han-Ping Chen , Hung-Chen Sung , Cheng-Yuan Hsu
发明人： Han-Ping Chen , Hung-Chen Sung , Cheng-Yuan Hsu
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/28114 , H01L29/42376
摘要： A method is taught for forming a rectangular or near rectangular polysilicon sidewall structure, which can be used as an ultra narrow MOSFET gate electrode. The method employs the use a step on a sacrificial oxide against which the polysilicon sidewall is formed. An etch stop, such as a gate oxide is formed alongside the step. A polysilicon layer is deposited over the step followed by a silicon nitride layer. Next a flowable layer is deposited and cured. In a first embodiment the flowable layer is deposited to completely cover the polysilicon layer. Next the wafer is planarized to exposed the polysilicon layer over the high part of the step an to a level wherein the polysilicon/silicon nitride interface is driven away from the step to a distance which determines the final width of the final sidewall structure. The residual flowable layer is then removed and a silicon oxide hardmask is grown over the exposed polysilicon. The polysilicon is anisotropically etched, part way to the through and the hardmask is removed. Anisotropic etching is then continued until the etch stop and the top of the sacrificial oxide are exposed, leaving a polysilicon sidewall with a rectangular cross section. In a second embodiment, the flowable layer is deposited to partially fill the valley next to the step. The second embodiment, which is less complex than the first and does not employ planarization processing, forms a near rectangular sidewall structure with a curved top surface. This profile is useable in most sidewall polysilicon gate applications. The process is especially useful in split-gate flash memory applications.
摘要翻译：教导了一种用于形成矩形或近似矩形的多晶硅侧壁结构的方法，其可以用作超窄MOSFET栅电极。该方法采用在形成多晶硅侧壁的牺牲氧化物上使用台阶。沿着台阶形成蚀刻停止物，例如栅极氧化物。在该步骤之后沉积多晶硅层，接着是氮化硅层。接下来，沉积和固化可流动层。在第一实施例中，沉积可流动层以完全覆盖多晶硅层。接下来，晶片被平坦化以将步骤a的高部分上的多晶硅层暴露于其中将多晶硅/氮化硅界面从该步骤驱动到一定距离，从而确定最终侧壁结构的最终宽度。然后除去残留的可流动层，并在暴露的多晶硅上生长氧化硅硬掩模。多晶硅被各向异性地蚀刻，部分途径到通孔，硬掩模被去除。然后继续进行各向异性蚀刻，直到蚀刻停止和牺牲氧化物的顶部暴露，留下具有矩形横截面的多晶硅侧壁。在第二实施例中，沉积可流动层以部分地填充步骤旁边的谷。第二实施例，其比第一实施例不复杂并且不采用平面化处理，形成具有弯曲顶表面的接近矩形的侧壁结构。该型材可用于大多数侧壁多晶硅栅极应用。该过程在分闸门闪存应用中特别有用。

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