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1. 发明授权

US07153744B2 Method of forming self-aligned poly for embedded flash 有权
标题翻译：用于嵌入式闪光灯的自对准聚酰亚胺的方法
公开(公告)号：US07153744B2
公开(公告)日：2006-12-26
申请号：US10822505
申请日：2004-04-12
申请人： Han-Ping Chen , Chung-Yi Yu
发明人： Han-Ping Chen , Chung-Yi Yu
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11521 , H01L27/11534 , H01L27/1203 , H01L29/42324 , H01L29/7885
摘要： A method of manufacturing a microelectronic device including, in one embodiment, providing a substrate having a plurality of partially completed microelectronic devices including at least one partially completed memory device and at least one partially completed transistor. At least a portion of the partially completed transistor is protected by forming a first layer over the portion of the partially completed transistor to be protected during a subsequent material removal step. A second layer is formed substantially covering the partially completed memory device and the partially completed transistor. Portions of the second layer are removed leaving a portion of the second layer over the partially completed memory device. At least a substantial portion of the first layer is removed from the partially completed transistor after the portions of the second layer are removed.
摘要翻译：一种制造微电子器件的方法，在一个实施例中包括提供具有多个部分完成的微电子器件的衬底，所述微电子器件包括至少一个部分完成的存储器件和至少一个部分完成的晶体管。通过在随后的材料去除步骤期间在待保护的部分完成的晶体管的部分上形成第一层来保护部分完成的晶体管的至少一部分。形成基本覆盖部分完成的存储器件和部分完成的晶体管的第二层。去除第二层的部分，留下部分完成的存储器件上的第二层的一部分。在去除第二层的部分之后，第一层的至少大部分被从部分完成的晶体管中去除。

2. 发明申请

US20050127435A1 Method of forming self-aligned poly for embedded flash 有权
标题翻译：用于嵌入式闪光灯的自对准聚酰亚胺的方法
公开(公告)号：US20050127435A1
公开(公告)日：2005-06-16
申请号：US10822505
申请日：2004-04-12
申请人： Han-Ping Chen , Chung-Yi Yu
发明人： Han-Ping Chen , Chung-Yi Yu
IPC分类号： H01L21/8247 , H01L27/115 , H01L27/12 , H01L29/423 , H01L29/76 , H01L29/788
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11521 , H01L27/11534 , H01L27/1203 , H01L29/42324 , H01L29/7885
摘要： A method of manufacturing a microelectronic device including, in one embodiment, providing a substrate having a plurality of partially completed microelectronic devices including at least one partially completed memory device and at least one partially completed transistor. At least a portion of the partially completed transistor is protected by forming a first layer over the portion of the partially completed transistor to be protected during a subsequent material removal step. A second layer is formed substantially covering the partially completed memory device and the partially completed transistor. Portions of the second layer are removed leaving a portion of the second layer over the partially completed memory device. At least a substantial portion of the first layer is removed from the partially completed transistor after the portions of the second layer are removed.
摘要翻译：一种制造微电子器件的方法，在一个实施例中包括提供具有多个部分完成的微电子器件的衬底，所述微电子器件包括至少一个部分完成的存储器件和至少一个部分完成的晶体管。通过在随后的材料去除步骤期间在待保护的部分完成的晶体管的部分上形成第一层来保护部分完成的晶体管的至少一部分。形成基本覆盖部分完成的存储器件和部分完成的晶体管的第二层。去除第二层的部分，留下部分完成的存储器件上的第二层的一部分。在去除第二层的部分之后，第一层的至少大部分被从部分完成的晶体管中去除。

3. 发明授权

US09233844B2 Graded aluminum—gallium—nitride and superlattice buffer layer for III-V nitride layer on silicon substrate 有权
标题翻译：在硅衬底上用于III-V氮化物层的分级氮化镓 - 氮化镓和超晶格缓冲层
公开(公告)号：US09233844B2
公开(公告)日：2016-01-12
申请号：US13534368
申请日：2012-06-27
申请人： Chi-Ming Chen , Po-Chun Liu , Chung-Yi Yu
发明人： Chi-Ming Chen , Po-Chun Liu , Chung-Yi Yu
IPC分类号： H01L31/00 , B82Y10/00 , B82Y40/00 , H01L21/02 , H01L29/10 , H01L29/20 , H01L29/66 , H01L29/778
CPC分类号： B82Y10/00 , B82Y40/00 , H01L21/02381 , H01L21/02458 , H01L21/02507 , H01L21/0251 , H01L21/0254 , H01L29/1075 , H01L29/2003 , H01L29/66462 , H01L29/7786
摘要： The present disclosure is directed to an integrated circuit and a method for the fabrication of the integrated circuit. The integrated circuit includes a lattice matching structure. The lattice matching structure can include a first buffer region, a second buffer region and a superlattice structure formed from AlxGa1-xN/AlyGa1-yN layer pairs.
摘要翻译：本公开涉及用于制造集成电路的集成电路和方法。集成电路包括晶格匹配结构。晶格匹配结构可以包括由Al x Ga 1-x N / Al y Ga 1-y N层对形成的第一缓冲区，第二缓冲区和超晶格结构。

4. 发明授权

US09142407B2 Semiconductor structure having sets of III-V compound layers and method of forming the same 有权
标题翻译：具有III-V族化合物层的半导体结构及其形成方法
公开(公告)号：US09142407B2
公开(公告)日：2015-09-22
申请号：US13743045
申请日：2013-01-16
申请人： Chi-Ming Chen , Po-Chun Liu , Chung-Yi Yu , Chia-Shiung Tsai
发明人： Chi-Ming Chen , Po-Chun Liu , Chung-Yi Yu , Chia-Shiung Tsai
IPC分类号： H01L29/66 , H01L21/02 , H01L29/778 , H01L29/15 , H01L29/20
CPC分类号： H01L21/02507 , H01L21/02458 , H01L21/02505 , H01L21/0251 , H01L21/0254 , H01L29/157 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/66522 , H01L29/778 , H01L29/7787
摘要： A semiconductor structure includes a substrate, a first III-V compound layer over the substrate, one or more sets of III-V compound layers over the first III-V compound layer, a second III-V compound layer over the one or more sets of III-V compound layers, and an active layer over the second III-V compound layer. The first III-V compound layer has a first type doping. Each of the one or more sets of III-V compound layers includes a lower III-V compound layer and an upper III-V compound layer over the lower III-V compound layer. The upper III-V compound layer having the first type doping, and the lower III-V compound layer is at least one of undoped, unintentionally doped having a second type doping, or doped having the second type doping. The second III-V compound layer is either undoped or unintentionally doped having the second type doping.
摘要翻译：半导体结构包括衬底，在衬底上的第一III-V化合物层，在第一III-V化合物层上的一组或多组III-V化合物层，在一个或多个组上的第二III-V化合物层的III-V化合物层，以及在第二III-V化合物层上的活性层。第一III-V族化合物层具有第一种掺杂。一组或多组III-V化合物层中的每一个在下III-V化合物层上包括下III-V化合物层和上III-V化合物层。具有第一类掺杂的上III-V化合物层和下III-V族化合物层是至少一种未掺杂的，无意掺杂的具有第二类型掺杂或掺杂具有第二类掺杂的至少一种。第二III-V族化合物层是未掺杂的或无意掺杂的，具有第二种掺杂。

5. 发明授权

US08772845B2 Technique for smoothing an interface between layers of a semiconductor device 有权
标题翻译：用于平滑半导体器件的层之间的界面的技术
公开(公告)号：US08772845B2
公开(公告)日：2014-07-08
申请号：US13240714
申请日：2011-09-22
申请人： Chih-Ming Chen , Cheng-Yuan Tsai , Chung-Yi Yu , Kai-Wen Cheng , Kuo-Ming Wu
发明人： Chih-Ming Chen , Cheng-Yuan Tsai , Chung-Yi Yu , Kai-Wen Cheng , Kuo-Ming Wu
IPC分类号： H01L21/02
CPC分类号： H01L27/228 , H01L43/08 , H01L43/12
摘要： The present disclosure provides a semiconductor memory device. The device includes a pinning layer having an anti-ferromagnetic material and disposed over a first electrode; a pinned layer disposed over the pinning layer; a composite layer disposed over the pinned layer, the composite layer having a magnetic material randomly distributed in a non-magnetic material; a barrier layer disposed on the composite layer; a free layer disposed over the barrier layer; and a second electrode disposed over the free layer.
摘要翻译：本公开提供一种半导体存储器件。该装置包括具有反铁磁材料并设置在第一电极上的钉扎层; 设置在钉扎层上方的钉扎层; 复合层，其设置在所述被钉扎层上方，所述复合层具有随机分布在非磁性材料中的磁性材料; 设置在所述复合层上的阻挡层; 设置在阻挡层上的自由层; 以及设置在所述自由层上方的第二电极。

6. 发明授权

US08710560B2 Embedded bonding pad for image sensors 有权
标题翻译：用于图像传感器的嵌入式焊盘
公开(公告)号：US08710560B2
公开(公告)日：2014-04-29
申请号：US11835814
申请日：2007-08-08
申请人： Yuan-Chih Hsieh , Shih-Chang Liu , Shih-Chi Fu , Tzu-Hsuan Hsu , Chung-Yi Yu , Gwo-Yuh Shiau , Chia-Shiung Tsai
发明人： Yuan-Chih Hsieh , Shih-Chang Liu , Shih-Chi Fu , Tzu-Hsuan Hsu , Chung-Yi Yu , Gwo-Yuh Shiau , Chia-Shiung Tsai
IPC分类号： H01L31/062
CPC分类号： H01L27/14643 , H01L24/05 , H01L27/14636 , H01L2224/05556 , H01L2924/12043 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate having a front surface and a back surface, elements formed on the substrate, interconnect metal layers formed over the front surface of the substrate, including a topmost interconnect metal layer, an inter-metal dielectric for insulating each of the plurality of interconnect metal layers, and a bonding pad disposed within the inter-metal dielectric, the bonding pad in contact with one of the interconnect metal layers other than the topmost interconnect metal layer.
摘要翻译：半导体器件包括具有前表面和后表面的半导体衬底，形成在衬底上的元件，形成在衬底的前表面上的互连金属层，包括最上面的互连金属层，用于绝缘的金属间电介质所述多个互连金属层和设置在所述金属间电介质内的接合焊盘，所述接合焊盘与所述互连金属层中的一个互连金属层之外的最上面的互连金属层接触。

7. 发明申请

US20130099282A1 FinFET Device And Method Of Manufacturing Same 有权
标题翻译： FinFET器件及其制造方法相同
公开(公告)号：US20130099282A1
公开(公告)日：2013-04-25
申请号：US13277669
申请日：2011-10-20
申请人： Chi-Ming Chen , Chung-Yi Yu , Ho-Yung David Hwang
发明人： Chi-Ming Chen , Chung-Yi Yu , Ho-Yung David Hwang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/8258 , H01L27/0605 , H01L27/0886 , H01L27/0924 , H01L29/66795 , H01L29/785
摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first dielectric layer disposed over the substrate. The semiconductor device further includes a buffer layer disposed over the substrate and between first and second walls of a trench of the dielectric layer. The semiconductor device further includes an insulator layer disposed over the buffer layer and between the first and second wall of the trench of the dielectric layer. The semiconductor device also includes a second dielectric layer disposed over the first dielectric layer and the insulator layer. Further, the semiconductor device includes a fin structure disposed over the insulator layer and between first and second walls of a trench of the second dielectric layer.
摘要翻译：公开了一种用于制造半导体器件的半导体器件和方法。示例性的半导体器件包括：衬底，包括设置在衬底上的第一介电层。该半导体器件还包括一个缓冲层，该缓冲层设置在该衬底上并且位于介电层沟槽的第一和第二壁之间。半导体器件还包括设置在缓冲层之上并位于介电层沟槽的第一和第二壁之间的绝缘体层。半导体器件还包括设置在第一介电层和绝缘体层之上的第二电介质层。此外，半导体器件包括布置在绝缘体层之上以及第二介电层的沟槽的第一和第二壁之间的翅片结构。

8. 发明申请

US20130078783A1 FORMING A PROTECTIVE FILM ON A BACK SIDE OF A SILICON WAFER IN A III-V FAMILY FABRICATION PROCESS 有权
标题翻译：在III-V家族制造工艺中形成硅片背面的保护膜
公开(公告)号：US20130078783A1
公开(公告)日：2013-03-28
申请号：US13244340
申请日：2011-09-24
申请人： Chun-Feng Nieh , Chung-Yi Yu , Hung-Ta Lin
发明人： Chun-Feng Nieh , Chung-Yi Yu , Hung-Ta Lin
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： Provided is a method of fabricating a semiconductor device. The method includes forming a first dielectric layer over a first surface and a second surface of a silicon substrate. the first and second surfaces being opposite surfaces. A first portion of the first dielectric layer covers the first surface of the substrate, and a second portion of the first dielectric layer covers the second surface of the substrate. The method includes forming openings that extend into the substrate from the first surface. The method includes filling the openings with a second dielectric layer. The method includes removing the first portion of the first dielectric layer without removing the second portion of the first dielectric layer.
摘要翻译：提供一种制造半导体器件的方法。该方法包括在硅衬底的第一表面和第二表面上形成第一电介质层。第一和第二表面是相对的表面。第一介电层的第一部分覆盖基板的第一表面，并且第一介电层的第二部分覆盖基板的第二表面。该方法包括形成从第一表面延伸到基底中的开口。该方法包括用第二介电层填充开口。该方法包括在不去除第一介电层的第二部分的情况下去除第一介电层的第一部分。

9. 发明授权

US08334187B2 Hard mask for thin film resistor manufacture 有权
标题翻译：薄膜电阻制造的硬掩模
公开(公告)号：US08334187B2
公开(公告)日：2012-12-18
申请号：US12824495
申请日：2010-06-28
申请人： Li-Wen Chang , Der-Chyang Yeh , Chung-Yi Yu , Hsun-Chung Kuang , Hua-Chou Tseng , Chih-Ping Chao , Ming Chyi Liu , Yuan-Tai Tseng
发明人： Li-Wen Chang , Der-Chyang Yeh , Chung-Yi Yu , Hsun-Chung Kuang , Hua-Chou Tseng , Chih-Ping Chao , Ming Chyi Liu , Yuan-Tai Tseng
IPC分类号： H01L21/20
CPC分类号： H01L28/20 , H01L28/24
摘要： Methods of fabricating an integrated circuit device, such as a thin film resistor, are disclosed. An exemplary method includes providing a semiconductor substrate; forming a resistive layer over the semiconductor substrate; forming a hard mask layer over the resistive layer, wherein the hard mask layer includes a barrier layer over the resistive layer and a dielectric layer over the barrier layer; and forming an opening in the hard mask layer that exposes a portion of the resistive layer.
摘要翻译：公开了制造诸如薄膜电阻器的集成电路器件的方法。一种示例性方法包括提供半导体衬底; 在所述半导体衬底上形成电阻层; 在所述电阻层上形成硬掩模层，其中所述硬掩模层包括所述电阻层上的阻挡层和所述阻挡层上的电介质层; 以及在所述硬掩模层中形成暴露所述电阻层的一部分的开口。

10. 发明申请

US20120238076A1 Method and Apparatus for Forming a III-V Family Layer 审中-公开
标题翻译：用于形成III-V族层的方法和装置
公开(公告)号：US20120238076A1
公开(公告)日：2012-09-20
申请号：US13482029
申请日：2012-05-29
申请人： Chi-Ming Chen , Chung-Yi Yu , Chia-Shiung Tsai , Ho-Yung David Hwang
发明人： Chi-Ming Chen , Chung-Yi Yu , Chia-Shiung Tsai , Ho-Yung David Hwang
IPC分类号： H01L21/20
CPC分类号： C23C16/303 , C23C16/4401 , C23C16/54 , C23C16/56
摘要： Provided is an apparatus. The apparatus includes: a first deposition component that is operable to form a compound over a semiconductor wafer, the compound including at least one of: a III-family element and a V-family element; a second deposition component that is operable to form a passivation layer over the compound; and a transfer component that is operable to move the semiconductor wafer between the first and second deposition components, the transfer component enclosing a space that contains substantially no oxygen and substantially no silicon; wherein the loading component, the first and second deposition components, and the transfer component are all integrated into a single fabrication tool.
摘要翻译：提供了一种装置。该装置包括：第一沉积部件，其可操作以在半导体晶片上形成化合物，所述化合物包括III族元素和V族元素中的至少一种; 第二沉积组分，其可操作以在所述化合物上形成钝化层; 以及可操作以在所述第一和第二沉积部件之间移动所述半导体晶片的转移部件，所述转移部件包围基本上不含氧且基本上不含硅的空间; 其中装载部件，第一和第二沉积部件以及传送部件都被集成到单个制造工具中。

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