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1. 发明授权

US06737725B2 Multilevel interconnect structure containing air gaps and method for making 有权
标题翻译：包含气隙的多层互连结构和制造方法
公开(公告)号：US06737725B2
公开(公告)日：2004-05-18
申请号：US10144574
申请日：2002-05-13
申请人： Alfred Grill , Jeffrey Curtis Hedrick , Christopher Vincent Jahnes , Satyanarayana Venkata Nitta , Kevin S. Petrarca , Sampath Purushothaman , Katherine Lynn Saenger , Stanley Joseph Whitehair
发明人： Alfred Grill , Jeffrey Curtis Hedrick , Christopher Vincent Jahnes , Satyanarayana Venkata Nitta , Kevin S. Petrarca , Sampath Purushothaman , Katherine Lynn Saenger , Stanley Joseph Whitehair
IPC分类号： H01L2900
CPC分类号： H01L21/7682 , H01L21/76831 , H01L21/76834 , H01L21/76835 , H01L21/76885
摘要： A method for forming a multilayer interconnect structure on a substrate that include interconnected conductive wiring and vias spaced apart by a combination of solid or gaseous dielectrics. The inventive method includes the steps of: (a) forming a first planar via plus line level pair embedded in a dielectric matrix formed from one or more solid dielectrics and comprising a via level dielectric and a line level dielectric on a substrate, wherein, at least one of said solid dielectrics is at least partially sacrificial; (b) etching back sacrificial portions of said at least partially sacrificial dielectrics are removed to leave cavities extending into and through said via level, while leaving, at least some of the original via level dielectric as a permanent dielectric under said lines; (c) partially filling or overfilling said cavities with a place-holder material which may or may not be sacrificial; (d) planarizing the structure by removing overfill of said place-holder material; (e) repeating, as necessary, steps (a)-(d); (f) forming a dielectric bridge layer over the planar structure; and (g) forming air gaps by at least partially extracting said place-holder material.
摘要翻译：一种在衬底上形成多层互连结构的方法，其包括互连的导电布线和通过固体或气体电介质的组合间隔开的通孔。本发明的方法包括以下步骤：（a）形成嵌入在由一个或多个固体电介质形成的电介质矩阵中并且包括通孔层电介质和衬底上的线路电介质的介电矩阵中的第一平面通孔加线电平对，其中，在至少一个所述固体电介质至少部分地是牺牲的; （b）蚀刻所述至少部分牺牲电介质的牺牲部分被去除以留下延伸进入并穿过所述通孔级的空腔，同时留下至少一些原始通孔级电介质作为所述线下的永久电介质; （c）用可能牺牲或可能不是牺牲的位置保持材料部分填充或过度填充所述空腔; （d）通过去除所述位置保持器材料的过量填充来平坦化结构; （e）必要时重复步骤（a） - （d）; （f）在所述平面结构上形成电介质桥接层; 和（g）通过至少部分地提取所述放置支架材料形成气隙。

2. 发明授权

US06413852B1 Method of forming multilevel interconnect structure containing air gaps including utilizing both sacrificial and placeholder material 有权
标题翻译：形成包含气隙的多层互连结构的方法，包括利用牺牲和占位材料
公开(公告)号：US06413852B1
公开(公告)日：2002-07-02
申请号：US09652754
申请日：2000-08-31
申请人： Alfred Grill , Jeffrey Curtis Hedrick , Christopher Vincent Jahnes , Satyanarayana Venkata Nitta , Kevin S. Petrarca , Sampath Purushothaman , Katherine Lynn Saenger , Stanley Joseph Whitehair
发明人： Alfred Grill , Jeffrey Curtis Hedrick , Christopher Vincent Jahnes , Satyanarayana Venkata Nitta , Kevin S. Petrarca , Sampath Purushothaman , Katherine Lynn Saenger , Stanley Joseph Whitehair
IPC分类号： H01L218234
CPC分类号： H01L21/7682 , H01L21/76831 , H01L21/76834 , H01L21/76835 , H01L21/76885
摘要： A method for forming a multilayer interconnect structure on a substrate that include interconnected conductive wiring and vias spaced apart by a combination of solid or gaseous dielectrics. The inventive method includes the steps of: (a) forming a first planar via plus line level pair embedded in a dielectric matrix formed from one or more solid dielectrics and comprising a via level dielectric and a line level dielectric on a substrate, wherein, at least one of said solid dielectrics is at least partially sacrificial; (b) etching back sacrificial portions of said at least partially sacrificial dielectrics are removed to leave cavities extending into and through said via level, while leaving, at least some of the original via level dielectric as a permanent dielectric under said lines; (c) partially filling or overfilling said cavities with a place-holder material which may or may not be sacrificial; (d) planarizing the structure by removing overfill of said place-holder material; (e) repeating, as necessary, steps (a)-(d); (f) forming a dielectric bridge layer over the planar structure; and (g) forming air gaps by at least partially extracting said place-holder material.
摘要翻译：一种在衬底上形成多层互连结构的方法，其包括互连的导电布线和通过固体或气体电介质的组合间隔开的通孔。本发明的方法包括以下步骤：（a）形成嵌入在由一个或多个固体电介质形成的电介质矩阵中并且包括通孔层电介质和衬底上的线路电介质的介电矩阵中的第一平面通孔加线电平对，其中，在至少一个所述固体电介质至少部分地是牺牲的; （b）蚀刻所述至少部分牺牲电介质的牺牲部分被去除以留下延伸进入并穿过所述通孔级的空腔，同时留下至少一些原始通孔级电介质作为所述线下的永久电介质; （c）用可能牺牲或可能不是牺牲的位置保持材料部分填充或过度填充所述空腔; （d）通过去除所述位置保持器材料的过量填充来平坦化结构; （e）必要时重复步骤（a） - （d）; （f）在所述平面结构上形成电介质桥接层; 和（g）通过至少部分地提取所述放置支架材料形成气隙。

3. 发明授权

US06943451B2 Semiconductor devices containing a discontinuous cap layer and methods for forming same 有权
标题翻译：包含不连续盖层的半导体器件及其形成方法
公开(公告)号：US06943451B2
公开(公告)日：2005-09-13
申请号：US09897200
申请日：2001-07-02
申请人： Stanley Joseph Whitehair , Stephen McConnell Gates , Sampath Purushothaman , Satyanarayana V. Nitta , Maurice McGlashan-Powell , Kevin S. Petrarca
发明人： Stanley Joseph Whitehair , Stephen McConnell Gates , Sampath Purushothaman , Satyanarayana V. Nitta , Maurice McGlashan-Powell , Kevin S. Petrarca
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48 , H01L21/4763 , H01L23/52 , H01L23/58 , H01L29/40
CPC分类号： H01L21/76888 , H01L21/76834 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Novel semiconductor devices containing a discontinuous cap layer and possessing a relatively low dielectric constant are provide herein. The novel semiconductor devices includes at least a substrate, a first dielectric layer applied on at least a portion of the substrate, a first set of openings formed through the dielectric layer to expose the surface of the substrate so that a conductive material deposited within and filling the openings provides a first set of electrical contact conductive elements and a discontinuous layer of cap material covering at least the top of the conductive elements to provide a first set of discontinuous cap elements. Methods for forming the semiconductor devices are also provided.
摘要翻译：本文提供了包含不连续盖层并且具有相对低介电常数的新型半导体器件。新颖的半导体器件至少包括衬底，施加在衬底的至少一部分上的第一介电层，通过电介质层形成的第一组开口，以暴露衬底的表面，使得沉积在其中并填充的导电材料开口提供第一组电接触导电元件和覆盖至少导电元件的顶部的不连续的覆盖材料层，以提供第一组不连续帽元件。还提供了形成半导体器件的方法。

4. 发明授权

US08633580B2 Integrated void fill for through silicon via 有权
标题翻译：通过硅通孔的集成空隙填充
公开(公告)号：US08633580B2
公开(公告)日：2014-01-21
申请号：US13569231
申请日：2012-08-08
申请人： Richard P. Volant , Mukta G. Farooq , Kevin S. Petrarca
发明人： Richard P. Volant , Mukta G. Farooq , Kevin S. Petrarca
IPC分类号： H01L25/11
CPC分类号： H01L21/76879 , H01L21/76805 , H01L21/76898 , H01L23/481 , H01L24/16 , H01L24/29 , H01L24/82 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/29 , H01L2224/29298 , H01L2224/9202 , H01L2224/92144 , H01L2225/06541 , H01L2225/06575 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/12042 , H01L2924/14 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929 , H01L2224/05552 , H01L2924/00
摘要： A microelectronic assembly having a through hole extending through a first wafer (or chip) and a second wafer (or chip) are provided. The first and second wafers (or chips) have confronting faces and metallic features at the faces which are joined together to assemble the first and second wafers (or chips) leaving a gap between the confronting faces. A hole is etched in the first wafer (or chip), then material is sputtered to form a wall of material in the gap between wafers (or chips). Etching continues to extend the hole into or through the second wafer (or chip). The hole is filled to form a substantially vertical through silicon conductive via.
摘要翻译：提供具有延伸穿过第一晶片（或芯片）和第二晶片（或芯片）的通孔的微电子组件。第一和第二晶片（或芯片）在面处具有面对面和金属特征，所述表面和金属特征被连接在一起以组装在相对面之间留下间隙的第一和第二晶片（或芯片）。在第一晶片（或芯片）中蚀刻孔，然后溅射材料以在晶片（或芯片）之间的间隙中形成材料壁。蚀刻继续将孔扩展到第二晶片（或芯片）中或通过第二晶片（或芯片）。该孔被填充以形成基本垂直的通过硅的导电通孔。

5. 发明授权

US08386977B2 Circuit design checking for three dimensional chip technology 有权
标题翻译：电路设计检查三维芯片技术
公开(公告)号：US08386977B2
公开(公告)日：2013-02-26
申请号：US13113421
申请日：2011-05-23
申请人： Mukta G. Farooq , John A. Griesemer , William Francis Landers , Kevin S. Petrarca , Richard Paul Volant
发明人： Mukta G. Farooq , John A. Griesemer , William Francis Landers , Kevin S. Petrarca , Richard Paul Volant
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5081
摘要： A tool that allows three dimensional chip circuit designs to be checked subsequent to 3D design layer mirroring. The 3D chip design is converted to a corresponding 2D chip design by mirroring one or more design layers from the mirrored side of a 3D design and merging those design layers with unmirrored design layers from the unmirrored side of a 3D design. The converted circuit design can be processed by standard verification checks. The tool may also receive design layers corresponding to an integrated circuit that will pass through multiple semiconductor chips. Each design cell is examined to determine if it corresponds to a mirrored or unmirrored side of its respective semiconductor chip. If the respective design cell corresponds to the mirrored side, the design cell is mirrored. All mirrored cells are then merged with the unmirrored design cells in the correct order. The merged design is processed by standard verification checks. The tool also has the capability to create terminal metal abstracts for two adjoining chips. One of the abstracts is mirrored and then merged with the other for connectivity and alignment checking.
摘要翻译：一种允许在3D设计层镜像之后检查三维芯片电路设计的工具。通过从3D设计的镜像侧镜像一个或多个设计层，将3D芯片设计转换为相应的2D芯片设计，并将这些设计层与未设计的设计层从3D设计的非镜面合并。转换电路设计可以通过标准验证检查进行处理。该工具还可以接收对应于将通过多个半导体芯片的集成电路的设计层。检查每个设计单元以确定它是否对应于其相应的半导体芯片的镜像或非镜像侧。如果相应的设计单元对应于镜像侧，则设计单元被镜像。然后所有镜像单元格以正确的顺序与未设计的设计单元合并。合并设计通过标准验证检查进行处理。该工具还可以为两个相邻的芯片创建终端金属摘要。其中一个摘要被镜像，然后与另一个摘要进行连接和对齐检查。

6. 发明授权

US08120175B2 Soft error rate mitigation by interconnect structure 有权
标题翻译：通过互连结构缓解软错误率
公开(公告)号：US08120175B2
公开(公告)日：2012-02-21
申请号：US11947832
申请日：2007-11-30
申请人： Mukta G. Farooq , Ian D. Melville , Kevin S. Petrarca
发明人： Mukta G. Farooq , Ian D. Melville , Kevin S. Petrarca
IPC分类号： H01L23/48
CPC分类号： H01L24/16 , H01L24/11 , H01L24/13 , H01L24/81 , H01L2224/05001 , H01L2224/05023 , H01L2224/05568 , H01L2224/10126 , H01L2224/1147 , H01L2224/1148 , H01L2224/1191 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2224/81801 , H01L2924/00013 , H01L2924/01005 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/15787 , H01L2224/29099 , H01L2924/00 , H01L2224/05541 , H01L2224/05005
摘要： A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.
摘要翻译：一种方法产生一种结构，其包括通过柱和开口连接到集成电路芯片的载体。因此，在这种结构中，至少一个导电柱与集成电路芯片的表面延伸一段距离或高度，并且阻挡层围绕导电柱的下部，使得阻挡层覆盖柱的高度的至少一部分最接近芯片表面。载体中至少有一个开口足够大以容纳导电柱和屏障，并且导电柱和屏障位于开口中。在开口的底部使用焊料将导电柱连接到开口的底部。屏障防止焊料接触由屏障保护的导电柱的部分。

7. 发明申请

US20120040277A1 DAMASCENE RETICLE AND METHOD OF MANUFACTURE THEREOF 失效
标题翻译：大理石制品及其制造方法
公开(公告)号：US20120040277A1
公开(公告)日：2012-02-16
申请号：US13278571
申请日：2011-10-21
申请人： Kevin S. Petrarca , Donald F. Canaperi , Mahadevaiyer Krishnan , Rebecca D. Mih , Steven Steen , Henry Grabarz , Michael S. Hibbs
发明人： Kevin S. Petrarca , Donald F. Canaperi , Mahadevaiyer Krishnan , Rebecca D. Mih , Steven Steen , Henry Grabarz , Michael S. Hibbs
IPC分类号： G03F1/00 , B24B41/06
CPC分类号： G03F1/00 , G03F1/26 , G03F1/50
摘要： A reticle carrier for a polishing tool capable of accommodating a reticle includes a base plate with an obverse and reverse surfaces, a retaining ring secured to the obverse surface of the base plate forming a recess defined by the obverse surface of the rigid base plate and internal edges of the retaining ring. A reticle pad supports a reticle in the recess. The base plate and the reticle pad having an array of matching, aligned passageway holes therethrough for exhaustion of air from space between the base plate and a the reticle and for supply of air to that space so a vacuum can retain a the reticle in place on the reticle carrier under vacuum conditions and application of air under pressure can eject a reticle from the reticle carrier.
摘要翻译：用于能够容纳标线的抛光工具的掩模版载体包括具有正面和反面的基板，固定在基板的正面的保持环，形成由刚性基板的正面限定的凹部和内部固定环的边缘。掩模垫在凹槽中支撑掩模版。基板和标线垫具有一组匹配的对准的通孔，用于从底板和标线板之间的空间排出空气，并将空气供给到该空间，因此真空可以将该掩模版保持在适当的位置上在真空条件下的掩模版载体和在压力下施加空气可以从掩模版载体喷出掩模版。

8. 发明申请

US20110318865A1 MANUFACTURING PROCESS FOR MAKING PHOTOVOLTAIC SOLAR CELLS 失效
标题翻译：制造光伏太阳能电池的制造工艺
公开(公告)号：US20110318865A1
公开(公告)日：2011-12-29
申请号：US13154140
申请日：2011-06-06
申请人： Ranier Krauser , Lawrence A. Clevenger , Kevin Prettyman , Brian Christopher Sapp , Kevin S. Petrarca , Harold John Hovel , Gerd Pfeiffer , Zhengwen Li , Carl John Radens
发明人： Ranier Krauser , Lawrence A. Clevenger , Kevin Prettyman , Brian Christopher Sapp , Kevin S. Petrarca , Harold John Hovel , Gerd Pfeiffer , Zhengwen Li , Carl John Radens
IPC分类号： H01L31/18
CPC分类号： H01L31/1804 , H01L31/02167 , H01L31/022425 , H01L31/068 , Y02E10/547 , Y02P70/521
摘要： The invention relates to a manufacturing process of a photovoltaic solar cell (100) comprising: providing high doped areas (20) on the rear side (18) of the photovoltaic solar cell (100), providing localized metal contacts (30) localized on said high doped areas (20), providing a passivation layer (50) covering a surface (52) between said contacts (30), wherein the contacts (30) remain substantially free of the passivation layer (50), and depositing a metal layer (32) for a back surface field.
摘要翻译：本发明涉及一种光伏太阳能电池（100）的制造方法，包括：在光伏太阳能电池（100）的后侧（18）上提供高掺杂区域（20），提供位于所述光伏太阳能电池（100）上的局部金属触点（30）提供覆盖所述触头（30）之间的表面（52）的钝化层（50），其中触点（30）保持基本上不含钝化层（50），并沉积金属层（50） 32）用于背面场。

9. 发明授权

US08017997B2 Vertical metal-insulator-metal (MIM) capacitor using gate stack, gate spacer and contact via 有权
标题翻译：垂直金属绝缘体金属（MIM）电容器，采用栅极叠层，栅极隔离和接触通孔
公开(公告)号：US08017997B2
公开(公告)日：2011-09-13
申请号：US12344697
申请日：2008-12-29
申请人： Ramachandra Divakaruni , Mukta G. Farooq , Jeffrey P. Gambino , Kevin S. Petrarca
发明人： Ramachandra Divakaruni , Mukta G. Farooq , Jeffrey P. Gambino , Kevin S. Petrarca
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L28/60 , H01L21/76897 , H01L23/485 , H01L27/0629 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure including a vertical metal-insulator-metal capacitor, and a method for fabricating the semiconductor structure including the vertical metal-insulator-metal capacitor, each use structural components from a dummy metal oxide semiconductor field effect transistor located and formed over an isolation region located over a semiconductor substrate. The dummy metal oxide field effect transistor may be formed simultaneously with a metal oxide semiconductor field effect transistor located over a semiconductor substrate that includes the isolation region. The metal-insulator-metal capacitor uses a gate as a capacitor plate, a uniform thickness gate spacer as a gate dielectric and a contact via as another capacitor plate. The uniform thickness gate spacer may include a conductor layer for enhanced capacitance. A mirrored metal-insulator-metal capacitor structure that uses a single contact via may also be used for enhanced capacitance.
摘要翻译：包括垂直金属 - 绝缘体 - 金属电容器的半导体结构以及包括垂直金属 - 绝缘体 - 金属电容器的半导体结构的制造方法，每个都使用位于隔离层上并形成的虚设金属氧化物半导体场效应晶体管的结构部件区域位于半导体衬底上。虚拟金属氧化物场效应晶体管可以与位于包括隔离区域的半导体衬底之上的金属氧化物半导体场效应晶体管同时形成。金属 - 绝缘体 - 金属电容器使用栅极作为电容器板，均匀厚度的栅极间隔物作为栅极电介质和作为另一个电容器板的接触通孔。均匀厚度的栅极间隔物可以包括用于增强电容的导体层。使用单个接触通孔的镜像金属 - 绝缘体 - 金属电容器结构也可用于增强电容。

10. 发明申请

US20110092069A1 SELF-ALIGNED PATTERNED ETCH STOP LAYERS FOR SEMICONDUCTOR DEVICES 失效
标题翻译：用于半导体器件的自对准图形蚀刻停止层
公开(公告)号：US20110092069A1
公开(公告)日：2011-04-21
申请号：US12582137
申请日：2009-10-20
申请人： Kangguo Cheng , Lawrence A. Clevenger , Johnathan E. Faltermeier , Stephan Grunow , Kaushik A. Kumar , Kevin S. Petrarca
发明人： Kangguo Cheng , Lawrence A. Clevenger , Johnathan E. Faltermeier , Stephan Grunow , Kaushik A. Kumar , Kevin S. Petrarca
IPC分类号： H01L21/3205 , H01L21/768
CPC分类号： H01L21/76808 , H01L21/76802 , H01L21/7681 , H01L21/76825 , H01L21/76829
摘要： A method of forming a semiconductor device includes patterning a photoresist layer formed over a homogeneous semiconductor device layer to be etched; subjecting the semiconductor device to an implant process that selectively implants a sacrificial etch stop layer that is self-aligned in accordance with locations of features to be etched within the homogeneous semiconductor device layer, and at a desired depth for the features to be etched; etching a feature pattern defined by the patterned photoresist layer into the homogenous semiconductor device layer, stopping on the implanted sacrificial etch stop layer; and removing remaining portion of the implanted sacrificial etch stop layer prior to filling the etched feature pattern with a fill material.
摘要翻译：形成半导体器件的方法包括：图案化在待蚀刻的均匀半导体器件层上形成的光致抗蚀剂层; 对半导体器件进行注入工艺，该注入工艺根据待均匀半导体器件层内待蚀刻的特征的位置以及在要蚀刻的特征的期望深度选择性地埋入自对准的牺牲蚀刻停止层; 将由图案化的光致抗蚀剂层限定的特征图案蚀刻成均匀的半导体器件层，停止在注入的牺牲蚀刻停止层上; 以及在用填充材料填充蚀刻的特征图案之前去除注入的牺牲蚀刻停止层的剩余部分。

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