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1. 发明授权

US07098476B2 Multilayer interconnect structure containing air gaps and method for making 有权
公开(公告)号：US07098476B2
公开(公告)日：2006-08-29
申请号：US10949837
申请日：2004-09-24
申请人： Katherina E. Babich , Roy Arthur Carruthers , Timothy Joseph Dalton , Alfred Grill , Jeffrey Curtis Hedrick , Christopher Vincent Jahnes , Ebony Lynn Mays , Laurent Perraud , Sampath Purushothaman , Katherine Lynn Saenger
发明人： Katherina E. Babich , Roy Arthur Carruthers , Timothy Joseph Dalton , Alfred Grill , Jeffrey Curtis Hedrick , Christopher Vincent Jahnes , Ebony Lynn Mays , Laurent Perraud , Sampath Purushothaman , Katherine Lynn Saenger
IPC分类号： H01L31/20 , H01L29/04
CPC分类号： H01L21/76831 , H01L21/7681 , H01L21/7682 , H01L21/76834 , H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.

2. 发明授权

US06815329B2 Multilayer interconnect structure containing air gaps and method for making 有权
标题翻译：包含气隙的多层互连结构和制造方法
公开(公告)号：US06815329B2
公开(公告)日：2004-11-09
申请号：US10117797
申请日：2002-04-02
申请人： Katherina E. Babich , Roy Arthur Carruthers , Timothy Joseph Dalton , Alfred Grill , Jeffrey Curtis Hedrick , Christopher Vincent Jahnes , Ebony Lynn Mays , Laurent Perraud , Sampath Purushothaman , Katherine Lynn Saenger
发明人： Katherina E. Babich , Roy Arthur Carruthers , Timothy Joseph Dalton , Alfred Grill , Jeffrey Curtis Hedrick , Christopher Vincent Jahnes , Ebony Lynn Mays , Laurent Perraud , Sampath Purushothaman , Katherine Lynn Saenger
IPC分类号： H01L214763
CPC分类号： H01L21/76831 , H01L21/7681 , H01L21/7682 , H01L21/76834 , H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.
摘要翻译：描述了一种新颖的含气隙的互连布线结构，其在通孔级中结合有固体低k电介质，并且在布线层中结合了复合固体和气隙电介质。还提供了形成这种互连结构的方法。该方法很容易扩展到包含多个布线级别的互连结构，并且与双镶嵌后端（BEOL）处理兼容。

3. 发明授权

US07081676B2 Structure for controlling the interface roughness of cobalt disilicide 有权
标题翻译：控制二硅化钴界面粗糙度的结构
公开(公告)号：US07081676B2
公开(公告)日：2006-07-25
申请号：US10691299
申请日：2003-10-22
申请人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
发明人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
IPC分类号： H01L29/40 , H01L23/48 , H01L23/52
CPC分类号： H01L23/485 , H01L21/28518 , H01L2924/0002 , H01L2924/00
摘要： A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.
摘要翻译：本文公开了一种制造具有降低的界面粗糙度的电接触以及电接触本身的方法。本发明的方法包括（a）在含硅基材上形成具有式MX的合金层，其中M是选自Co和Ni的金属，X是合金添加剂; （b）任选地在所述合金层上形成任选的氧阻隔层; （c）在足以在所述结构中形成MXSi层的温度下退火所述合金层; （d）除去所述任选的氧气阻挡层和任何剩余的合金层; 以及任选地（e）在足以在所述结构中形成MXSi 2层的温度下退火所述MXSi层。

4. 发明授权

US06503641B2 Interconnects with Ti-containing liners 有权
标题翻译：与含Ti衬板互连
公开(公告)号：US06503641B2
公开(公告)日：2003-01-07
申请号：US09740089
申请日：2000-12-18
申请人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Chao-Kun Hu , Kim Yang Lee , Ismail Cevdet Noyan , Robert Rosenberg , Thomas McCarroll Shaw
发明人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Chao-Kun Hu , Kim Yang Lee , Ismail Cevdet Noyan , Robert Rosenberg , Thomas McCarroll Shaw
IPC分类号： B32B1501
CPC分类号： H01L21/76843 , B32B15/01 , C22C27/02 , H01L21/76846 , H01L23/53223 , H01L23/53238 , H01L2924/0002 , Y10S428/929 , Y10S428/935 , Y10S428/936 , Y10S428/938 , Y10T428/12639 , Y10T428/12743 , Y10T428/12806 , Y10T428/12812 , Y10T428/12819 , Y10T428/12826 , Y10T428/12833 , Y10T428/1284 , Y10T428/12903 , H01L2924/00
摘要： An electrical conductor for use in an electronic structure is disclosed which includes a conductor body that is formed of an alloy including between about 0.001 atomic % and about 2 atomic % of an element selected from the group consisting of Ti, Zr, In, Sn and Hf; and a liner abutting the conductor body which is formed of an alloy that includes Ta, W, Ti, Nb and V. The invention further discloses a liner for use in a semiconductor interconnect that is formed of a material selected from the group consisting of Ti, Hf, In, Sn, Zr and alloys thereof, TiCu3, Ta1−XTix, Ta1−X, Hfx, Ta1−X, Inxy, Ta1−XSnx, Ta1−XZrx.
摘要翻译：公开了一种用于电子结构的电导体，其包括由合金构成的导体，该合金包括选自Ti，Zr，In，Sn中的元素的约0.001原子％至约2原子％，以及 Hf; 以及与包括Ta，W，Ti，Nb和V的合金形成的导体本体的衬垫。本发明还公开了一种用于半导体互连的衬垫，其由选自Ti ，Hf，In，Sn，Zr及其合金，TiCu3，Ta1-XTix，Ta1-X，Hfx，Ta1-X，Inxy，Ta1-XSnx，Ta1-XZrx。

5. 发明授权

US06440851B1 Method and structure for controlling the interface roughness of cobalt disilicide 失效
标题翻译：控制二硅化钴界面粗糙度的方法和结构
公开(公告)号：US06440851B1
公开(公告)日：2002-08-27
申请号：US09416083
申请日：1999-10-12
申请人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
发明人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
IPC分类号： H01L2144
CPC分类号： H01L23/485 , H01L21/28518 , H01L2924/0002 , H01L2924/00
摘要： A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.
摘要翻译：本文公开了一种制造具有降低的界面粗糙度的电接触以及电接触本身的方法。本发明的方法包括（a）在含硅基材上形成具有式MX的合金层，其中M是选自Co和Ni的金属，X是合金添加剂; （b）任选地在所述合金层上形成任选的氧阻隔层; （c）在足以在所述结构中形成MXSi层的温度下退火所述合金层; （d）除去所述任选的氧气阻挡层和任何剩余的合金层; 以及任选地（e）在足以在所述结构中形成MXSi 2层的温度下退火所述MXSi层。

6. 发明授权

US06413859B1 Method and structure for retarding high temperature agglomeration of silicides using alloys 失效
标题翻译：使用合金阻止硅化物高温聚集的方法和结构
公开(公告)号：US06413859B1
公开(公告)日：2002-07-02
申请号：US09519898
申请日：2000-03-06
申请人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Paul Michael Kozlowski , Christian Lavoie , Joseph Scott Newbury , Ronnen Andrew Roy
发明人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Paul Michael Kozlowski , Christian Lavoie , Joseph Scott Newbury , Ronnen Andrew Roy
IPC分类号： H01L214763
CPC分类号： H01L21/28518 , H01L21/823814
摘要： Complementary metal oxide semiconductor (CMOS) devices having metal silicide contacts that withstand the high temperature anneals used in activating the source/drain regions of the devices are provided by adding at least one alloying element to an initial metal layer used in forming the silicide.
摘要翻译：通过向用于形成硅化物的初始金属层添加至少一种合金元素，提供具有金属硅化物接触的互补金属氧化物半导体（CMOS）器件，其具有经受用于激活器件的源极/漏极区域的高温退火。

7. 发明授权

US07102234B2 Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy 有权
标题翻译：使用金属锗合金降低金属硅化物的接触电阻的方法和结构
公开(公告)号：US07102234B2
公开(公告)日：2006-09-05
申请号：US10827064
申请日：2004-04-19
申请人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Ronnen Andrew Roy , Yun Yu Wang
发明人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Ronnen Andrew Roy , Yun Yu Wang
IPC分类号： H01L23/48 , H01L29/40
CPC分类号： H01L21/28518
摘要： A method of reducing the contact resistance of metal silicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g., Co—Ge or Ti—Ge, two annealing steps are required to provide the lowest resistance phase of those metals, whereas, when Ni is employed, a single annealing step forms the lowest resistance phase of Ni silicide.
摘要翻译：一种降低金属硅化物与衬底的p +硅区域或n +硅区域的接触电阻的方法，包括：（a）在含硅衬底上形成金属锗（Ge）层，其中所述金属选自由Co，Ti，Ni及其混合物组成的组; （b）任选地在所述金属锗层上形成氧阻隔层; （c）在有效地将其至少一部分转化成基本上不可蚀刻的金属硅化物层的温度下退火所述金属锗层，同时在所述含硅衬底和所述基本上不可蚀刻的衬底之间形成Si-Ge中间层金属硅化物层; 和（d）去除所述任选的氧气阻挡层和任何剩余的合金层。当使用Co或Ti合金时，例如Co-Ge或Ti-Ge，需要两个退火步骤来提供这些金属的最低电阻相，而在使用Ni时，单个退火步骤形成最低的电阻相的Ni硅化物。

8. 发明授权

US06809030B2 Method and structure for controlling the interface roughness of cobalt disilicide 失效
标题翻译：控制二硅化钴界面粗糙度的方法和结构
公开(公告)号：US06809030B2
公开(公告)日：2004-10-26
申请号：US10185547
申请日：2002-06-28
申请人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
发明人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
IPC分类号： H01L2144
CPC分类号： H01L23/485 , H01L21/28518 , H01L2924/0002 , H01L2924/00
摘要： A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additives over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.
摘要翻译：本文公开了一种制造具有降低的界面粗糙度的电接触以及电接触本身的方法。本发明的方法包括（a）形成具有式MX的合金层，其中M是选自Co和Ni的金属，X是含硅基体上的合金添加剂; （b）任选地在所述合金层上形成任选的氧阻隔层; （c）在足以在所述结构中形成MXSi层的温度下退火所述合金层; （d）除去所述任选的氧气阻挡层和任何剩余的合金层; 以及任选地（e）在足以在所述结构中形成MXSi 2层的温度下退火所述MXSi层。

9. 发明授权

US06753606B2 Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy 有权
标题翻译：使用金属锗合金降低金属硅化物的接触电阻的方法和结构
公开(公告)号：US06753606B2
公开(公告)日：2004-06-22
申请号：US09994954
申请日：2001-11-27
申请人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Ronnen Andrew Roy , Yun Yu Wang
发明人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Ronnen Andrew Roy , Yun Yu Wang
IPC分类号： H01L2348
CPC分类号： H01L21/28518
摘要： A method of reducing the contact resistance of metal silicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g., Co—Ge or Ti—Ge, two annealing steps are required to provide the lowest resistance phase of those metals, whereas, when Ni is employed, a single annealing step forms the lowest resistance phase of Ni silicide.
摘要翻译：一种降低金属硅化物与衬底的p +硅区域或n +硅区域的接触电阻的方法，包括：（a）在含硅衬底上形成金属锗（Ge）层，其中所述金属选自由Co，Ti，Ni及其混合物组成的组; （b）任选地在所述金属锗层上形成氧阻隔层; （c）在有效地将其至少一部分转化成基本上不可蚀刻的金属硅化物层的温度下退火所述金属锗层，同时在所述含硅衬底和所述基本上不可蚀刻的衬底之间形成Si-Ge中间层金属硅化物层; 和（d）去除所述任选的氧气阻挡层和任何剩余的合金层。当使用Co或Ti合金时，例如Co-Ge或Ti-Ge，需要两个退火步骤来提供这些金属的最低电阻相，而在使用Ni时，单个退火步骤形成最低的电阻相的Ni硅化物。

10. 发明授权

US06503833B1 Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby 有权
标题翻译：自对准硅化物（硅化物）工艺，用于应变硅MOSFET on SiGe和由此形成的结构
公开(公告)号：US06503833B1
公开(公告)日：2003-01-07
申请号：US09712264
申请日：2000-11-15
申请人： Atul Champaklal Ajmera , Cyril Cabral, Jr. , Roy Arthur Carruthers , Kevin Kok Chan , Guy Moshe Cohen , Paul Michael Kozlowski , Christian Lavoie , Joseph Scott Newbury , Ronnen Andrew Roy
发明人： Atul Champaklal Ajmera , Cyril Cabral, Jr. , Roy Arthur Carruthers , Kevin Kok Chan , Guy Moshe Cohen , Paul Michael Kozlowski , Christian Lavoie , Joseph Scott Newbury , Ronnen Andrew Roy
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/28518 , H01L29/1054 , H01L29/7834
摘要： A method of forming a semiconductor substrate (and resultant structure), includes providing a semiconductor substrate to be silicided including a source and drain formed therein on respective sides of a gate, depositing a metal film over the gate, source and drain regions, reacting the metal film with Si at a first predetermined temperature, to form a metal-silicon alloy, etching the unreacted metal, depositing a silicon film over the source drain and gate regions, annealing the substrate at a second predetermined temperature, to form a metal-Si2 alloy, and selectively etching the unreacted Si.
摘要翻译：一种形成半导体衬底（及其结构）的方法，包括在栅极的各个侧面上设置硅化物半导体衬底，该半导体衬底包括形成在其中的源极和漏极，在栅极，源极和漏极区域上沉积金属膜，在第一预定温度下具有Si的金属膜，以形成金属 - 硅合金，蚀刻未反应的金属，在源极漏极和栅极区域上沉积硅膜，在第二预定温度下退火衬底以形成金属-Si2 合金，并选择性地蚀刻未反应的Si。

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