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1. 发明授权

US06367051B1 System and method for concurrent buffer insertion and placement of logic gates 失效
标题翻译：并行缓冲区插入和放置逻辑门的系统和方法
公开(公告)号：US06367051B1
公开(公告)日：2002-04-02
申请号：US09096810
申请日：1998-06-12
申请人： Lawrence Pileggi , Sharad Malik , Emre Tuncer , Abhijeet Chakraborty , Satyamurthy Pullela , Altan Odabasioglu , Douglas B. Boyle
发明人： Lawrence Pileggi , Sharad Malik , Emre Tuncer , Abhijeet Chakraborty , Satyamurthy Pullela , Altan Odabasioglu , Douglas B. Boyle
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： A design tool for integrated circuits includes a placement tool which concurrently places logic gates and interconnect. In one embodiment, the logic gates are placed into bins and virtual buffers are inserted between logic gates mapped to different bins. Placement and interconnect wire lengths and densities are successively improved leading to removal of some buffers and actualization of the virtual buffers.
摘要翻译：用于集成电路的设计工具包括同时放置逻辑门和互连的放置工具。在一个实施例中，逻辑门被放置到存储区中，并且虚拟缓冲器被插入映射到不同仓的逻辑门之间。放置和互连线长度和密度被连续改善，导致一些缓冲器的移除和虚拟缓冲器的实现。

2. 发明授权

US06651232B1 Method and system for progressive clock tree or mesh construction concurrently with physical design 有权
标题翻译：与物理设计同时进行的时钟树或网格构造的方法和系统
公开(公告)号：US06651232B1
公开(公告)日：2003-11-18
申请号：US09186430
申请日：1998-11-05
申请人： Lawrence Pileggi , Christopher Dunn , Satyamurthy Pullela , Majid Sarrafzadeh , Tong Gao , Salil Raje
发明人： Lawrence Pileggi , Christopher Dunn , Satyamurthy Pullela , Majid Sarrafzadeh , Tong Gao , Salil Raje
IPC分类号： G06F1750
CPC分类号： G06F1/10 , G06F17/5077
摘要： Progressively optimized clock tree/mesh construction is performed concurrently with placement of all remaining objects. Clock tree/mesh is specified loosely for initial placement, then followed by progressive detailed placement. In particular, preferred approach provides automated and reliable solution to clock tree/mesh construction, occuring concurrently with placement process so that clock tree wiring and buffering considers and influences placement and wiring of all other objects, such as logic gates, memory elements, macrocells, etc. Hence, in this concurrent manner, clock tree/mesh pre-wiring and pre-buffering may be based on construction of approximate clock tree using partitioning information only, i.e., prior to object placement. Further, present approach provides modified DME-based clock tree topology construction without meandering, and recursive algorithm for buffered clock tree construction.
摘要翻译：逐渐优化的时钟树/网格构建与所有剩余对象的放置同时执行。时钟树/网格被松散地指定用于初始放置，然后是渐进的详细放置。特别地，优选的方法为时钟树/网格构造提供了自动化和可靠的解决方案，与布置过程同时发生，使得时钟树布线和缓冲考虑并影响所有其他对象（诸如逻辑门，存储器元件，宏单元）的布局和布线，因此，以这种并发方式，时钟树/网格预接线和预缓冲可以基于仅使用分区信息（即，在对象放置之前）构建近似时钟树。此外，目前的方法提供了基于改进的基于DME的时钟树拓扑构造而不进行曲折，并且缓冲时钟树构建的递归算法。

3. 发明授权

US6074429A Optimizing combinational circuit layout through iterative restructuring 失效
标题翻译：通过迭代重组优化组合电路布局
公开(公告)号：US6074429A
公开(公告)日：2000-06-13
申请号：US805865
申请日：1997-03-03
申请人： Satyamurthy Pullela , Stephen C. Moore , David Blaauw , Rajendran Panda , Gopalakrishnan Vijayan
发明人： Satyamurthy Pullela , Stephen C. Moore , David Blaauw , Rajendran Panda , Gopalakrishnan Vijayan
IPC分类号： H01L21/82 , G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045 , G06F2217/84
摘要： Speed, size, and power trade-offs of a VLSI combinational circuit are optimized through iterative restructuring. First, timing analysis for the circuit is performed (102) to find the critical path through the circuit (104). Then, a gate is selected from the critical path (106), and a window is contracted around the gate (108). Within the window, alternate structures are constructed (110) and sized (112). The best alternative is substituted into the window (114), and the new circuit is resized (116). If the new circuit is not an improvement over the old (118), then the original window is replaced (120). In any case, this is repeated for each gate in the circuit (124). The entire process is then repeated until either user constraints are met, or the circuit doesn't change (122).
摘要翻译： VLSI组合电路的速度，尺寸和功率权衡通过迭代重组进行优化。首先，执行电路的定时分析（102）以找到通过电路（104）的关键路径。然后，从关键路径（106）选择一个门，并且窗口围绕门（108）收缩。在窗口内，构造（110）和尺寸（112）的替代结构。最好的替代方案被替换到窗口（114）中，并且新电路被调整大小（116）。如果新电路不是旧的（118）的改进，那么原来的窗口被替换（120）。在任何情况下，对于电路（124）中的每个门重复这一点。然后重复整个过程直到满足用户约束，或者电路不改变（122）。

4. 发明授权

US5790415A Complementary network reduction for load modeling 失效
标题翻译：用于负载建模的互补网络简化
公开(公告)号：US5790415A
公开(公告)日：1998-08-04
申请号：US630189
申请日：1996-04-10
申请人： Satyamurthy Pullela , Abhijit Dharchoudhury , David T. Blaauw , Tim J. Edwards , Joseph W. Norton
发明人： Satyamurthy Pullela , Abhijit Dharchoudhury , David T. Blaauw , Tim J. Edwards , Joseph W. Norton
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022 , G06F2217/78
摘要： A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (405) between arrival and required times for each node. If the actual arrival time for a particular node is after the time required to meet a predetermined design constraint of the node (407), a determination (411) is made regarding the effect of that element on the nodal slack for an incremental increase in the size of that element. Thereafter an element is selected (413) for sizing increase (415) in accordance with a weighting function and the process is repeated until all of the nodes in the integrated circuit have positive slack times (407, 409). One method of accomplishing a timing analysis step (303) includes an analytical circuit simulation technique (1000-1015) in which circuit "I-V" characteristics are more precisely represented with a power series (1006) including a plurality of regional segmental approximations (901-907). Another method of timing analysis includes an equivalency methodology (1501-1513) of translating passive transistors to equivalent RC networks (801). In the overall optimization process, a method is provided (1701-1715) for automatically correcting transistor predicted sensitivities based upon a correction factor (1713). A multi-model timing method (1601-1619) is also illustrated (1601-1619) for synergistically combining fast and accurate circuit timing models to optimize the speed and accuracy of the design process itself while remaining within an accuracy threshold.
摘要翻译：用于最佳地确定集成电路元件的尺寸的过程和实现计算机系统（13）包括确定集成电路内所有节点处的处理信号的实际到达时间和所需的到达时间（403），并确定到达之间的松弛或差异（405）和每个节点所需的时间。如果特定节点的实际到达时间在满足节点（407）的预定设计约束所需的时间之后，则确定（411）关于该元素对节点松弛的影响，以增加节点该元素的大小。此后，根据加权函数选择用于尺寸增加（415）的元件（413），并重复该过程，直到集成电路中的所有节点具有正的松弛时间（407,409）。实现定时分析步骤（303）的一种方法包括一种分析电路仿真技术（1000-1015），其中电路“IV”特性被更精确地用包括多个区域分段近似（901- 907）。定时分析的另一种方法包括将无源晶体管转换为等效RC网络的等效方法（1501-1513）（801）。在整体优化过程中，提供了一种基于校正因子（1713）自动校正晶体管预测灵敏度的方法（1701-1715）。还示出了多模式定时方法（1601-1619）（1601-1619），用于协同地组合快速和精确的电路定时模型，以优化设计过程本身的速度和精度，同时保持在精度阈值内。

5. 发明授权

US5903471A Method for optimizing element sizes in a semiconductor device 失效
标题翻译：用于优化半导体器件中的元件尺寸的方法
公开(公告)号：US5903471A
公开(公告)日：1999-05-11
申请号：US805862
申请日：1997-03-03
申请人： Satyamurthy Pullela , Timothy J. Edwards , Joseph Norton , Abhijit Dharchoudhury , David Blaauw
发明人： Satyamurthy Pullela , Timothy J. Edwards , Joseph Norton , Abhijit Dharchoudhury , David Blaauw
IPC分类号： H01L21/82 , G06F17/50 , G06F19/00
CPC分类号： G06F17/505
摘要： A slack time, based on a required and actual delay time, is calculated for each node in a circuit (302). For each element in the circuit, a sensitivity (304) and a figure of merit (306) is calculated. A variance is determined for the calculated figure of merits (308). The circuit element having the smallest absolute figure or merit is optimized when the variance is smaller than a predefined threshold (310, 312).
摘要翻译：对于电路中的每个节点（302）计算基于所需和实际延迟时间的松弛时间。对于电路中的每个元件，计算灵敏度（304）和品质因数（306）。对于计算出的品质因数确定方差（308）。当方差小于预定阈值（310,312）时，优化具有最小绝对值或优点的电路元件。

6. 发明授权

US5787008A Simulation corrected sensitivity 失效
标题翻译：模拟校正灵敏度
公开(公告)号：US5787008A
公开(公告)日：1998-07-28
申请号：US629488
申请日：1996-04-10
申请人： Satyamurthy Pullela , Abhijit Dharchoudhury , David T. Blaauw , Tim J. Edwards , Joseph W. Norton , Peter R. O'Brien
发明人： Satyamurthy Pullela , Abhijit Dharchoudhury , David T. Blaauw , Tim J. Edwards , Joseph W. Norton , Peter R. O'Brien
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/505
摘要： A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (405) between arrival and required times for each node. If the actual arrival time for a particular node is after the time required to meet a predetermined design constraint of the node (407), a determination (411) is made regarding the effect of that element on the nodal slack for an incremental increase in the size of that element. Thereafter an element is selected (413) for sizing increase (415) in accordance with a weighting function and the process is repeated until all of the nodes in the integrated circuit have positive slack times (407, 409). One method of accomplishing a timing analysis step (303) includes an analytical circuit simulation technique (1000-1015) in which circuit "I-V" characteristics are more precisely represented with a power series (1006) including a plurality of regional segmental approximations (901-907). Another method of timing analysis includes an equivalency methodology (1501-1513) of translating passive transistors to equivalent RC networks (801). In the overall optimization process, a method is provided (1701-1715) for automatically correcting transistor predicted sensitivities based upon a correction factor (1713). A multi-model timing method (1601-1619) is also illustrated (1601-1619) for synergistically combining fast and accurate circuit timing models to optimize the speed and accuracy of the design process itself while remaining within an accuracy threshold.
摘要翻译：用于最佳地确定集成电路元件的尺寸的过程和实现计算机系统（13）包括确定集成电路内所有节点处的处理信号的实际到达时间和所需的到达时间（403），并确定到达之间的松弛或差异（405）和每个节点所需的时间。如果特定节点的实际到达时间在满足节点（407）的预定设计约束所需的时间之后，则确定（411）关于该元素对节点松弛的影响，以增加节点该元素的大小。此后，根据加权函数选择用于尺寸增加（415）的元件（413），并重复该过程，直到集成电路中的所有节点具有正的松弛时间（407,409）。实现定时分析步骤（303）的一种方法包括一种分析电路仿真技术（1000-1015），其中电路“IV”特性被更精确地用包括多个区域分段近似（901- 907）。定时分析的另一种方法包括将无源晶体管转换为等效RC网络的等效方法（1501-1513）（801）。在整体优化过程中，提供了一种基于校正因子（1713）自动校正晶体管预测灵敏度的方法（1701-1715）。还示出了多模式定时方法（1601-1619）（1601-1619），用于协同地组合快速和精确的电路定时模型，以优化设计过程本身的速度和精度，同时保持在精度阈值内。

7. 发明授权

US5751593A Accurate delay prediction based on multi-model analysis 失效
标题翻译：基于多模型分析的精确延迟预测
公开(公告)号：US5751593A
公开(公告)日：1998-05-12
申请号：US629487
申请日：1996-04-10
申请人： Satyamurthy Pullela , Abhijit Dharchoudhury , David T. Blaauw , Tim J. Edwards , Joseph W. Norton
发明人： Satyamurthy Pullela , Abhijit Dharchoudhury , David T. Blaauw , Tim J. Edwards , Joseph W. Norton
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/505
摘要： A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (405) between arrival and required times for each node. If the actual arrival time for a particular node is after the time required to meet a predetermined design constraint of the node (407), a determination (411) is made regarding the effect of that element on the nodal slack for an incremental increase in the size of that element. Thereafter an element is selected (413) for sizing increase (415) in accordance with a weighting function and the process is repeated until all of the nodes in the integrated circuit have positive slack times (407,409). One method of accomplishing a timing analysis step (303) includes an analytical circuit simulation technique (1000-1015) in which circuit "I-V" characteristics are more precisely represented with a power series (1006) including a plurality of regional segmental approximations (901-907). Another method of timing analysis includes an equivalency methodology (1501-1513) of translating passive transistors to equivalent RC networks (801). In the overall optimization process, a method is provided (1701-1715) for automatically correcting transistor predicted sensitivities based upon a correction factor (1713). A multi-model timing method (1601-1619) is also illustrated (1601-1619) for synergistically combining fast and accurate circuit timing models to optimize the speed and accuracy of the design process itself while remaining within an accuracy threshold.
摘要翻译：用于最佳地确定集成电路元件的尺寸的过程和实现计算机系统（13）包括确定集成电路内所有节点处的处理信号的实际到达时间和所需的到达时间（403），并确定到达之间的松弛或差异（405）和每个节点所需的时间。如果特定节点的实际到达时间在满足节点（407）的预定设计约束所需的时间之后，则确定（411）关于该元素对节点松弛的影响，以增加节点该元素的大小。此后，根据加权函数选择用于调整尺寸增加的元件（413），并重复该过程，直到集成电路中的所有节点具有正的松弛时间（407,409）。实现定时分析步骤（303）的一种方法包括一种分析电路仿真技术（1000-1015），其中电路“IV”特性被更精确地用包括多个区域分段近似（901- 907）。定时分析的另一种方法包括将无源晶体管转换为等效RC网络的等效方法（1501-1513）（801）。在整体优化过程中，提供了一种基于校正因子（1713）自动校正晶体管预测灵敏度的方法（1701-1715）。还示出了多模式定时方法（1601-1619）（1601-1619），用于协同地组合快速和精确的电路定时模型，以优化设计过程本身的速度和精度，同时保持在精度阈值内。

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