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1. 发明授权

US06700164B1 Tungsten hot wire current limiter for ESD protection 失效
标题翻译：钨热线电流限制器，用于ESD保护
公开(公告)号：US06700164B1
公开(公告)日：2004-03-02
申请号：US09611812
申请日：2000-07-07
申请人： Ciaran J. Brennan , Kevin A. Duncan , William R. Tonti , Steven H. Voldman
发明人： Ciaran J. Brennan , Kevin A. Duncan , William R. Tonti , Steven H. Voldman
IPC分类号： H01L2362
CPC分类号： H01L23/62 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In order to divert damaging currents into an electrostatic discharge (ESD) protection device during an ESD event, a tungsten wire resistor is incorporated into a current path connected in parallel with the ESD protection circuitry. The tungsten wire resistor has linear current-voltage (IV) characteristics at low currents, and non-linear IV characteristics at high current levels. The width and length of the resistor is chosen so that the resistor experiences significant self-heating caused by the higher currents generated by the ESD event. At a higher current level, the resistor becomes hot and its resistance increases dramatically. As a result the voltage drop across it increases thus diverting excess current into the parallel connected ESD protection circuitry. This limits the current through the resistor and thereby protects circuit elements in series with the resistor.
摘要翻译：为了在ESD事件期间将损坏电流转移到静电放电（ESD）保护装置中，钨线电阻器被并入到与ESD保护电路并联连接的电流路径中。钨丝电阻器在低电流下具有线性电流电压（IV）特性，在高电流水平下具有非线性IV特性。选择电阻器的宽度和长度，使得电阻器经受由ESD事件产生的较高电流引起的显着的自身加热。在较高的电流水平，电阻变热，其电阻急剧增加。因此，其上的压降增加，从而将过剩电流转移到并联的ESD保护电路中。这限制了通过电阻器的电流，从而保护与电阻器串联的电路元件。

2. 发明授权

US07543203B2 LSSD-compatible edge-triggered shift register latch 有权
标题翻译： LSSD兼容边沿触发移位寄存器锁存器
公开(公告)号：US07543203B2
公开(公告)日：2009-06-02
申请号：US10708382
申请日：2004-02-27
申请人： Gerry Ashton , Kevin A. Duncan , Terry D. Keim , Toshiharu Saitoh , Tad J. Wilder
发明人： Gerry Ashton , Kevin A. Duncan , Terry D. Keim , Toshiharu Saitoh , Tad J. Wilder
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/318552
摘要： A shift register latch (SRL) (300, 304, 400) compatible with performing level sensitive scan design (LSSD) testing with a single scan clock (SCAN CLK) and single scan clock tree (64). The SRL includes a master latch (308, 308′, 404), a slave latch (312, 312′, 408) and a circuit element (328, 328′, 416) connected between the scan clock tree and the master latch. The scan clock generates a clock signal (350, 440) having regularly spaced pulses during the scan phase of the LSSD testing. The circuit element generates a short-pulsed signal (354, 354′) based on the scan clock signal for triggering the master latch. This short-pulsed signal compensates for any delay in the clock signal due to the physical length of the signal path from the scan clock to the SRL, thereby preventing scanned data from being flushed through a scan chain of the SRLs of the present invention
摘要翻译：与使用单个扫描时钟（SCAN CLK）和单个扫描时钟树（64）执行电平敏感扫描设计（LSSD）测试兼容的移位寄存器锁存器（SRL）（300,304,400）。 SRL包括主锁存器（308,308'，404），从锁存器（312,312'，408）和连接在扫描时钟树和主锁存器之间的电路元件（328,328'，416）。在LSSD测试的扫描阶段期间，扫描时钟产生具有规则间隔脉冲的时钟信号（350,440）。电路元件基于用于触发主锁存器的扫描时钟信号产生短脉冲信号（354,354'）。这种短脉冲信号由于从扫描时钟到SRL的信号路径的物理长度来补偿时钟信号中的任何延迟，从而防止扫描数据被冲洗穿过本发明的SRL的扫描链

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