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1. 发明授权

US06661097B1 Ti liner for copper interconnect with low-k dielectric 失效
标题翻译：用于低k电介质的铜互连的Ti衬垫
公开(公告)号：US06661097B1
公开(公告)日：2003-12-09
申请号：US10287155
申请日：2002-11-01
申请人： Larry Clevenger , Stanley J. Klepeis , Hsiao-Ling Lu , Jeffrey R. Marino , Andrew Herbert Simon , Yun-Yu Wang , Kwong Hon Wong , Chih-Chao Yang
发明人： Larry Clevenger , Stanley J. Klepeis , Hsiao-Ling Lu , Jeffrey R. Marino , Andrew Herbert Simon , Yun-Yu Wang , Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/76846 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In copper backend integrated circuit technology, advanced technology using low-k organic-based interlayer dielectrics have a problem of carbon contamination that dos not occur in circuits using oxide as dielectric. A composite liner layer for the copper lines uses Ti as the bottom layer, which has the property of gettering carbon and other contaminants. The known problem with Ti of reacting with copper to form a high resistivity compound is avoided by adding a layer of TiN, which isolates the Ti and the copper.
摘要翻译：在铜后端集成电路技术中，使用低k有机基层间电介质的先进技术具有碳污染的问题，在使用氧化物作为电介质的电路中不会发生这种问题。用于铜线的复合衬里层使用Ti作为底层，其具有吸除碳和其它污染物的性质。通过添加一层分离Ti和铜的TiN层，避免了与铜反应形成高电阻率化合物的Ti的已知问题。

2. 发明授权

US06249138B1 Method for testing leakage current caused self-aligned silicide 有权
标题翻译：泄漏电流测试方法引起自对准硅化物
公开(公告)号：US06249138B1
公开(公告)日：2001-06-19
申请号：US09447846
申请日：1999-11-23
申请人： Michael WC Huang , Gwo-Shii Yang , Hsiao-Ling Lu , Wen-Yi Hsieh
发明人： Michael WC Huang , Gwo-Shii Yang , Hsiao-Ling Lu , Wen-Yi Hsieh
IPC分类号： G01R3126
CPC分类号： G01R31/2648
摘要： A method of testing a leakage current caused by a self-aligned silicide process is described. The invention uses different test structure to monitor degree of and reason for a leakage current caused by a self-aligned silicide process. While monitoring a self-aligned silicide process performed on a metal-oxide semiconductor transistor without a LDD region, in addition to considering a leakage current occurring from the metal silicide layer to the junction and occurring at edge of the metal silicide layer, the invention further considers a leakage current at comer of the metal silicide layer. For a metal-oxide semiconductor transistor having a LDD region, the invention further considers a leakage current from the metal silicide layer to the LDD region. The invention monitors a leakage current at comer of the metal silicide layer.
摘要翻译：描述了由自对准硅化物工艺引起的漏电流的测试方法。本发明使用不同的测试结构来监测由自对准硅化物工艺引起的漏电流的程度和原因。在监视对没有LDD区域的金属氧化物半导体晶体管进行的自对准硅化物处理的同时，除了考虑从金属硅化物层发生到结以及在金属硅化物层的边缘处发生的漏电流之外，本发明进一步考虑在金属硅化物层的角落处的漏电流。对于具有LDD区域的金属氧化物半导体晶体管，本发明还考虑了从金属硅化物层到LDD区域的漏电流。本发明监测金属硅化物层的角落处的漏电流。

3. 发明授权

US07544305B2 Chemical mechanical polishing process for forming shallow trench isolation structure 有权
标题翻译：用于形成浅沟槽隔离结构的化学机械抛光工艺
公开(公告)号：US07544305B2
公开(公告)日：2009-06-09
申请号：US11863665
申请日：2007-09-28
申请人： Chia-Jung Hsu , Art Yu , Hsiao-Ling Lu , Teng-Chun Tsai
发明人： Chia-Jung Hsu , Art Yu , Hsiao-Ling Lu , Teng-Chun Tsai
IPC分类号： B44C1/22
CPC分类号： H01L21/76229 , H01L21/31053
摘要： A shallow trench isolation (STI) multistage chemical mechanical polishing (CMP) method for forming a shallow trench isolation structure is provided. The substrate comprising a dense region and an isolation region, a silicon nitride layer formed over the substrate, a plurality of trenches formed in the silicon nitride layer and the substrate, an oxide layer formed over the substrate, filling the trenches, wherein a width of the trenches in the dense region is smaller than that in the isolation region. A first polishing step is performed to remove a portion of the silicon oxide layer until a thickness of the remaining portion of the oxide layer reaches a predetermined thickness. A second polishing step is performed to remove a portion of the remaining portion of the silicon oxide layer until the silicon nitride layer is exposed.
摘要翻译：提供了一种用于形成浅沟槽隔离结构的浅沟槽隔离（STI）多级化学机械抛光（CMP）方法。所述基板包括致密区域和隔离区域，在所述基板上形成的氮化硅层，形成在所述氮化硅层和所述基板中的多个沟槽，形成在所述基板上方的填充所述沟槽的氧化物层，密集区域中的沟槽小于隔离区域中的沟槽。执行第一抛光步骤以除去氧化硅层的一部分直到氧化物层的剩余部分的厚度达到预定厚度。执行第二抛光步骤以去除氧化硅层的剩余部分的一部分，直到暴露氮化硅层。

4. 发明申请

US20060172526A1 Method for preventing edge peeling defect 审中-公开
标题翻译：防止边缘剥落缺陷的方法
公开(公告)号：US20060172526A1
公开(公告)日：2006-08-03
申请号：US11331361
申请日：2006-01-13
申请人： Chia-Lin Hsu , Shu-Hsien Lee , Chien-Chien Tsai , Hsiao-Ling Lu
发明人： Chia-Lin Hsu , Shu-Hsien Lee , Chien-Chien Tsai , Hsiao-Ling Lu
IPC分类号： H01L21/4763
CPC分类号： H01L21/0209 , H01L21/02087 , H01L21/76883
摘要： A method for improving edge peeling defect is disclosed in this invention. According to this invention, a wafer can be kept from the edge peeling defect of the prior art by introducing a step for removing the weakly adhesive films and the metal structures at the wafer edge after forming a metal interconnect layer on the wafer. Thus, this invention can raise the yield of semiconductor manufacturing, and reduce the pollution chance of the chamber of the semiconductor manufacture.
摘要翻译：本发明公开了一种改善边缘剥离缺陷的方法。根据本发明，通过在晶片上形成金属互连层之后，通过引入在晶片边缘处去除弱粘合膜和金属结构的步骤，可以保持晶片免受现有技术的边缘剥离缺陷的影响。因此，本发明可以提高半导体制造的产量，并且减少半导体制造室的污染机会。

5. 发明授权

US07294575B2 Chemical mechanical polishing process for forming shallow trench isolation structure 有权
标题翻译：用于形成浅沟槽隔离结构的化学机械抛光工艺
公开(公告)号：US07294575B2
公开(公告)日：2007-11-13
申请号：US10752362
申请日：2004-01-05
申请人： Chia-Rung Hsu , Art Yu , Hsiao-Ling Lu , Teng-Chun Tsai
发明人： Chia-Rung Hsu , Art Yu , Hsiao-Ling Lu , Teng-Chun Tsai
IPC分类号： H01L31/461
CPC分类号： H01L21/76229 , H01L21/31053
摘要： A shallow trench isolation (STI) multistage chemical mechanical polishing (CMP) method for forming a shallow trench isolation structure is provided. The substrate comprising a dense region and an isolation region, a silicon nitride layer formed over the substrate, a plurality of trenches formed in the silicon nitride layer and the substrate, an oxide layer formed over the substrate, filling the trenches, wherein a width of the trenches in the dense region is smaller than that in the isolation region. A first polishing step is performed to remove a portion of the silicon oxide layer until a thickness of the remaining portion of the oxide layer reaches a predetermined thickness. A second polishing step is performed to remove a portion of the remaining portion of the silicon oxide layer until the silicon nitride layer is exposed.
摘要翻译：提供了一种用于形成浅沟槽隔离结构的浅沟槽隔离（STI）多级化学机械抛光（CMP）方法。所述基板包括致密区域和隔离区域，在所述基板上形成的氮化硅层，形成在所述氮化硅层和所述基板中的多个沟槽，形成在所述基板上方的填充所述沟槽的氧化物层，密集区域中的沟槽小于隔离区域中的沟槽。执行第一抛光步骤以除去氧化硅层的一部分直到氧化物层的剩余部分的厚度达到预定厚度。执行第二抛光步骤以去除氧化硅层的剩余部分的一部分，直到暴露氮化硅层。

6. 发明申请

US20050085163A1 Method for preventing edge peeling defect 审中-公开
标题翻译：防止边缘剥落缺陷的方法
公开(公告)号：US20050085163A1
公开(公告)日：2005-04-21
申请号：US10685588
申请日：2003-10-16
申请人： Chia-Lin Hsu , Shu-Hsien Lee , Chien-Chien Tsai , Hsiao-Ling Lu
发明人： Chia-Lin Hsu , Shu-Hsien Lee , Chien-Chien Tsai , Hsiao-Ling Lu
IPC分类号： B24B49/00 , B24B51/00 , H01L21/02
CPC分类号： H01L21/0209 , H01L21/02087
摘要： A method for improving edge peeling defect is disclosed in this invention. According to this invention, a wafer can be kept from the edge peeling defect of the prior art by introducing a step for removing the weakly adhesive films and the metal structures at the wafer edge after forming a metal interconnect layer on the wafer. Thus, this invention can raise the yield of semiconductor manufacturing, and reduce the pollution chance of the chamber of the semiconductor manufacture.
摘要翻译：本发明公开了一种改善边缘剥离缺陷的方法。根据本发明，通过在晶片上形成金属互连层之后，通过引入在晶片边缘处去除弱粘合膜和金属结构的步骤，可以保持晶片免受现有技术的边缘剥离缺陷的影响。因此，本发明可以提高半导体制造的产量，并且减少半导体制造室的污染机会。

7. 发明授权

US06235606B1 Method of fabricating shallow trench isolation 有权
标题翻译：浅沟槽隔离的制作方法
公开(公告)号：US06235606B1
公开(公告)日：2001-05-22
申请号：US09225031
申请日：1999-01-04
申请人： Michael W C Huang , Kuo-Tai Huang , Hsiao-Ling Lu , Tri-Rung Yew
发明人： Michael W C Huang , Kuo-Tai Huang , Hsiao-Ling Lu , Tri-Rung Yew
IPC分类号： H01L2176
CPC分类号： H01L21/76897 , H01L21/76224
摘要： A method for fabricating a shallow trench isolation. A pad oxide layer and a mask layer are formed over a substrate. The pad oxide layer, the mask layer, and the substrate are patterned to form a trench exposing a portion of the substrate. A liner oxide layer is formed on the substrate exposed by the trench. An isolation layer is formed over the substrate to cover the liner oxide layer. The isolation layer is conformal to the trench. An oxide layer is formed over the substrate to fill the trench. A portion of the oxide layer and the isolation layer is removed until the mask layer is exposed. The mask layer and the pad oxide layer are removed to form a shallow trench isolation.
摘要翻译：一种制造浅沟槽隔离的方法。在衬底上形成衬垫氧化物层和掩模层。将衬垫氧化物层，掩模层和衬底图案化以形成暴露衬底的一部分的沟槽。在由沟槽暴露的衬底上形成衬里氧化物层。在衬底上形成隔离层以覆盖衬里氧化物层。隔离层与沟槽保形。在衬底上形成氧化物层以填充沟槽。除去氧化物层和隔离层的一部分直到掩模层露出。去除掩模层和焊盘氧化物层以形成浅沟槽隔离。

8. 发明申请

US20050148184A1 Chemical mechanical polishing process for forming shallow trench isolation structure 有权
标题翻译：用于形成浅沟槽隔离结构的化学机械抛光工艺
公开(公告)号：US20050148184A1
公开(公告)日：2005-07-07
申请号：US10752362
申请日：2004-01-05
申请人： Chia-Rung Hsu , Art Yu , Hsiao-Ling Lu , Teng-Chun Tsai
发明人： Chia-Rung Hsu , Art Yu , Hsiao-Ling Lu , Teng-Chun Tsai
IPC分类号： H01L21/302 , H01L21/3105 , H01L21/461 , H01L21/762
CPC分类号： H01L21/76229 , H01L21/31053
摘要： A shallow trench isolation (STI) multistage chemical mechanical polishing (CMP) method for forming a shallow trench isolation structure is provided. The substrate comprising a dense region and an isolation region, a silicon nitride layer formed over the substrate, a plurality of trenches formed in the silicon nitride layer and the substrate, an oxide layer formed over the substrate, filling the trenches, wherein a width of the trenches in the dense region is smaller than that in the isolation region. A first polishing step is performed to remove a portion of the silicon oxide layer until a thickness of the remaining portion of the oxide layer reaches a predetermined thickness. A second polishing step is performed to remove a portion of the remaining portion of the silicon oxide layer until the silicon nitride layer is exposed.
摘要翻译：提供了一种用于形成浅沟槽隔离结构的浅沟槽隔离（STI）多级化学机械抛光（CMP）方法。所述基板包括致密区域和隔离区域，在所述基板上形成的氮化硅层，形成在所述氮化硅层和所述基板中的多个沟槽，形成在所述基板上方的填充所述沟槽的氧化物层，密集区域中的沟槽小于隔离区域中的沟槽。执行第一抛光步骤以除去氧化硅层的一部分直到氧化物层的剩余部分的厚度达到预定厚度。执行第二抛光步骤以去除氧化硅层的剩余部分的一部分，直到暴露氮化硅层。

9. 发明授权

US06251779B1 Method of forming a self-aligned silicide on a semiconductor wafer 有权
标题翻译：在半导体晶片上形成自对准硅化物的方法
公开(公告)号：US06251779B1
公开(公告)日：2001-06-26
申请号：US09584694
申请日：2000-06-01
申请人： Hsiao-Ling Lu , Li-Yeat Chen , Wen-Yi Hsieh
发明人： Hsiao-Ling Lu , Li-Yeat Chen , Wen-Yi Hsieh
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28518
摘要： This invention provides a method of forming a self-aligned silicide of a semiconductor wafer, the surface of the semiconductor wafer comprising at least one silicon device. A cobalt-containing metallic layer is formed on the semiconductor wafer which covers on the surface of the silicon device. A first thermal treatment process is performed to rapidly heat the semiconductor wafer up to 300˜500° C. for 10˜50 seconds and form Co2Si on the surface of the silicon device. A second thermal treatment process is performed to rapidly heat the semiconductor wafer up to 400˜680° C. for 20˜50 seconds and then cool down the semiconductor wafer afterwards so as to convert Co2Si into CoSi. An etching process is performed to remove the metallic layer. A third thermal treatment process is performed to rapidly heat the semiconductor wafer up to 700˜950° C. for 30˜60 seconds and then cool down the semiconductor wafer afterward so as to convert CoSi into the self-aligned silicide.
摘要翻译：本发明提供一种形成半导体晶片的自对准硅化物的方法，所述半导体晶片的表面包括至少一个硅器件。在覆盖硅器件表面的半导体晶片上形成含钴金属层。执行第一热处理工艺以将半导体晶片快速加热至300〜500℃持续10〜50秒，并在硅器件的表面上形成Co2Si。执行第二热处理工艺以将半导体晶片快速加热至400〜680℃，持续20〜50秒，然后冷却半导体晶片，从而将Co 2 Si转化为CoSi。进行蚀刻处理以去除金属层。执行第三热处理工艺以将半导体晶片快速加热至700〜950℃，持续30〜60秒，然后冷却半导体晶片，从而将CoSi转化为自对准硅化物。

10. 发明授权

US6140192A Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US6140192A
公开(公告)日：2000-10-31
申请号：US346554
申请日：1999-06-30
申请人： Michael W C Huang , Hsiao-Ling Lu , Tri-Rung Yew
发明人： Michael W C Huang , Hsiao-Ling Lu , Tri-Rung Yew
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/28061 , H01L21/28247 , H01L29/665
摘要： A method for fabricating a semiconductor device. A substrate having a gate is provided. An ion implantation process is performed to form lightly doped source/drain region in the substrate. A liner layer and an insulation layer are formed over a substrate in sequence. A portion of the insulation layer is removed by an anisotropic etching process. The insulation layer remaining on sidewalls of the gate is used as a spacer. A top of the spacer is substantially level with an upper surface of the liner layer. An ion implantation process is performed to form heavily doped source/drain region in the substrate. A portion of the spacer is removed by wet etching. As a result, a top surface of the spacer is lower than the upper surface of the gate. The method can increase the exposed surface of the gate and maintain sufficient width of the lightly doped source/drain region to prevent the hot carrier effect and the short channel effect.
摘要翻译：一种半导体器件的制造方法。提供具有栅极的基板。执行离子注入工艺以在衬底中形成轻掺杂的源极/漏极区域。依次在衬底上形成衬垫层和绝缘层。通过各向异性蚀刻工艺去除绝缘层的一部分。留在栅极侧壁上的绝缘层用作间隔物。间隔件的顶部与衬里层的上表面基本一致。执行离子注入工艺以在衬底中形成重掺杂的源极/漏极区域。通过湿蚀刻去除间隔物的一部分。结果，间隔件的顶表面比门的上表面低。该方法可以增加栅极的暴露表面，并保持轻掺杂源极/漏极区域的足够宽度，以防止热载流子效应和短沟道效应。

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