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1. 发明授权

US07544305B2 Chemical mechanical polishing process for forming shallow trench isolation structure 有权
标题翻译：用于形成浅沟槽隔离结构的化学机械抛光工艺
公开(公告)号：US07544305B2
公开(公告)日：2009-06-09
申请号：US11863665
申请日：2007-09-28
申请人： Chia-Jung Hsu , Art Yu , Hsiao-Ling Lu , Teng-Chun Tsai
发明人： Chia-Jung Hsu , Art Yu , Hsiao-Ling Lu , Teng-Chun Tsai
IPC分类号： B44C1/22
CPC分类号： H01L21/76229 , H01L21/31053
摘要： A shallow trench isolation (STI) multistage chemical mechanical polishing (CMP) method for forming a shallow trench isolation structure is provided. The substrate comprising a dense region and an isolation region, a silicon nitride layer formed over the substrate, a plurality of trenches formed in the silicon nitride layer and the substrate, an oxide layer formed over the substrate, filling the trenches, wherein a width of the trenches in the dense region is smaller than that in the isolation region. A first polishing step is performed to remove a portion of the silicon oxide layer until a thickness of the remaining portion of the oxide layer reaches a predetermined thickness. A second polishing step is performed to remove a portion of the remaining portion of the silicon oxide layer until the silicon nitride layer is exposed.
摘要翻译：提供了一种用于形成浅沟槽隔离结构的浅沟槽隔离（STI）多级化学机械抛光（CMP）方法。所述基板包括致密区域和隔离区域，在所述基板上形成的氮化硅层，形成在所述氮化硅层和所述基板中的多个沟槽，形成在所述基板上方的填充所述沟槽的氧化物层，密集区域中的沟槽小于隔离区域中的沟槽。执行第一抛光步骤以除去氧化硅层的一部分直到氧化物层的剩余部分的厚度达到预定厚度。执行第二抛光步骤以去除氧化硅层的剩余部分的一部分，直到暴露氮化硅层。

2. 发明申请

US20080029478A1 CHEMICAL MECHANICAL POLISHING PROCESS FOR FORMING SHALLOW TRENCH ISOLATION STRUCTURE 有权
标题翻译：化学机械抛光工艺形成浅层分离结构
公开(公告)号：US20080029478A1
公开(公告)日：2008-02-07
申请号：US11863665
申请日：2007-09-28
申请人： Chia-Jung Hsu , Art Yu , Hsiao-Ling Lu , Teng-Chun Tsai
发明人： Chia-Jung Hsu , Art Yu , Hsiao-Ling Lu , Teng-Chun Tsai
IPC分类号： B44C1/22
CPC分类号： H01L21/76229 , H01L21/31053
摘要： A shallow trench isolation (STI) multistage chemical mechanical polishing (CMP) method for forming a shallow trench isolation structure is provided. The substrate comprising a dense region and an isolation region, a silicon nitride layer formed over the substrate, a plurality of trenches formed in the silicon nitride layer and the substrate, an oxide layer formed over the substrate, filling the trenches, wherein a width of the trenches in the dense region is smaller than that in the isolation region. A first polishing step is performed to remove a portion of the silicon oxide layer until a thickness of the remaining portion of the oxide layer reaches a predetermined thickness. A second polishing step is performed to remove a portion of the remaining portion of the silicon oxide layer until the silicon nitride layer is exposed.
摘要翻译：提供了一种用于形成浅沟槽隔离结构的浅沟槽隔离（STI）多级化学机械抛光（CMP）方法。所述基板包括致密区域和隔离区域，在所述基板上形成的氮化硅层，形成在所述氮化硅层和所述基板中的多个沟槽，形成在所述基板上方的填充所述沟槽的氧化物层，密集区域中的沟槽小于隔离区域中的沟槽。执行第一抛光步骤以除去氧化硅层的一部分直到氧化物层的剩余部分的厚度达到预定厚度。执行第二抛光步骤以去除氧化硅层的剩余部分的一部分，直到暴露氮化硅层。

3. 发明授权

US11682728B2 Structure of high-voltage transistor and method for fabricating the same 有权
公开(公告)号：US11682728B2
公开(公告)日：2023-06-20
申请号：US17073038
申请日：2020-10-16
申请人： United Microelectronics Corp. , Chun-Ya Chiu , Chih-Kai Hsu , Chin-Hung Chen , Chia-Jung Hsu , Ssu-I Fu , Yu-Hsiang Lin
发明人： Chun-Ya Chiu , Chih-Kai Hsu , Chin-Hung Chen , Chia-Jung Hsu , Ssu-I Fu , Yu-Hsiang Lin
IPC分类号： H01L29/78 , H01L29/08 , H01L29/165 , H01L29/267 , H01L29/66 , H01L21/02
CPC分类号： H01L29/7848 , H01L21/02521 , H01L21/02532 , H01L29/0847 , H01L29/165 , H01L29/267 , H01L29/66636
摘要： The disclosure discloses a structure of high-voltage (HV) transistor which includes a substrate. An epitaxial doped structure with a first conductive type is formed in the substrate, wherein a top portion of the epitaxial doped structure includes a top undoped epitaxial layer. A gate structure is disposed on the substrate and at least overlapping with the top undoped epitaxial layer. A source/drain (S/D) region with a second conductive type is formed in the epitaxial doped structure at a side of the gate structure. The first conductive type is different from the second conductive type.

4. 发明申请

US20120284473A1 MEMORY STORAGE DEVICE AND MEMORY CONTROLLER AND ACCESS METHOD THEREOF 有权
标题翻译：存储器件和存储器控制器及其访问方法
公开(公告)号：US20120284473A1
公开(公告)日：2012-11-08
申请号：US13170203
申请日：2011-06-28
申请人： Chia-Jung Hsu , Shih-Hsien Hsu
发明人： Chia-Jung Hsu , Shih-Hsien Hsu
IPC分类号： G06F12/02 , G06F12/14
CPC分类号： G06F12/0246 , G06F12/1466 , G06F21/00 , G06F21/554 , G06F21/79 , G06F21/85 , G06F2212/7201 , G06F2221/2149 , G06F2221/2153
摘要： A memory storage device and a memory controller and an access method thereof are provided. The memory storage device includes a rewritable non-volatile memory chip having a plurality of physical blocks. The access method includes configuring a plurality of logical blocks to be mapped to a part of the physical blocks and dividing the logical blocks into at least a first partition and a second partition, wherein the first partition records an auto-execute file. The access method also includes determining whether a trigger signal is existent and sending a media ready message to a host system if the trigger signal is existent, so as to allow the host system to automatically run the auto-execute file and receive a first password. The access method further includes determining whether to provide the logical blocks in the second partition to the host system according to the first password received from the host system.
摘要翻译：提供了一种存储器存储装置和存储器控制器及其存取方法。存储器存储装置包括具有多个物理块的可重写非易失性存储器芯片。所述访问方法包括配置要映射到所述物理块的一部分的多个逻辑块，并且将所述逻辑块划分为至少第一分区和第二分区，其中所述第一分区记录自动执行文件。访问方法还包括确定触发信号是否存在并且如果触发信号存在则向主机系统发送媒体就绪消息，以便允许主机系统自动运行自动执行文件并接收第一密码。所述访问方法还包括根据从所述主机系统接收到的所述第一密码，确定是否向所述主机系统提供所述第二分区中的逻辑块。

5. 发明申请

US20110294287A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING DUAL FULLY-SILICIDED GATE 审中-公开
标题翻译：制造具有双重全硅酸盐的半导体器件的方法
公开(公告)号：US20110294287A1
公开(公告)日：2011-12-01
申请号：US13208772
申请日：2011-08-12
申请人： Chin-Hsiang Lin , Chia-Jung Hsu , Li-Wei Cheng , Hsien-Liang Meng , Ming-Te Wei , Che-Hua Hsu
发明人： Chin-Hsiang Lin , Chia-Jung Hsu , Li-Wei Cheng , Hsien-Liang Meng , Ming-Te Wei , Che-Hua Hsu
IPC分类号： H01L21/263
CPC分类号： H01L21/823835 , H01L21/28097 , H01L29/4975 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： A method of manufacturing the semiconductor device having a dual fully-silicided gate includes the following steps. A substrate having a first transistor and a second transistor formed thereon is provided, wherein the first transistor includes a first gate and a first source/drain and the second transistor includes a second gate and a second source/drain. The gate height of the first gate is different from that of the second gate. A first silicidation process is performed to respectively transform the first gate and the second gate into a first silicided gate and a second silicided gate simultaneously, wherein the material of the first silicided gate is different from that of the second silicided gate.
摘要翻译：制造具有双全硅化物栅的半导体器件的方法包括以下步骤。提供了具有形成在其上的第一晶体管和第二晶体管的衬底，其中所述第一晶体管包括第一栅极和第一源极/漏极，所述第二晶体管包括第二栅极和第二源极/漏极。第一栅极的栅极高度与第二栅极的栅极高度不同。执行第一硅化处理以分别将第一栅极和第二栅极转换成第一硅化栅极和第二硅化物栅极，其中第一硅化栅极的材料与第二硅化物栅极的材料不同。

6. 发明授权

US07636018B2 Phase locked loop with phase shifted input 有权
标题翻译：带相移输入的锁相环
公开(公告)号：US07636018B2
公开(公告)日：2009-12-22
申请号：US11686092
申请日：2007-03-14
申请人： Jen-Chung Chang , Chia-Jung Hsu , Shey-Shi Lu , Yu-Che Yang , Tsung-Chien Wu , Tzu-Chao Lin
发明人： Jen-Chung Chang , Chia-Jung Hsu , Shey-Shi Lu , Yu-Che Yang , Tsung-Chien Wu , Tzu-Chao Lin
IPC分类号： H03L7/00
CPC分类号： H03L7/1976 , H03L7/081 , H03L7/087
摘要： In a phase locked loop (PLL), phase shifters shift a phase of an input signal. Based on the phases of the input signal, the shifted signals, and a frequency division output signal, phase frequency detectors (PFDs) generate phase difference signals. In response to the phase difference signals, charge pumps (CPs) control output voltages thereof. Based on the output voltages of the CPs, a voltage controlled oscillator (VCO) outputs an output signal. A frequency divider divides the frequency of the output signal from the VCO to generate the frequency division output signal. A circulator outputs the frequency division output signal to one of the PFDs at a proper timing. A modulator reduces quantization errors of the frequency divider.
摘要翻译：在锁相环（PLL）中，移相器移位输入信号的相位。基于输入信号的相位，移位的信号和分频输出信号，相位频率检测器（PFD）产生相位差信号。响应于相位差信号，电荷泵（CP）控制其输出电压。基于CP的输出电压，压控振荡器（VCO）输出输出信号。分频器分频来自VCO的输出信号的频率，以产生分频输出信号。循环器在正确的时机将分频输出信号输出到一个PFD。调制器减少了分频器的量化误差。

7. 发明授权

US09514040B2 Memory storage device and memory controller and access method thereof 有权
标题翻译：存储器和存储器控制器及其访问方法
公开(公告)号：US09514040B2
公开(公告)日：2016-12-06
申请号：US13170203
申请日：2011-06-28
申请人： Chia-Jung Hsu , Shih-Hsien Hsu
发明人： Chia-Jung Hsu , Shih-Hsien Hsu
IPC分类号： G06F12/02 , G06F12/14 , G06F21/00 , G06F21/55 , G06F21/79 , G06F21/85
CPC分类号： G06F12/0246 , G06F12/1466 , G06F21/00 , G06F21/554 , G06F21/79 , G06F21/85 , G06F2212/7201 , G06F2221/2149 , G06F2221/2153
摘要： A memory storage device and a memory controller and an access method thereof are provided. The memory storage device includes a rewritable non-volatile memory chip having a plurality of physical blocks. The access method includes configuring a plurality of logical blocks to be mapped to a part of the physical blocks and dividing the logical blocks into at least a first partition and a second partition, wherein the first partition records an auto-execute file. The access method also includes determining whether a trigger signal is existent and sending a media ready message to a host system if the trigger signal is existent, so as to allow the host system to automatically run the auto-execute file and receive a first password. The access method further includes determining whether to provide the logical blocks in the second partition to the host system according to the first password received from the host system.
摘要翻译：提供了一种存储器存储装置和存储器控制器及其存取方法。存储器存储装置包括具有多个物理块的可重写非易失性存储器芯片。所述访问方法包括配置要映射到所述物理块的一部分的多个逻辑块，并且将所述逻辑块划分为至少第一分区和第二分区，其中所述第一分区记录自动执行文件。访问方法还包括确定触发信号是否存在并且如果触发信号存在则向主机系统发送媒体就绪消息，以便允许主机系统自动运行自动执行文件并接收第一密码。所述访问方法还包括根据从所述主机系统接收到的所述第一密码，确定是否向所述主机系统提供所述第二分区中的逻辑块。

8. 发明申请

US20130151858A1 STORAGE DEVICE PROTECTION SYSTEM AND METHOD FOR LOCKING AND UNLOCKING STORAGE DEVICE 有权
标题翻译：存储设备保护系统和锁定和解锁存储设备的方法
公开(公告)号：US20130151858A1
公开(公告)日：2013-06-13
申请号：US13366373
申请日：2012-02-06
申请人： Ching-Hsien Wang , Chia-Jung Hsu
发明人： Ching-Hsien Wang , Chia-Jung Hsu
IPC分类号： H04L9/28
CPC分类号： G06F21/34 , G06F12/1466 , G06F21/602 , G06F21/83 , H04L9/0897
摘要： A storage device protection system including a protection control unit, a detection unit, an account/password input unit, an ID acquiring unit, and an encryption unit is provided. The detection unit determines whether a storage device and a key storage device are both coupled to a host. The account/password input unit receives an administrator ID and an administrator password. The ID acquiring unit obtains IDs of the storage device and the key storage device. The encryption unit encrypts the administrator ID, the administrator password, and the IDs of the storage device and the key storage device into encryption data. The protection control unit stores the encryption data into the key storage device and sets an access mode of the storage device as a protection status according to the administrator ID and the administrator password. Thereby, the storage device can be effectively unlocked by using the key storage device.
摘要翻译：提供了包括保护控制单元，检测单元，帐户/密码输入单元，ID获取单元和加密单元的存储设备保护系统。检测单元确定存储设备和密钥存储设备是否都耦合到主机。帐号/密码输入单元接收管理员ID和管理员密码。 ID获取单元获得存储设备和密钥存储设备的ID。加密单元将管理员ID，管理员密码以及存储设备和密钥存储设备的ID加密成加密数据。保护控制单元将加密数据存储到密钥存储装置中，并根据管理员ID和管理员密码将存储装置的访问模式设置为保护状态。由此，可以通过使用密钥存储装置来有效地解锁存储装置。

9. 发明申请

US20080153241A1 METHOD FOR FORMING FULLY SILICIDED GATES 审中-公开
标题翻译：形成全硅胶门的方法
公开(公告)号：US20080153241A1
公开(公告)日：2008-06-26
申请号：US11616029
申请日：2006-12-26
申请人： Chia-Jung Hsu , Chin-Hsiang Lin , Li-Wei Cheng
发明人： Chia-Jung Hsu , Chin-Hsiang Lin , Li-Wei Cheng
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L21/28097 , H01L21/7624 , H01L21/823835 , H01L29/66507 , H01L29/66545
摘要： A method for forming a fully silicided gate is disclosed. A gate structure of a transistor device is provided on a substrate. A mask layer is spin-on coated over the substrate to cover the gate structure and source/drain regions of the transistor device. The mask layer is etched back to expose a silicon layer of the gate structure. The silicon layer of the gate structure is then fully silicided. The mask layer is then removed from the substrate to expose the source/drain regions. The source/drain regions are finally silicided.
摘要翻译：公开了一种形成全硅化物栅的方法。晶体管器件的栅极结构设置在衬底上。将掩模层旋涂在衬底上以覆盖晶体管器件的栅极结构和源极/漏极区域。掩模层被回蚀以露出栅极结构的硅层。然后，栅极结构的硅层被完全硅化。然后从衬底去除掩模层以暴露源极/漏极区域。源极/漏极区域最终被硅化。

10. 发明申请

US20060026158A1 Sorting method utilizing memory space efficiently, machine-readable medium thereof, and related apparatus 审中-公开
标题翻译：利用存储空间有效地分类方法，其机器可读介质及相关装置
公开(公告)号：US20060026158A1
公开(公告)日：2006-02-02
申请号：US11160920
申请日：2005-07-15
申请人： Chia-Jung Hsu
发明人： Chia-Jung Hsu
IPC分类号： G06F7/00 , G06F12/00
CPC分类号： B60S1/40 , B60S1/42 , G06F7/22
摘要： The present invention discloses a sorting method using a memory as an auxiliary tool to sort a plurality of items stored in a storage device. The method includes the following steps: (a) retrieving full information of an item to be sorted from the storage device; (b) comparing only partial information of the item to be sorted with partial information of at least one already sorted item stored in the memory to determine an order of the item to be sorted and the already sorted items; and (c) storing partial information of the already sorted items and partial information of the item to be sorted into the memory according to the determined order.
摘要翻译：本发明公开了一种使用存储器作为辅助工具对存储在存储装置中的多个物品进行分类的排序方法。该方法包括以下步骤：（a）从存储设备检索待分类物品的完整信息; （b）仅将要分类的项目的部分信息与存储在存储器中的至少一个已经排序的项目的部分信息进行比较，以确定要排序的项目的顺序和已排序的项目; 以及（c）根据确定的顺序将已经排序的项目的部分信息和要分类的项目的部分信息存储到存储器中。

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