专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06661097B1 Ti liner for copper interconnect with low-k dielectric 失效
标题翻译：用于低k电介质的铜互连的Ti衬垫
公开(公告)号：US06661097B1
公开(公告)日：2003-12-09
申请号：US10287155
申请日：2002-11-01
申请人： Larry Clevenger , Stanley J. Klepeis , Hsiao-Ling Lu , Jeffrey R. Marino , Andrew Herbert Simon , Yun-Yu Wang , Kwong Hon Wong , Chih-Chao Yang
发明人： Larry Clevenger , Stanley J. Klepeis , Hsiao-Ling Lu , Jeffrey R. Marino , Andrew Herbert Simon , Yun-Yu Wang , Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/76846 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In copper backend integrated circuit technology, advanced technology using low-k organic-based interlayer dielectrics have a problem of carbon contamination that dos not occur in circuits using oxide as dielectric. A composite liner layer for the copper lines uses Ti as the bottom layer, which has the property of gettering carbon and other contaminants. The known problem with Ti of reacting with copper to form a high resistivity compound is avoided by adding a layer of TiN, which isolates the Ti and the copper.
摘要翻译：在铜后端集成电路技术中，使用低k有机基层间电介质的先进技术具有碳污染的问题，在使用氧化物作为电介质的电路中不会发生这种问题。用于铜线的复合衬里层使用Ti作为底层，其具有吸除碳和其它污染物的性质。通过添加一层分离Ti和铜的TiN层，避免了与铜反应形成高电阻率化合物的Ti的已知问题。

2. 发明授权

US07214608B2 Interlevel dielectric layer and metal layer sealing 有权
标题翻译：层间电介质层和金属层密封
公开(公告)号：US07214608B2
公开(公告)日：2007-05-08
申请号：US10710706
申请日：2004-07-29
申请人： Matthew S. Angyal , Peter E. Biolsi , Lawrence A. Clevenger , Habib Hichri , Bernd E. Kastenmeier , Michael W. Lane , Jeffrey R. Marino , Vincent J. McGahay , Theodorus E. Standaert
发明人： Matthew S. Angyal , Peter E. Biolsi , Lawrence A. Clevenger , Habib Hichri , Bernd E. Kastenmeier , Michael W. Lane , Jeffrey R. Marino , Vincent J. McGahay , Theodorus E. Standaert
IPC分类号： H01L21/4763
CPC分类号： H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L21/76838 , H01L21/76844
摘要： Methods for sealing an organic ILD layer and a metal layer after an etching step. The method includes etching through an ILD layer and leaving a remaining portion of an underlying metal layer cap, maintaining the device in an inert gas, and depositing at least a portion of a liner into the opening to seal the ILD layer and the metal layer. Subsequent processing may include formation of a via by etching through the portion of the liner and the remaining portion of the cap layer, and depositing a metal.
摘要翻译：在蚀刻步骤之后密封有机ILD层和金属层的方法。该方法包括蚀刻穿过ILD层并留下下面的金属层帽的剩余部分，将该装置保持在惰性气体中，并将衬垫的至少一部分沉积到开口中以密封ILD层和金属层。随后的处理可以包括通过蚀刻穿过衬套的一部分和盖层的剩余部分以及沉积金属来形成通孔。

3. 发明授权

US5633047A Electronic devices having metallurgies containing copper-semiconductor compounds 失效
标题翻译：具有包含铜半导体化合物的冶金的电子器件
公开(公告)号：US5633047A
公开(公告)日：1997-05-27
申请号：US449196
申请日：1995-05-24
申请人： Michael J. Brady , Curtis E. Farrell , Sung K. Kang , Jeffrey R. Marino , Donald J. Mikalsen , Paul A. Moskowitz , Eugene J. O'Sullivan , Terrence R. O'Toole , Sampath Purushothaman , Sheldon C. Rieley , George F. Walker
发明人： Michael J. Brady , Curtis E. Farrell , Sung K. Kang , Jeffrey R. Marino , Donald J. Mikalsen , Paul A. Moskowitz , Eugene J. O'Sullivan , Terrence R. O'Toole , Sampath Purushothaman , Sheldon C. Rieley , George F. Walker
IPC分类号： C23C18/50 , C25D3/54 , H01L23/495 , H01L23/532 , B05D1/18
CPC分类号： H01L24/12 , C23C18/50 , C25D3/54 , H01L23/4951 , H01L23/53271 , H01L24/05 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/05644 , H01L2224/05647 , H01L2224/13099 , H01L2224/32014 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/4847 , H01L2224/48644 , H01L2224/48647 , H01L2224/48747 , H01L2224/48844 , H01L2224/48847 , H01L2224/73215 , H01L2224/85201 , H01L2224/85205 , H01L2224/85214 , H01L24/45 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/12032 , H01L2924/12042 , H01L2924/14 , H01L2924/15747 , H01L2924/15787 , H01L2924/181
摘要： Silicon and germanium containing materials are used at surface of conductors in electronic devices. Solder can be fluxlessly bonded and wires can be wire bonded to these surfaces. These material are used as a surface coating for lead frames for packaging integrated circuit chips. These materials can be decal transferred onto conductor surfaces or electrolessly or electrolytically disposed thereon.
摘要翻译：在电子设备中的导体的表面使用含锗和锗的材料。焊料可无焊接，电线可以与这些表面引线接合。这些材料用作用于封装集成电路芯片的引线框架的表面涂层。这些材料可以贴花地转移到导体表面上，或者无电解或电解地放置在其上。

4. 发明授权

US07033648B1 Means of seeding and metallizing polyimide 失效
标题翻译：种植和金属化聚酰亚胺的方法
公开(公告)号：US07033648B1
公开(公告)日：2006-04-25
申请号：US08781926
申请日：1996-12-30
申请人： Fuad E. Doany , Jeffrey R. Marino , Carlos J. Sambucetti , Ravi F. Saraf
发明人： Fuad E. Doany , Jeffrey R. Marino , Carlos J. Sambucetti , Ravi F. Saraf
IPC分类号： H05H1/00 , B05D3/00 , B05D5/12
CPC分类号： C23C18/22 , C23C18/1605 , C23C18/1641 , C23C18/1692 , C23C18/2006 , C23C18/208 , C23C18/30 , C23C18/31 , H05K1/0346 , H05K3/0032 , H05K3/184 , H05K3/381 , H05K2203/0793 , H05K2203/083 , H05K2203/095
摘要： A method to selectively metallize polyimide with an all-electroless process.
摘要翻译：选择性地使全化学镀金属化聚酰亚胺的方法。

5. 发明授权

US06202367B1 Raised border system 有权
标题翻译：凸起的边界系统
公开(公告)号：US06202367B1
公开(公告)日：2001-03-20
申请号：US09231099
申请日：1999-01-14
申请人： Jeffrey R. Marino , Anthony G. Topping
发明人： Jeffrey R. Marino , Anthony G. Topping
IPC分类号： E04B276
CPC分类号： A01G9/28
摘要： A support bracket and stake are provided which can be used for edging gardens and lawns or for the formation of retaining walls. Used together, the bracket and stake provide a means to support and anchor lengths of lumber to the ground to create a variety of edging systems. In particular, the stakes provide a means to attach the system securely to the ground surface, while the support bracket has a beam receiving portion to support a variety of different types of lumber frequently used in edging. A mounting column on the support bracket provides a means to secure the support bracket to the stakes such that the support bracket may freely rotate 360° perpendicular to the vertical axis of the stake. The stakes may be vertically engaged one upon and inside the other to provide a raised border system of various height. Where it is desired to vertically engage the stakes, more than one bracket may be secured to the vertical stakes, one bracket on top of the other, so as to support and anchor lengths of lumber, one on top of the other, to form a wall of any desired height.
摘要翻译：提供支撑托架和桩，可用于花园和草坪的边缘或用于形成挡土墙。支架和支架一起使用，可以将木材的长度支撑和锚定到地面上，以创建各种边缘系统。特别地，这些桩提供了将系统牢固地附接到地面的手段，而支撑托架具有支撑多个经常用于边缘的不同类型的木材的梁接收部分。支撑托架上的安装柱提供了将支撑托架固定到桩柱上的装置，使得支撑托架可以垂直于桩的垂直轴线自由旋转360°。桩可以垂直地接合在另一个上和内部，以提供各种高度的凸起边界系统。在需要垂直接合桩的情况下，可以将多于一个的支架固定到垂直桩，一个支架在另一个的顶部上，以便支撑和锚固长度的木材，一个在另一个之上，以形成任何所需高度的墙壁。

6. 发明授权

US6010918A Gate electrode structure for field emission devices and method of making 失效
标题翻译：场发射器件的栅电极结构及其制造方法
公开(公告)号：US6010918A
公开(公告)日：2000-01-04
申请号：US21317
申请日：1998-02-10
申请人： Jeffrey R. Marino , Joseph K. Ho
发明人： Jeffrey R. Marino , Joseph K. Ho
IPC分类号： H01J3/02 , H01J9/02 , H01L21/00
CPC分类号： H01J9/025 , H01J3/022
摘要： Field emission devices may include emitter wells formed in a body of dielectric material. A gate conductor may be provided along the upper surface of the dielectric material. A gate hole may be provided in the gate conductor directly above each of the emitter wells. A method for forming the gate holes and emitter wells is disclosed. The method includes the steps of providing a first gate conductor layer on a dielectric layer. A pattern of second gate conductor material may be formed over the first gate conductor layer, said pattern defining gate holes in the second gate conductor material. The gate holes may then be completed and emitter wells formed by etching through the first gate conductor layer and into the dielectric layer using an etch that selectively etches the first gate conductor layer and the dielectric layer, and does not etch substantially the second gate conductor material.
摘要翻译：场致发射器件可以包括在电介质材料体中形成的发射极阱。可以沿着电介质材料的上表面设置栅极导体。可以在每个发射极阱的正上方的栅极导体中设置栅极孔。公开了一种用于形成栅极孔和发射极阱的方法。该方法包括在电介质层上提供第一栅极导体层的步骤。可以在第一栅极导体层之上形成第二栅极导体材料的图案，所述图案限定第二栅极导体材料中的栅极孔。然后可以完成栅极孔，并且通过蚀刻通过第一栅极导体层并进入电介质层而形成的发射极阱，其使用选择性蚀刻第一栅极导体层和电介质层的蚀刻，并且基本不蚀刻第二栅极导体材料。

7. 发明授权

US06831363B2 Structure and method for reducing thermo-mechanical stress in stacked vias 有权
标题翻译：用于降低堆叠过孔中热机械应力的结构和方法
公开(公告)号：US06831363B2
公开(公告)日：2004-12-14
申请号：US10319032
申请日：2002-12-12
申请人： Timothy J. Dalton , Sanjit K. Das , Brett H. Engel , Brian W. Herbst , Habib Hichri , Bernd E. Kastenmeier , Kelly Malone , Jeffrey R. Marino , Arthur Martin , Vincent J. McGahay , Ian D. Melville , Chandrasekhar Narayan , Kevin S. Petrarca , Richard P. Volant
发明人： Timothy J. Dalton , Sanjit K. Das , Brett H. Engel , Brian W. Herbst , Habib Hichri , Bernd E. Kastenmeier , Kelly Malone , Jeffrey R. Marino , Arthur Martin , Vincent J. McGahay , Ian D. Melville , Chandrasekhar Narayan , Kevin S. Petrarca , Richard P. Volant
IPC分类号： H01L2348
CPC分类号： H01L21/76808 , H01L21/76801 , H01L21/76831 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.
摘要翻译：用于半导体器件的互连结构包括在较低金属化水平上形成的有机低介电常数（低k）电介质层。形成的通孔在低k电介质层内，通孔连接在下金属化层形成的下金属化线与上金属化层形成的上金属化线。通孔被选自具有热膨胀系数（CTE）的材料的结构轴环包围，以便在低k电介质层的热膨胀之后保护通孔不受剪切力的影响。

8. 发明授权

US06311428B1 Garden trellis wall system 失效
标题翻译：花园格子墙系统
公开(公告)号：US06311428B1
公开(公告)日：2001-11-06
申请号：US09229417
申请日：1999-01-12
申请人： Jeffrey R. Marino , Anthony G. Topping
发明人： Jeffrey R. Marino , Anthony G. Topping
IPC分类号： A01G1706
CPC分类号： A01G9/12
摘要： The invention provides a simple device for providing vertical support of vegetable plants, thereby eliminating the conventional problems routinely associated with home gardening. In particular, the device provides a maintenance free, vertical support frame assembly of adjustable height to which is attached a mesh netting and supporting stakes, forming an extendable garden trellis. Growing plants may be attached to the gardening trellis, thereby allowing maximum upward growth of the plants while also elevating the plants.
摘要翻译：本发明提供了一种用于提供蔬菜植物的垂直支撑的简单装置，从而消除了与家庭园艺常规相关的常规问题。特别地，该装置提供了一种免维护的可调高度的垂直支撑框架组件，其附接有网状网和支撑桩，形成可扩展的花园网格。生长的植物可以附着在园艺格子上，从而允许植物的最大向上生长，同时也提高植物。

9. 外观设计

USD428798S Trellis bracket 失效
公开(公告)号：USD428798S
公开(公告)日：2000-08-01
申请号：US103738
申请日：1999-04-22
申请人： Jeffrey R. Marino , Anthony G. Topping
设计人： Jeffrey R. Marino , Anthony G. Topping

10. 外观设计

USD423626S Tee pee leg connector 失效
公开(公告)号：USD423626S
公开(公告)日：2000-04-25
申请号：US105966
申请日：1999-06-03
申请人： Jeffrey R. Marino , Anthony G. Topping
设计人： Jeffrey R. Marino , Anthony G. Topping

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式