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1. 发明申请

WO2012087073A3 PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：印刷电路板及其制造方法
公开(公告)号：WO2012087073A3
公开(公告)日：2012-09-27
申请号：PCT/KR2011010058
申请日：2011-12-23
申请人： LG INNOTEK CO LTD , RYU SUNG WUK , SHIM SEONG BO , SHIN SEUNG YUL
发明人： RYU SUNG WUK , SHIM SEONG BO , SHIN SEUNG YUL
IPC分类号： H05K3/40 , H05K3/34
CPC分类号： H05K1/02 , H05K3/3436 , H05K3/3452 , H05K3/40 , H05K3/4007 , H05K2201/0367
摘要： A printed circuit board, according to one embodiment of the present invention, comprises: an insulation layer; a pad, which is formed on the insulation layer, and is exposed through an open portion of a solder resist; and a bump, which is from the top of the pad so as to burry the open portion of the solder resist and has a width that is smaller than the width of the open portion of th solder resist.
摘要翻译：根据本发明的一个实施例的印刷电路板包括：绝缘层; 衬垫，其形成在绝缘层上，并且通过阻焊剂的开口部分露出; 以及从焊盘的顶部起凸起阻焊剂的开口部分的凸块，其宽度小于阻焊剂的开口部分的宽度。

2. 发明申请

WO2012087072A3 PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：印刷电路板及其制造方法
公开(公告)号：WO2012087072A3
公开(公告)日：2012-10-11
申请号：PCT/KR2011010057
申请日：2011-12-23
申请人： LG INNOTEK CO LTD , RYU SUNG WUK , SHIM SEONG BO , SHIN SEUNG YUL
发明人： RYU SUNG WUK , SHIM SEONG BO , SHIN SEUNG YUL
IPC分类号： H05K3/40 , H05K3/28
CPC分类号： H05K1/09 , H05K3/28 , H05K3/3473 , H05K3/4007 , H05K13/00 , H05K2201/0367 , H05K2203/054 , H05K2203/0577
摘要： A printed circuit board, according to one embodiment, comprises: an insulation layer; at least one circuit pattern or pad which is formed on the insulation layer; a solder resist having an open portion for exposing the upper surface of the pad and is formed on the insulation layer; and a bump which is formed on the pad that is exposed through the open portion of the solder resist and has lower surface area that is smaller than the upper surface area of the pad.
摘要翻译：根据一个实施例的印刷电路板包括：绝缘层; 至少一个形成在绝缘层上的电路图案或焊盘; 具有用于暴露所述焊盘的上表面的开口部分并形成在所述绝缘层上的阻焊剂; 以及形成在所述焊盘上的凸块，所述凸块通过所述阻焊剂的所述开口部分而暴露，并具有比所述焊盘的上表面区域小的下表面区域。

3. 发明申请

WO2010126302A3 SEMICONDUCTOR PACKAGE WITH NSMD TYPE SOLDER MASK AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：具有NSMD型焊接掩模的半导体封装及其制造方法
公开(公告)号：WO2010126302A3
公开(公告)日：2010-12-29
申请号：PCT/KR2010002683
申请日：2010-04-28
申请人： LG INNOTEK CO LTD , SHIM SEONG BO , LEE YOUNG JAE , RYU SUNG WUK
发明人： SHIM SEONG BO , LEE YOUNG JAE , RYU SUNG WUK
IPC分类号： H01L21/60 , H01L23/12 , H01L23/48
CPC分类号： H01L24/16 , H01L21/4853 , H01L23/49816 , H01L24/13 , H01L24/81 , H01L24/94 , H01L2224/05001 , H01L2224/05022 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05572 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/13099 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16225 , H01L2224/81193 , H01L2224/812 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12044 , H01L2924/00014 , H01L2924/00
摘要： A method for manufacturing semiconductor package comprising: a first step of forming a solder mask formed with an opening on an insulation substrate; and a second step of firmly adhering a solder paste and a metal ball on the solder mask to mount chips thereon, such that a circuit density of a substrate can be greatly increased by directly printing a solder paste on a solder mask following formation of an opening of the solder mask on a trace and can be applied to a fine bump pitch of less than 100µm due to non-existence of bump bridges.
摘要翻译：一种半导体封装的制造方法，包括：在绝缘基板上形成形成有开口的焊料掩模的第一工序; 以及将焊膏和金属球牢固地粘合在焊料掩模上以在其上安装芯片的第二步骤，使得可以通过在形成开口之后直接将焊膏印刷在焊料掩模上来大大增加基板的电路密度的焊锡掩模，并且由于不存在凸块桥，可以应用于小于100μm的微小凸起间距。

4. 发明申请

WO2010074510A3 STRUCTURE FOR MULTI-ROW LEADFRAME AND SEMICONDUCTOR PACKAGE THEREOF AND MANUFACTURE METHOD THEREOF 审中-公开
标题翻译：多引线框架结构及其半导体封装及其制造方法
公开(公告)号：WO2010074510A3
公开(公告)日：2010-09-10
申请号：PCT/KR2009007724
申请日：2009-12-23
申请人： LG INNOTEK CO LTD , CHUN HYUN A , CHOI JAE BONG , LEE SUNG WON , RYU SUNG WUK , LEE HYUK SOO , EOM SAI RAN
发明人： CHUN HYUN A , CHOI JAE BONG , LEE SUNG WON , RYU SUNG WUK , LEE HYUK SOO , EOM SAI RAN
IPC分类号： H01L23/495
CPC分类号： H01L21/4832 , H01L23/49582 , H01L24/29 , H01L24/48 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/92247 , H01L2924/00014 , H01L2924/01029 , H01L2924/01046 , H01L2924/01067 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/01322 , H01L2924/181 , H01L2924/00 , H01L2924/01026 , H01L2924/01028 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask.
摘要翻译：本发明涉及一种用于半导体封装的多列引线框，其特征在于：在引线框架材料上形成电镀图案（第一步骤）; 在电镀图案上形成保护图案（第二工序）; 并且通过使用保护图案作为掩模形成纳米图案（第三步骤），由此在电镀图案的上表面上形成保护图案，以通过防止由蚀刻溶液导致的镀层损伤而提高产品的可靠性引线框架的图案形成，从而解决了使用镀层作为蚀刻掩模的问题。

5. 发明申请

WO2010036051A2 STRUCTURE AND MANUFACTURE METHOD FOR MULTI-ROW LEAD FRAME AND SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：用于多引线框架和半导体封装的结构和制造方法
公开(公告)号：WO2010036051A2
公开(公告)日：2010-04-01
申请号：PCT/KR2009005481
申请日：2009-09-25
申请人： LG INNOTEK CO LTD , KIM JI YUN , SHIN HYUN SUB , LEE SUNG WON , LEE HYUNG EUI , SEO YEONG UK , RYU SUNG WUK , LEE HYUK SOO
发明人： KIM JI YUN , SHIN HYUN SUB , LEE SUNG WON , LEE HYUNG EUI , SEO YEONG UK , RYU SUNG WUK , LEE HYUK SOO
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L21/4832 , H01L23/49503 , H01L23/49513 , H01L23/49541 , H01L23/49568 , H01L23/49582 , H01L24/48 , H01L24/73 , H01L24/95 , H01L2224/32057 , H01L2224/32245 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/484 , H01L2224/73265 , H01L2224/83385 , H01L2224/85001 , H01L2224/85411 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/85457 , H01L2224/85464 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15153 , H01L2924/15165 , H01L2924/157 , H01L2924/181 , H01L2924/19043 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： The present invention relates to structure and manufacture method for multi-row lead frame and semiconductor package, the method characterized by forming a pad portion on a metal material (first step); performing a surface plating process or organic material coating following the first pattern formation (second step); forming a second pattern on the metal material (third step); and packaging a semiconductor chip following the second pattern formation (fourth step), whereby an under-cut phenomenon is minimized by applying a gradual etching.
摘要翻译：本发明涉及多排引线框架和半导体封装的结构和制造方法，其特征在于在金属材料上形成焊盘部分（第一步骤）; 在第一图案形成之后执行表面电镀工艺或有机材料涂层（第二步骤）; 在金属材料上形成第二图案（第三步骤）; 并且在第二图案形成之后封装半导体芯片（第四步骤），由此通过施加渐进蚀刻来最小化底切现象。

6. 发明专利

JP2015057827A 半導体パッケージ审中-公开
标题翻译：半导体封装
公开(公告)号：JP2015057827A
公开(公告)日：2015-03-26
申请号：JP2014187826
申请日：2014-09-16
申请人：エルジーイノテックカンパニーリミテッド , Lg Innotek Co Ltd , エルジーイノテックカンパニーリミテッド
发明人： KIM DONG SUN , RYU SUNG WUK , LEE JI HAENG
IPC分类号： H01L25/10 , H01L25/11 , H01L25/18
CPC分类号： H01L24/12 , H01L23/49822 , H01L23/5389 , H01L25/105 , H01L2224/0401 , H01L2224/04042 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06568 , H01L2225/1023 , H01L2225/1058 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/12042 , H01L2924/15 , H01L2924/15311 , H01L2924/15331 , H01L2924/35 , H01L2924/384 , H01L2924/00 , H01L2924/00012
摘要：【課題】上下のパッケージ間の間隔を広げ、実装されるチップの数を増加させることにより高密度に実装でき、かつ上部パッケージと下部パッケージ間の接合信頼性が優れた半導体パッケージを提供する。【解決手段】素子370が実装された下部パッケージ300と、下部パッケージ300に接続され、少なくとも一つの金属材料部を含む金属ポスト500と、素子430が実装されてはんだボール501を介して金属ポスト500に接続される上部パッケージ400と、を含む。【選択図】図1
摘要翻译：要解决的问题：提供通过增加上部封装和下部封装之间的距离来实现的具有高密度的半导体封装，以增加安装的芯片的数量，以及上部封装和下部封装之间的优异的焊接可靠性。解决方案：A 半导体封装包括：其上安装有元件370的下封装300; 金属柱500连接到下部封装300并且包括至少一个金属材料部分; 以及其上安装有元件430并且经由焊球501连接到金属柱500的上部封装400。

7. 发明公开

KR20200139370A 인쇄회로기판 및 인쇄회로기판 스트립 审中-公开
公开(公告)号：KR20200139370A
公开(公告)日：2020-12-14
申请号：KR20190065796
申请日：2019-06-04
申请人： LG INNOTEK CO LTD
发明人： RYU SUNG WUK , KIM JAE HWA , SHIN SEUNG YUL
IPC分类号： H05K1/02 , H05K3/46
摘要： 실시예에따른인쇄회로기판은제1 기판층; 상기제1 기판층위에배치된제2 기판층; 상기제1 기판층아래에배치된제3 기판층; 상기제2 기판층위에배치된제1 솔더레지스트층; 및상기제3 기판층아래에배치된제2 솔더레지스트층을포함하고, 상기제2 기판층이가지는열팽창계수는, 상기제3 기판층이가지는열팽창계수와다르며, 상기제1 솔더레지스트층의두께는, 상기제2 솔더레지스트층의두께와다르다.

8. 发明公开

KR20120072684A The printed circuit board and the method for manufacturing the same 有权
标题翻译：印刷电路板及其制造方法
公开(公告)号：KR20120072684A
公开(公告)日：2012-07-04
申请号：KR20100134546
申请日：2010-12-24
申请人： LG INNOTEK CO LTD
发明人： SHIM SEONG BO , RYU SUNG WUK
IPC分类号： H05K3/28 , H05K3/40
摘要： PURPOSE: A method for manufacturing a printed circuit board is provided to protect the surface of a first protective layer and effectively remove the residue on the first protective layer by inserting a second protective layer to the top of the first protective layer when forming bumps. CONSTITUTION: A pad(103) is connected to a circuit pattern formed on an insulating plate(101), which is made of a thermosetting or thermoplastic polymer substrate, a ceramic substrate, or an organic-inorganic composite substrate, by patterning a copper film formed on the insulating plate. Bumps(109) are formed on the pad. A plating seed layer(108) is formed on the bumps. A first protective layer(104) covers the front side of the circuit pattern and a part of the bumps.
摘要翻译：目的：提供一种制造印刷电路板的方法，用于通过在形成凸块时将第二保护层插入第一保护层的顶部来保护第一保护层的表面并有效地去除第一保护层上的残留物。构成：通过将铜膜图案化，将衬垫（103）连接到形成在由热固性或热塑性聚合物衬底，陶瓷衬底或有机 - 无机复合衬底制成的绝缘板（101）上的电路图案形成在绝缘板上。撞击板（109）形成在垫上。在凸块上形成电镀种子层（108）。第一保护层（104）覆盖电路图案的前侧和凸块的一部分。

9. 发明公开

KR20120012347A The printed circuit board and the method for manufacturing the same 有权
标题翻译：印刷电路板及其制造方法
公开(公告)号：KR20120012347A
公开(公告)日：2012-02-09
申请号：KR20100074437
申请日：2010-07-30
申请人： LG INNOTEK CO LTD
发明人： SHIM SEONG BO , RYU SUNG WUK , LEE YOUNG JAE
IPC分类号： H05K3/34 , H05K1/05
摘要： PURPOSE: A printed circuit board and a manufacturing method thereof are provided to arrange a copper connection part on the lower part of solder, thereby preventing malfunction of a bridge in a fine pattern formation process. CONSTITUTION: A printed circuit board(100) comprises an insulating plate(110), a pad(120) connected to a circuit pattern arranged on the insulating plate, and a solder resist(130) covering the circuit pattern. The solder resist protects the surface of the insulating plate. A metal layer(140) is arranged on the upper surface of the exposed pad. A solder connection part(150) is arranged on the metal layer. The metal layer is used as a seed layer for arranging the solder connection part. Solder(160) is formed on the solder connection part.
摘要翻译：目的：提供印刷电路板及其制造方法以在焊料的下部布置铜连接部，从而防止在精细图案形成工艺中桥的故障。构成：印刷电路板（100）包括绝缘板（110），连接到布置在绝缘板上的电路图案的焊盘（120）和覆盖电路图案的阻焊剂（130）。阻焊剂保护绝缘板的表面。金属层（140）布置在暴露的焊盘的上表面上。焊接连接部分（150）布置在金属层上。金属层用作用于布置焊料连接部的种子层。焊料（160）形成在焊料连接部上。

10. 发明公开

EP2856502A4 SEMICONDUCTOR PACKAGE SUBSTRATE, PACKAGE SYSTEM USING THE SAME AND METHOD FOR MANUFACTURING THEREOF 有权转让
标题翻译： HALBLEITERVERKAPSELUNGSSUBSTRAT，封装井井有条其制造
公开(公告)号：EP2856502A4
公开(公告)日：2015-08-05
申请号：EP13793826
申请日：2013-05-24
申请人： LG INNOTEK CO LTD
发明人： RYU SUNG WUK , KIM DONG SUN , SHIN SEUNG YUL
IPC分类号： H01L23/12 , H01L23/15
CPC分类号： H01L23/12 , H01L21/4846 , H01L23/49816 , H01L23/49822 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0657 , H01L2224/131 , H01L2224/13147 , H01L2224/134 , H01L2224/16238 , H01L2224/81192 , H01L2224/81447 , H01L2225/06517 , H01L2225/06562 , H01L2924/01029 , H01L2924/014 , H01L2924/12042 , H01L2924/151 , H01L2924/15787 , H05K1/181 , H01L2924/00
摘要： A semiconductor package substrate includes an insulating substrate, a circuit pattern on the insulating substrate, a protective layer formed on the insulating substrate to cover the circuit pattern on the insulating substrate, a pad formed on the protective layer while protruding from a surface of the protective layer, and an adhesive member on the pad.

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